1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
37
38 #include "i2c-stm32.h"
39
40 /* STM32F7 I2C registers */
41 #define STM32F7_I2C_CR1 0x00
42 #define STM32F7_I2C_CR2 0x04
43 #define STM32F7_I2C_OAR1 0x08
44 #define STM32F7_I2C_OAR2 0x0C
45 #define STM32F7_I2C_PECR 0x20
46 #define STM32F7_I2C_TIMINGR 0x10
47 #define STM32F7_I2C_ISR 0x18
48 #define STM32F7_I2C_ICR 0x1C
49 #define STM32F7_I2C_RXDR 0x24
50 #define STM32F7_I2C_TXDR 0x28
51
52 /* STM32F7 I2C control 1 */
53 #define STM32F7_I2C_CR1_PECEN BIT(23)
54 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
55 #define STM32F7_I2C_CR1_WUPEN BIT(18)
56 #define STM32F7_I2C_CR1_SBC BIT(16)
57 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
58 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
59 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
60 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
61 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
62 #define STM32F7_I2C_CR1_ERRIE BIT(7)
63 #define STM32F7_I2C_CR1_TCIE BIT(6)
64 #define STM32F7_I2C_CR1_STOPIE BIT(5)
65 #define STM32F7_I2C_CR1_NACKIE BIT(4)
66 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
67 #define STM32F7_I2C_CR1_RXIE BIT(2)
68 #define STM32F7_I2C_CR1_TXIE BIT(1)
69 #define STM32F7_I2C_CR1_PE BIT(0)
70 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
71 | STM32F7_I2C_CR1_TCIE \
72 | STM32F7_I2C_CR1_STOPIE \
73 | STM32F7_I2C_CR1_NACKIE \
74 | STM32F7_I2C_CR1_RXIE \
75 | STM32F7_I2C_CR1_TXIE)
76 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
77 | STM32F7_I2C_CR1_STOPIE \
78 | STM32F7_I2C_CR1_NACKIE \
79 | STM32F7_I2C_CR1_RXIE \
80 | STM32F7_I2C_CR1_TXIE)
81
82 /* STM32F7 I2C control 2 */
83 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
84 #define STM32F7_I2C_CR2_RELOAD BIT(24)
85 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
86 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
87 #define STM32F7_I2C_CR2_NACK BIT(15)
88 #define STM32F7_I2C_CR2_STOP BIT(14)
89 #define STM32F7_I2C_CR2_START BIT(13)
90 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
91 #define STM32F7_I2C_CR2_ADD10 BIT(11)
92 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
93 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
94 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
95 STM32F7_I2C_CR2_SADD10_MASK))
96 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
97 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
98
99 /* STM32F7 I2C Own Address 1 */
100 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
101 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
102 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
103 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
104 STM32F7_I2C_OAR1_OA1_10_MASK))
105 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
106 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
107 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
108 | STM32F7_I2C_OAR1_OA1_10_MASK \
109 | STM32F7_I2C_OAR1_OA1EN \
110 | STM32F7_I2C_OAR1_OA1MODE)
111
112 /* STM32F7 I2C Own Address 2 */
113 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
114 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
115 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
116 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
117 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
118 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
119 | STM32F7_I2C_OAR2_OA2_7_MASK \
120 | STM32F7_I2C_OAR2_OA2EN)
121
122 /* STM32F7 I2C Interrupt Status */
123 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
124 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
125 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
126 #define STM32F7_I2C_ISR_DIR BIT(16)
127 #define STM32F7_I2C_ISR_BUSY BIT(15)
128 #define STM32F7_I2C_ISR_PECERR BIT(11)
129 #define STM32F7_I2C_ISR_ARLO BIT(9)
130 #define STM32F7_I2C_ISR_BERR BIT(8)
131 #define STM32F7_I2C_ISR_TCR BIT(7)
132 #define STM32F7_I2C_ISR_TC BIT(6)
133 #define STM32F7_I2C_ISR_STOPF BIT(5)
134 #define STM32F7_I2C_ISR_NACKF BIT(4)
135 #define STM32F7_I2C_ISR_ADDR BIT(3)
136 #define STM32F7_I2C_ISR_RXNE BIT(2)
137 #define STM32F7_I2C_ISR_TXIS BIT(1)
138 #define STM32F7_I2C_ISR_TXE BIT(0)
139
140 /* STM32F7 I2C Interrupt Clear */
141 #define STM32F7_I2C_ICR_PECCF BIT(11)
142 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
143 #define STM32F7_I2C_ICR_BERRCF BIT(8)
144 #define STM32F7_I2C_ICR_STOPCF BIT(5)
145 #define STM32F7_I2C_ICR_NACKCF BIT(4)
146 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
147
148 /* STM32F7 I2C Timing */
149 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
150 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
151 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
152 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
153 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
154
155 #define STM32F7_I2C_MAX_LEN 0xff
156 #define STM32F7_I2C_DMA_LEN_MIN 0x16
157 enum {
158 STM32F7_SLAVE_HOSTNOTIFY,
159 STM32F7_SLAVE_7_10_BITS_ADDR,
160 STM32F7_SLAVE_7_BITS_ADDR,
161 STM32F7_I2C_MAX_SLAVE
162 };
163
164 #define STM32F7_I2C_DNF_DEFAULT 0
165 #define STM32F7_I2C_DNF_MAX 15
166
167 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
168 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
169 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
170
171 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
172 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
173
174 #define STM32F7_PRESC_MAX BIT(4)
175 #define STM32F7_SCLDEL_MAX BIT(4)
176 #define STM32F7_SDADEL_MAX BIT(4)
177 #define STM32F7_SCLH_MAX BIT(8)
178 #define STM32F7_SCLL_MAX BIT(8)
179
180 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
181
182 /**
183 * struct stm32f7_i2c_regs - i2c f7 registers backup
184 * @cr1: Control register 1
185 * @cr2: Control register 2
186 * @oar1: Own address 1 register
187 * @oar2: Own address 2 register
188 * @tmgr: Timing register
189 */
190 struct stm32f7_i2c_regs {
191 u32 cr1;
192 u32 cr2;
193 u32 oar1;
194 u32 oar2;
195 u32 tmgr;
196 };
197
198 /**
199 * struct stm32f7_i2c_spec - private i2c specification timing
200 * @rate: I2C bus speed (Hz)
201 * @fall_max: Max fall time of both SDA and SCL signals (ns)
202 * @rise_max: Max rise time of both SDA and SCL signals (ns)
203 * @hddat_min: Min data hold time (ns)
204 * @vddat_max: Max data valid time (ns)
205 * @sudat_min: Min data setup time (ns)
206 * @l_min: Min low period of the SCL clock (ns)
207 * @h_min: Min high period of the SCL clock (ns)
208 */
209 struct stm32f7_i2c_spec {
210 u32 rate;
211 u32 fall_max;
212 u32 rise_max;
213 u32 hddat_min;
214 u32 vddat_max;
215 u32 sudat_min;
216 u32 l_min;
217 u32 h_min;
218 };
219
220 /**
221 * struct stm32f7_i2c_setup - private I2C timing setup parameters
222 * @speed_freq: I2C speed frequency (Hz)
223 * @clock_src: I2C clock source frequency (Hz)
224 * @rise_time: Rise time (ns)
225 * @fall_time: Fall time (ns)
226 * @dnf: Digital filter coefficient (0-16)
227 * @analog_filter: Analog filter delay (On/Off)
228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
229 */
230 struct stm32f7_i2c_setup {
231 u32 speed_freq;
232 u32 clock_src;
233 u32 rise_time;
234 u32 fall_time;
235 u8 dnf;
236 bool analog_filter;
237 u32 fmp_clr_offset;
238 };
239
240 /**
241 * struct stm32f7_i2c_timings - private I2C output parameters
242 * @node: List entry
243 * @presc: Prescaler value
244 * @scldel: Data setup time
245 * @sdadel: Data hold time
246 * @sclh: SCL high period (master mode)
247 * @scll: SCL low period (master mode)
248 */
249 struct stm32f7_i2c_timings {
250 struct list_head node;
251 u8 presc;
252 u8 scldel;
253 u8 sdadel;
254 u8 sclh;
255 u8 scll;
256 };
257
258 /**
259 * struct stm32f7_i2c_msg - client specific data
260 * @addr: 8-bit or 10-bit slave addr, including r/w bit
261 * @count: number of bytes to be transferred
262 * @buf: data buffer
263 * @result: result of the transfer
264 * @stop: last I2C msg to be sent, i.e. STOP to be generated
265 * @smbus: boolean to know if the I2C IP is used in SMBus mode
266 * @size: type of SMBus protocol
267 * @read_write: direction of SMBus protocol
268 * SMBus block read and SMBus block write - block read process call protocols
269 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
270 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
271 * This buffer has to be 32-bit aligned to be compliant with memory address
272 * register in DMA mode.
273 */
274 struct stm32f7_i2c_msg {
275 u16 addr;
276 u32 count;
277 u8 *buf;
278 int result;
279 bool stop;
280 bool smbus;
281 int size;
282 char read_write;
283 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
284 };
285
286 /**
287 * struct stm32f7_i2c_dev - private data of the controller
288 * @adap: I2C adapter for this controller
289 * @dev: device for this controller
290 * @base: virtual memory area
291 * @complete: completion of I2C message
292 * @clk: hw i2c clock
293 * @bus_rate: I2C clock frequency of the controller
294 * @msg: Pointer to data to be written
295 * @msg_num: number of I2C messages to be executed
296 * @msg_id: message identifiant
297 * @f7_msg: customized i2c msg for driver usage
298 * @setup: I2C timing input setup
299 * @timing: I2C computed timings
300 * @slave: list of slave devices registered on the I2C bus
301 * @slave_running: slave device currently used
302 * @backup_regs: backup of i2c controller registers (for suspend/resume)
303 * @slave_dir: transfer direction for the current slave device
304 * @master_mode: boolean to know in which mode the I2C is running (master or
305 * slave)
306 * @dma: dma data
307 * @use_dma: boolean to know if dma is used in the current transfer
308 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
309 * @fmp_sreg: register address for setting Fast Mode Plus bits
310 * @fmp_creg: register address for clearing Fast Mode Plus bits
311 * @fmp_mask: mask for Fast Mode Plus bits in set register
312 * @wakeup_src: boolean to know if the device is a wakeup source
313 * @smbus_mode: states that the controller is configured in SMBus mode
314 * @host_notify_client: SMBus host-notify client
315 */
316 struct stm32f7_i2c_dev {
317 struct i2c_adapter adap;
318 struct device *dev;
319 void __iomem *base;
320 struct completion complete;
321 struct clk *clk;
322 unsigned int bus_rate;
323 struct i2c_msg *msg;
324 unsigned int msg_num;
325 unsigned int msg_id;
326 struct stm32f7_i2c_msg f7_msg;
327 struct stm32f7_i2c_setup setup;
328 struct stm32f7_i2c_timings timing;
329 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
330 struct i2c_client *slave_running;
331 struct stm32f7_i2c_regs backup_regs;
332 u32 slave_dir;
333 bool master_mode;
334 struct stm32_i2c_dma *dma;
335 bool use_dma;
336 struct regmap *regmap;
337 u32 fmp_sreg;
338 u32 fmp_creg;
339 u32 fmp_mask;
340 bool wakeup_src;
341 bool smbus_mode;
342 struct i2c_client *host_notify_client;
343 };
344
345 /*
346 * All these values are coming from I2C Specification, Version 6.0, 4th of
347 * April 2014.
348 *
349 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
350 * and Fast-mode Plus I2C-bus devices
351 */
352 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
353 {
354 .rate = I2C_MAX_STANDARD_MODE_FREQ,
355 .fall_max = 300,
356 .rise_max = 1000,
357 .hddat_min = 0,
358 .vddat_max = 3450,
359 .sudat_min = 250,
360 .l_min = 4700,
361 .h_min = 4000,
362 },
363 {
364 .rate = I2C_MAX_FAST_MODE_FREQ,
365 .fall_max = 300,
366 .rise_max = 300,
367 .hddat_min = 0,
368 .vddat_max = 900,
369 .sudat_min = 100,
370 .l_min = 1300,
371 .h_min = 600,
372 },
373 {
374 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
375 .fall_max = 100,
376 .rise_max = 120,
377 .hddat_min = 0,
378 .vddat_max = 450,
379 .sudat_min = 50,
380 .l_min = 500,
381 .h_min = 260,
382 },
383 };
384
385 static const struct stm32f7_i2c_setup stm32f7_setup = {
386 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
387 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
388 .dnf = STM32F7_I2C_DNF_DEFAULT,
389 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
390 };
391
392 static const struct stm32f7_i2c_setup stm32mp15_setup = {
393 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
394 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
395 .dnf = STM32F7_I2C_DNF_DEFAULT,
396 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
397 .fmp_clr_offset = 0x40,
398 };
399
stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)400 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
401 {
402 writel_relaxed(readl_relaxed(reg) | mask, reg);
403 }
404
stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)405 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
406 {
407 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
408 }
409
stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)410 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
411 {
412 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
413 }
414
stm32f7_get_specs(u32 rate)415 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
416 {
417 int i;
418
419 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
420 if (rate <= stm32f7_i2c_specs[i].rate)
421 return &stm32f7_i2c_specs[i];
422
423 return ERR_PTR(-EINVAL);
424 }
425
426 #define RATE_MIN(rate) ((rate) * 8 / 10)
stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, struct stm32f7_i2c_setup *setup, struct stm32f7_i2c_timings *output)427 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
428 struct stm32f7_i2c_setup *setup,
429 struct stm32f7_i2c_timings *output)
430 {
431 struct stm32f7_i2c_spec *specs;
432 u32 p_prev = STM32F7_PRESC_MAX;
433 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
434 setup->clock_src);
435 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
436 setup->speed_freq);
437 u32 clk_error_prev = i2cbus;
438 u32 tsync;
439 u32 af_delay_min, af_delay_max;
440 u32 dnf_delay;
441 u32 clk_min, clk_max;
442 int sdadel_min, sdadel_max;
443 int scldel_min;
444 struct stm32f7_i2c_timings *v, *_v, *s;
445 struct list_head solutions;
446 u16 p, l, a, h;
447 int ret = 0;
448
449 specs = stm32f7_get_specs(setup->speed_freq);
450 if (specs == ERR_PTR(-EINVAL)) {
451 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
452 setup->speed_freq);
453 return -EINVAL;
454 }
455
456 if ((setup->rise_time > specs->rise_max) ||
457 (setup->fall_time > specs->fall_max)) {
458 dev_err(i2c_dev->dev,
459 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
460 setup->rise_time, specs->rise_max,
461 setup->fall_time, specs->fall_max);
462 return -EINVAL;
463 }
464
465 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
466 dev_err(i2c_dev->dev,
467 "DNF out of bound %d/%d\n",
468 setup->dnf, STM32F7_I2C_DNF_MAX);
469 return -EINVAL;
470 }
471
472 /* Analog and Digital Filters */
473 af_delay_min =
474 (setup->analog_filter ?
475 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
476 af_delay_max =
477 (setup->analog_filter ?
478 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
479 dnf_delay = setup->dnf * i2cclk;
480
481 sdadel_min = specs->hddat_min + setup->fall_time -
482 af_delay_min - (setup->dnf + 3) * i2cclk;
483
484 sdadel_max = specs->vddat_max - setup->rise_time -
485 af_delay_max - (setup->dnf + 4) * i2cclk;
486
487 scldel_min = setup->rise_time + specs->sudat_min;
488
489 if (sdadel_min < 0)
490 sdadel_min = 0;
491 if (sdadel_max < 0)
492 sdadel_max = 0;
493
494 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
495 sdadel_min, sdadel_max, scldel_min);
496
497 INIT_LIST_HEAD(&solutions);
498 /* Compute possible values for PRESC, SCLDEL and SDADEL */
499 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
500 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
501 u32 scldel = (l + 1) * (p + 1) * i2cclk;
502
503 if (scldel < scldel_min)
504 continue;
505
506 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
507 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
508
509 if (((sdadel >= sdadel_min) &&
510 (sdadel <= sdadel_max)) &&
511 (p != p_prev)) {
512 v = kmalloc(sizeof(*v), GFP_KERNEL);
513 if (!v) {
514 ret = -ENOMEM;
515 goto exit;
516 }
517
518 v->presc = p;
519 v->scldel = l;
520 v->sdadel = a;
521 p_prev = p;
522
523 list_add_tail(&v->node,
524 &solutions);
525 break;
526 }
527 }
528
529 if (p_prev == p)
530 break;
531 }
532 }
533
534 if (list_empty(&solutions)) {
535 dev_err(i2c_dev->dev, "no Prescaler solution\n");
536 ret = -EPERM;
537 goto exit;
538 }
539
540 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
541 s = NULL;
542 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
543 clk_min = NSEC_PER_SEC / setup->speed_freq;
544
545 /*
546 * Among Prescaler possibilities discovered above figures out SCL Low
547 * and High Period. Provided:
548 * - SCL Low Period has to be higher than SCL Clock Low Period
549 * defined by I2C Specification. I2C Clock has to be lower than
550 * (SCL Low Period - Analog/Digital filters) / 4.
551 * - SCL High Period has to be lower than SCL Clock High Period
552 * defined by I2C Specification
553 * - I2C Clock has to be lower than SCL High Period
554 */
555 list_for_each_entry(v, &solutions, node) {
556 u32 prescaler = (v->presc + 1) * i2cclk;
557
558 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
559 u32 tscl_l = (l + 1) * prescaler + tsync;
560
561 if ((tscl_l < specs->l_min) ||
562 (i2cclk >=
563 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
564 continue;
565 }
566
567 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
568 u32 tscl_h = (h + 1) * prescaler + tsync;
569 u32 tscl = tscl_l + tscl_h +
570 setup->rise_time + setup->fall_time;
571
572 if ((tscl >= clk_min) && (tscl <= clk_max) &&
573 (tscl_h >= specs->h_min) &&
574 (i2cclk < tscl_h)) {
575 int clk_error = tscl - i2cbus;
576
577 if (clk_error < 0)
578 clk_error = -clk_error;
579
580 if (clk_error < clk_error_prev) {
581 clk_error_prev = clk_error;
582 v->scll = l;
583 v->sclh = h;
584 s = v;
585 }
586 }
587 }
588 }
589 }
590
591 if (!s) {
592 dev_err(i2c_dev->dev, "no solution at all\n");
593 ret = -EPERM;
594 goto exit;
595 }
596
597 output->presc = s->presc;
598 output->scldel = s->scldel;
599 output->sdadel = s->sdadel;
600 output->scll = s->scll;
601 output->sclh = s->sclh;
602
603 dev_dbg(i2c_dev->dev,
604 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
605 output->presc,
606 output->scldel, output->sdadel,
607 output->scll, output->sclh);
608
609 exit:
610 /* Release list and memory */
611 list_for_each_entry_safe(v, _v, &solutions, node) {
612 list_del(&v->node);
613 kfree(v);
614 }
615
616 return ret;
617 }
618
stm32f7_get_lower_rate(u32 rate)619 static u32 stm32f7_get_lower_rate(u32 rate)
620 {
621 int i = ARRAY_SIZE(stm32f7_i2c_specs);
622
623 while (--i)
624 if (stm32f7_i2c_specs[i].rate < rate)
625 break;
626
627 return stm32f7_i2c_specs[i].rate;
628 }
629
stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, struct stm32f7_i2c_setup *setup)630 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
631 struct stm32f7_i2c_setup *setup)
632 {
633 struct i2c_timings timings, *t = &timings;
634 int ret = 0;
635
636 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
637 t->scl_rise_ns = i2c_dev->setup.rise_time;
638 t->scl_fall_ns = i2c_dev->setup.fall_time;
639
640 i2c_parse_fw_timings(i2c_dev->dev, t, false);
641
642 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
643 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
644 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
645 return -EINVAL;
646 }
647
648 setup->speed_freq = t->bus_freq_hz;
649 i2c_dev->setup.rise_time = t->scl_rise_ns;
650 i2c_dev->setup.fall_time = t->scl_fall_ns;
651 setup->clock_src = clk_get_rate(i2c_dev->clk);
652
653 if (!setup->clock_src) {
654 dev_err(i2c_dev->dev, "clock rate is 0\n");
655 return -EINVAL;
656 }
657
658 do {
659 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
660 &i2c_dev->timing);
661 if (ret) {
662 dev_err(i2c_dev->dev,
663 "failed to compute I2C timings.\n");
664 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
665 break;
666 setup->speed_freq =
667 stm32f7_get_lower_rate(setup->speed_freq);
668 dev_warn(i2c_dev->dev,
669 "downgrade I2C Speed Freq to (%i)\n",
670 setup->speed_freq);
671 }
672 } while (ret);
673
674 if (ret) {
675 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
676 return ret;
677 }
678
679 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
680 setup->speed_freq, setup->clock_src);
681 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
682 setup->rise_time, setup->fall_time);
683 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
684 (setup->analog_filter ? "On" : "Off"), setup->dnf);
685
686 i2c_dev->bus_rate = setup->speed_freq;
687
688 return 0;
689 }
690
stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)691 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
692 {
693 void __iomem *base = i2c_dev->base;
694 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
695
696 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
697 }
698
stm32f7_i2c_dma_callback(void *arg)699 static void stm32f7_i2c_dma_callback(void *arg)
700 {
701 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
702 struct stm32_i2c_dma *dma = i2c_dev->dma;
703 struct device *dev = dma->chan_using->device->dev;
704
705 stm32f7_i2c_disable_dma_req(i2c_dev);
706 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
707 complete(&dma->dma_complete);
708 }
709
stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)710 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
711 {
712 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
713 u32 timing = 0;
714
715 /* Timing settings */
716 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
717 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
718 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
719 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
720 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
721 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
722
723 /* Enable I2C */
724 if (i2c_dev->setup.analog_filter)
725 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
726 STM32F7_I2C_CR1_ANFOFF);
727 else
728 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
729 STM32F7_I2C_CR1_ANFOFF);
730
731 /* Program the Digital Filter */
732 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
733 STM32F7_I2C_CR1_DNF_MASK);
734 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
735 STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
736
737 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
738 STM32F7_I2C_CR1_PE);
739 }
740
stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)741 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
742 {
743 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
744 void __iomem *base = i2c_dev->base;
745
746 if (f7_msg->count) {
747 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
748 f7_msg->count--;
749 }
750 }
751
stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)752 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
753 {
754 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
755 void __iomem *base = i2c_dev->base;
756
757 if (f7_msg->count) {
758 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
759 f7_msg->count--;
760 } else {
761 /* Flush RX buffer has no data is expected */
762 readb_relaxed(base + STM32F7_I2C_RXDR);
763 }
764 }
765
stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)766 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
767 {
768 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
769 u32 cr2;
770
771 if (i2c_dev->use_dma)
772 f7_msg->count -= STM32F7_I2C_MAX_LEN;
773
774 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
775
776 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
777 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
778 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
779 } else {
780 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
781 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
782 }
783
784 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
785 }
786
stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)787 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
788 {
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
790 u32 cr2;
791 u8 *val;
792
793 /*
794 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
795 * data received inform us how many data will follow.
796 */
797 stm32f7_i2c_read_rx_data(i2c_dev);
798
799 /*
800 * Update NBYTES with the value read to continue the transfer
801 */
802 val = f7_msg->buf - sizeof(u8);
803 f7_msg->count = *val;
804 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
805 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
806 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
807 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
808 }
809
stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)810 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
811 {
812 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
813
814 dev_info(i2c_dev->dev, "Trying to recover bus\n");
815
816 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
817 STM32F7_I2C_CR1_PE);
818
819 stm32f7_i2c_hw_config(i2c_dev);
820
821 return 0;
822 }
823
stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)824 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
825 {
826 u32 status;
827 int ret;
828
829 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
830 status,
831 !(status & STM32F7_I2C_ISR_BUSY),
832 10, 1000);
833 if (!ret)
834 return 0;
835
836 dev_info(i2c_dev->dev, "bus busy\n");
837
838 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
839 if (ret) {
840 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
841 return ret;
842 }
843
844 return -EBUSY;
845 }
846
stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, struct i2c_msg *msg)847 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
848 struct i2c_msg *msg)
849 {
850 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
851 void __iomem *base = i2c_dev->base;
852 u32 cr1, cr2;
853 int ret;
854
855 f7_msg->addr = msg->addr;
856 f7_msg->buf = msg->buf;
857 f7_msg->count = msg->len;
858 f7_msg->result = 0;
859 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
860
861 reinit_completion(&i2c_dev->complete);
862
863 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
864 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
865
866 /* Set transfer direction */
867 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
868 if (msg->flags & I2C_M_RD)
869 cr2 |= STM32F7_I2C_CR2_RD_WRN;
870
871 /* Set slave address */
872 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
873 if (msg->flags & I2C_M_TEN) {
874 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
875 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
876 cr2 |= STM32F7_I2C_CR2_ADD10;
877 } else {
878 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
879 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
880 }
881
882 /* Set nb bytes to transfer and reload if needed */
883 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
884 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
885 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
886 cr2 |= STM32F7_I2C_CR2_RELOAD;
887 } else {
888 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
889 }
890
891 /* Enable NACK, STOP, error and transfer complete interrupts */
892 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
893 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
894
895 /* Clear DMA req and TX/RX interrupt */
896 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
897 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
898
899 /* Configure DMA or enable RX/TX interrupt */
900 i2c_dev->use_dma = false;
901 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
902 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
903 msg->flags & I2C_M_RD,
904 f7_msg->count, f7_msg->buf,
905 stm32f7_i2c_dma_callback,
906 i2c_dev);
907 if (!ret)
908 i2c_dev->use_dma = true;
909 else
910 dev_warn(i2c_dev->dev, "can't use DMA\n");
911 }
912
913 if (!i2c_dev->use_dma) {
914 if (msg->flags & I2C_M_RD)
915 cr1 |= STM32F7_I2C_CR1_RXIE;
916 else
917 cr1 |= STM32F7_I2C_CR1_TXIE;
918 } else {
919 if (msg->flags & I2C_M_RD)
920 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
921 else
922 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
923 }
924
925 /* Configure Start/Repeated Start */
926 cr2 |= STM32F7_I2C_CR2_START;
927
928 i2c_dev->master_mode = true;
929
930 /* Write configurations registers */
931 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
932 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
933 }
934
stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, unsigned short flags, u8 command, union i2c_smbus_data *data)935 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
936 unsigned short flags, u8 command,
937 union i2c_smbus_data *data)
938 {
939 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
940 struct device *dev = i2c_dev->dev;
941 void __iomem *base = i2c_dev->base;
942 u32 cr1, cr2;
943 int i, ret;
944
945 f7_msg->result = 0;
946 reinit_completion(&i2c_dev->complete);
947
948 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
949 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
950
951 /* Set transfer direction */
952 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
953 if (f7_msg->read_write)
954 cr2 |= STM32F7_I2C_CR2_RD_WRN;
955
956 /* Set slave address */
957 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
958 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
959
960 f7_msg->smbus_buf[0] = command;
961 switch (f7_msg->size) {
962 case I2C_SMBUS_QUICK:
963 f7_msg->stop = true;
964 f7_msg->count = 0;
965 break;
966 case I2C_SMBUS_BYTE:
967 f7_msg->stop = true;
968 f7_msg->count = 1;
969 break;
970 case I2C_SMBUS_BYTE_DATA:
971 if (f7_msg->read_write) {
972 f7_msg->stop = false;
973 f7_msg->count = 1;
974 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
975 } else {
976 f7_msg->stop = true;
977 f7_msg->count = 2;
978 f7_msg->smbus_buf[1] = data->byte;
979 }
980 break;
981 case I2C_SMBUS_WORD_DATA:
982 if (f7_msg->read_write) {
983 f7_msg->stop = false;
984 f7_msg->count = 1;
985 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
986 } else {
987 f7_msg->stop = true;
988 f7_msg->count = 3;
989 f7_msg->smbus_buf[1] = data->word & 0xff;
990 f7_msg->smbus_buf[2] = data->word >> 8;
991 }
992 break;
993 case I2C_SMBUS_BLOCK_DATA:
994 if (f7_msg->read_write) {
995 f7_msg->stop = false;
996 f7_msg->count = 1;
997 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
998 } else {
999 f7_msg->stop = true;
1000 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1001 !data->block[0]) {
1002 dev_err(dev, "Invalid block write size %d\n",
1003 data->block[0]);
1004 return -EINVAL;
1005 }
1006 f7_msg->count = data->block[0] + 2;
1007 for (i = 1; i < f7_msg->count; i++)
1008 f7_msg->smbus_buf[i] = data->block[i - 1];
1009 }
1010 break;
1011 case I2C_SMBUS_PROC_CALL:
1012 f7_msg->stop = false;
1013 f7_msg->count = 3;
1014 f7_msg->smbus_buf[1] = data->word & 0xff;
1015 f7_msg->smbus_buf[2] = data->word >> 8;
1016 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1017 f7_msg->read_write = I2C_SMBUS_READ;
1018 break;
1019 case I2C_SMBUS_BLOCK_PROC_CALL:
1020 f7_msg->stop = false;
1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1022 dev_err(dev, "Invalid block write size %d\n",
1023 data->block[0]);
1024 return -EINVAL;
1025 }
1026 f7_msg->count = data->block[0] + 2;
1027 for (i = 1; i < f7_msg->count; i++)
1028 f7_msg->smbus_buf[i] = data->block[i - 1];
1029 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1030 f7_msg->read_write = I2C_SMBUS_READ;
1031 break;
1032 case I2C_SMBUS_I2C_BLOCK_DATA:
1033 /* Rely on emulated i2c transfer (through master_xfer) */
1034 return -EOPNOTSUPP;
1035 default:
1036 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1037 return -EOPNOTSUPP;
1038 }
1039
1040 f7_msg->buf = f7_msg->smbus_buf;
1041
1042 /* Configure PEC */
1043 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1044 cr1 |= STM32F7_I2C_CR1_PECEN;
1045 if (!f7_msg->read_write) {
1046 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1047 f7_msg->count++;
1048 }
1049 } else {
1050 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1051 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1052 }
1053
1054 /* Set number of bytes to be transferred */
1055 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1056 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1057
1058 /* Enable NACK, STOP, error and transfer complete interrupts */
1059 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1060 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1061
1062 /* Clear DMA req and TX/RX interrupt */
1063 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1064 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1065
1066 /* Configure DMA or enable RX/TX interrupt */
1067 i2c_dev->use_dma = false;
1068 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1069 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1070 cr2 & STM32F7_I2C_CR2_RD_WRN,
1071 f7_msg->count, f7_msg->buf,
1072 stm32f7_i2c_dma_callback,
1073 i2c_dev);
1074 if (!ret)
1075 i2c_dev->use_dma = true;
1076 else
1077 dev_warn(i2c_dev->dev, "can't use DMA\n");
1078 }
1079
1080 if (!i2c_dev->use_dma) {
1081 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1082 cr1 |= STM32F7_I2C_CR1_RXIE;
1083 else
1084 cr1 |= STM32F7_I2C_CR1_TXIE;
1085 } else {
1086 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1087 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1088 else
1089 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1090 }
1091
1092 /* Set Start bit */
1093 cr2 |= STM32F7_I2C_CR2_START;
1094
1095 i2c_dev->master_mode = true;
1096
1097 /* Write configurations registers */
1098 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1099 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1100
1101 return 0;
1102 }
1103
stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)1104 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1105 {
1106 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1107 void __iomem *base = i2c_dev->base;
1108 u32 cr1, cr2;
1109 int ret;
1110
1111 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1112 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1113
1114 /* Set transfer direction */
1115 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1116
1117 switch (f7_msg->size) {
1118 case I2C_SMBUS_BYTE_DATA:
1119 f7_msg->count = 1;
1120 break;
1121 case I2C_SMBUS_WORD_DATA:
1122 case I2C_SMBUS_PROC_CALL:
1123 f7_msg->count = 2;
1124 break;
1125 case I2C_SMBUS_BLOCK_DATA:
1126 case I2C_SMBUS_BLOCK_PROC_CALL:
1127 f7_msg->count = 1;
1128 cr2 |= STM32F7_I2C_CR2_RELOAD;
1129 break;
1130 }
1131
1132 f7_msg->buf = f7_msg->smbus_buf;
1133 f7_msg->stop = true;
1134
1135 /* Add one byte for PEC if needed */
1136 if (cr1 & STM32F7_I2C_CR1_PECEN) {
1137 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1138 f7_msg->count++;
1139 }
1140
1141 /* Set number of bytes to be transferred */
1142 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1143 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1144
1145 /*
1146 * Configure RX/TX interrupt:
1147 */
1148 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1149 cr1 |= STM32F7_I2C_CR1_RXIE;
1150
1151 /*
1152 * Configure DMA or enable RX/TX interrupt:
1153 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1154 * dma as we don't know in advance how many data will be received
1155 */
1156 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1157 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1158
1159 i2c_dev->use_dma = false;
1160 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1161 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1162 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1163 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1164 cr2 & STM32F7_I2C_CR2_RD_WRN,
1165 f7_msg->count, f7_msg->buf,
1166 stm32f7_i2c_dma_callback,
1167 i2c_dev);
1168
1169 if (!ret)
1170 i2c_dev->use_dma = true;
1171 else
1172 dev_warn(i2c_dev->dev, "can't use DMA\n");
1173 }
1174
1175 if (!i2c_dev->use_dma)
1176 cr1 |= STM32F7_I2C_CR1_RXIE;
1177 else
1178 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1179
1180 /* Configure Repeated Start */
1181 cr2 |= STM32F7_I2C_CR2_START;
1182
1183 /* Write configurations registers */
1184 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1185 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1186 }
1187
stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)1188 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1189 {
1190 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1191 u8 count, internal_pec, received_pec;
1192
1193 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1194
1195 switch (f7_msg->size) {
1196 case I2C_SMBUS_BYTE:
1197 case I2C_SMBUS_BYTE_DATA:
1198 received_pec = f7_msg->smbus_buf[1];
1199 break;
1200 case I2C_SMBUS_WORD_DATA:
1201 case I2C_SMBUS_PROC_CALL:
1202 received_pec = f7_msg->smbus_buf[2];
1203 break;
1204 case I2C_SMBUS_BLOCK_DATA:
1205 case I2C_SMBUS_BLOCK_PROC_CALL:
1206 count = f7_msg->smbus_buf[0];
1207 received_pec = f7_msg->smbus_buf[count];
1208 break;
1209 default:
1210 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1211 return -EINVAL;
1212 }
1213
1214 if (internal_pec != received_pec) {
1215 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1216 internal_pec, received_pec);
1217 return -EBADMSG;
1218 }
1219
1220 return 0;
1221 }
1222
stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)1223 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1224 {
1225 u32 addr;
1226
1227 if (!slave)
1228 return false;
1229
1230 if (slave->flags & I2C_CLIENT_TEN) {
1231 /*
1232 * For 10-bit addr, addcode = 11110XY with
1233 * X = Bit 9 of slave address
1234 * Y = Bit 8 of slave address
1235 */
1236 addr = slave->addr >> 8;
1237 addr |= 0x78;
1238 if (addr == addcode)
1239 return true;
1240 } else {
1241 addr = slave->addr & 0x7f;
1242 if (addr == addcode)
1243 return true;
1244 }
1245
1246 return false;
1247 }
1248
stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)1249 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1250 {
1251 struct i2c_client *slave = i2c_dev->slave_running;
1252 void __iomem *base = i2c_dev->base;
1253 u32 mask;
1254 u8 value = 0;
1255
1256 if (i2c_dev->slave_dir) {
1257 /* Notify i2c slave that new read transfer is starting */
1258 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1259
1260 /*
1261 * Disable slave TX config in case of I2C combined message
1262 * (I2C Write followed by I2C Read)
1263 */
1264 mask = STM32F7_I2C_CR2_RELOAD;
1265 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1266 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1267 STM32F7_I2C_CR1_TCIE;
1268 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1269
1270 /* Enable TX empty, STOP, NACK interrupts */
1271 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1272 STM32F7_I2C_CR1_TXIE;
1273 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1274
1275 /* Write 1st data byte */
1276 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1277 } else {
1278 /* Notify i2c slave that new write transfer is starting */
1279 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1280
1281 /* Set reload mode to be able to ACK/NACK each received byte */
1282 mask = STM32F7_I2C_CR2_RELOAD;
1283 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1284
1285 /*
1286 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1287 * Set Slave Byte Control to be able to ACK/NACK each data
1288 * byte received
1289 */
1290 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1291 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1292 STM32F7_I2C_CR1_TCIE;
1293 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1294 }
1295 }
1296
stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)1297 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1298 {
1299 void __iomem *base = i2c_dev->base;
1300 u32 isr, addcode, dir, mask;
1301 int i;
1302
1303 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1304 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1305 dir = isr & STM32F7_I2C_ISR_DIR;
1306
1307 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1308 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1309 i2c_dev->slave_running = i2c_dev->slave[i];
1310 i2c_dev->slave_dir = dir;
1311
1312 /* Start I2C slave processing */
1313 stm32f7_i2c_slave_start(i2c_dev);
1314
1315 /* Clear ADDR flag */
1316 mask = STM32F7_I2C_ICR_ADDRCF;
1317 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1318 break;
1319 }
1320 }
1321 }
1322
stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, struct i2c_client *slave, int *id)1323 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1324 struct i2c_client *slave, int *id)
1325 {
1326 int i;
1327
1328 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1329 if (i2c_dev->slave[i] == slave) {
1330 *id = i;
1331 return 0;
1332 }
1333 }
1334
1335 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1336
1337 return -ENODEV;
1338 }
1339
stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, struct i2c_client *slave, int *id)1340 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1341 struct i2c_client *slave, int *id)
1342 {
1343 struct device *dev = i2c_dev->dev;
1344 int i;
1345
1346 /*
1347 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1348 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1349 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1350 */
1351 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1352 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1353 goto fail;
1354 *id = STM32F7_SLAVE_HOSTNOTIFY;
1355 return 0;
1356 }
1357
1358 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1359 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1360 (slave->flags & I2C_CLIENT_TEN))
1361 continue;
1362 if (!i2c_dev->slave[i]) {
1363 *id = i;
1364 return 0;
1365 }
1366 }
1367
1368 fail:
1369 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1370
1371 return -EINVAL;
1372 }
1373
stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)1374 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1375 {
1376 int i;
1377
1378 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1379 if (i2c_dev->slave[i])
1380 return true;
1381 }
1382
1383 return false;
1384 }
1385
stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)1386 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1387 {
1388 int i, busy;
1389
1390 busy = 0;
1391 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1392 if (i2c_dev->slave[i])
1393 busy++;
1394 }
1395
1396 return i == busy;
1397 }
1398
stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)1399 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1400 {
1401 void __iomem *base = i2c_dev->base;
1402 u32 cr2, status, mask;
1403 u8 val;
1404 int ret;
1405
1406 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1407
1408 /* Slave transmitter mode */
1409 if (status & STM32F7_I2C_ISR_TXIS) {
1410 i2c_slave_event(i2c_dev->slave_running,
1411 I2C_SLAVE_READ_PROCESSED,
1412 &val);
1413
1414 /* Write data byte */
1415 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1416 }
1417
1418 /* Transfer Complete Reload for Slave receiver mode */
1419 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1420 /*
1421 * Read data byte then set NBYTES to receive next byte or NACK
1422 * the current received byte
1423 */
1424 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1425 ret = i2c_slave_event(i2c_dev->slave_running,
1426 I2C_SLAVE_WRITE_RECEIVED,
1427 &val);
1428 if (!ret) {
1429 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1430 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1431 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1432 } else {
1433 mask = STM32F7_I2C_CR2_NACK;
1434 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1435 }
1436 }
1437
1438 /* NACK received */
1439 if (status & STM32F7_I2C_ISR_NACKF) {
1440 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1441 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1442 }
1443
1444 /* STOP received */
1445 if (status & STM32F7_I2C_ISR_STOPF) {
1446 /* Disable interrupts */
1447 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1448
1449 if (i2c_dev->slave_dir) {
1450 /*
1451 * Flush TX buffer in order to not used the byte in
1452 * TXDR for the next transfer
1453 */
1454 mask = STM32F7_I2C_ISR_TXE;
1455 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1456 }
1457
1458 /* Clear STOP flag */
1459 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1460
1461 /* Notify i2c slave that a STOP flag has been detected */
1462 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1463
1464 i2c_dev->slave_running = NULL;
1465 }
1466
1467 /* Address match received */
1468 if (status & STM32F7_I2C_ISR_ADDR)
1469 stm32f7_i2c_slave_addr(i2c_dev);
1470
1471 return IRQ_HANDLED;
1472 }
1473
stm32f7_i2c_isr_event(int irq, void *data)1474 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1475 {
1476 struct stm32f7_i2c_dev *i2c_dev = data;
1477 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1478 struct stm32_i2c_dma *dma = i2c_dev->dma;
1479 void __iomem *base = i2c_dev->base;
1480 u32 status, mask;
1481 int ret = IRQ_HANDLED;
1482
1483 /* Check if the interrupt if for a slave device */
1484 if (!i2c_dev->master_mode) {
1485 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1486 return ret;
1487 }
1488
1489 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1490
1491 /* Tx empty */
1492 if (status & STM32F7_I2C_ISR_TXIS)
1493 stm32f7_i2c_write_tx_data(i2c_dev);
1494
1495 /* RX not empty */
1496 if (status & STM32F7_I2C_ISR_RXNE)
1497 stm32f7_i2c_read_rx_data(i2c_dev);
1498
1499 /* NACK received */
1500 if (status & STM32F7_I2C_ISR_NACKF) {
1501 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1502 __func__, f7_msg->addr);
1503 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1504 if (i2c_dev->use_dma) {
1505 stm32f7_i2c_disable_dma_req(i2c_dev);
1506 dmaengine_terminate_all(dma->chan_using);
1507 }
1508 f7_msg->result = -ENXIO;
1509 }
1510
1511 /* STOP detection flag */
1512 if (status & STM32F7_I2C_ISR_STOPF) {
1513 /* Disable interrupts */
1514 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1515 mask = STM32F7_I2C_XFER_IRQ_MASK;
1516 else
1517 mask = STM32F7_I2C_ALL_IRQ_MASK;
1518 stm32f7_i2c_disable_irq(i2c_dev, mask);
1519
1520 /* Clear STOP flag */
1521 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1522
1523 if (i2c_dev->use_dma && !f7_msg->result) {
1524 ret = IRQ_WAKE_THREAD;
1525 } else {
1526 i2c_dev->master_mode = false;
1527 complete(&i2c_dev->complete);
1528 }
1529 }
1530
1531 /* Transfer complete */
1532 if (status & STM32F7_I2C_ISR_TC) {
1533 if (f7_msg->stop) {
1534 mask = STM32F7_I2C_CR2_STOP;
1535 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1536 } else if (i2c_dev->use_dma && !f7_msg->result) {
1537 ret = IRQ_WAKE_THREAD;
1538 } else if (f7_msg->smbus) {
1539 stm32f7_i2c_smbus_rep_start(i2c_dev);
1540 } else {
1541 i2c_dev->msg_id++;
1542 i2c_dev->msg++;
1543 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1544 }
1545 }
1546
1547 if (status & STM32F7_I2C_ISR_TCR) {
1548 if (f7_msg->smbus)
1549 stm32f7_i2c_smbus_reload(i2c_dev);
1550 else
1551 stm32f7_i2c_reload(i2c_dev);
1552 }
1553
1554 return ret;
1555 }
1556
stm32f7_i2c_isr_event_thread(int irq, void *data)1557 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1558 {
1559 struct stm32f7_i2c_dev *i2c_dev = data;
1560 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1561 struct stm32_i2c_dma *dma = i2c_dev->dma;
1562 u32 status;
1563 int ret;
1564
1565 /*
1566 * Wait for dma transfer completion before sending next message or
1567 * notity the end of xfer to the client
1568 */
1569 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1570 if (!ret) {
1571 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1572 stm32f7_i2c_disable_dma_req(i2c_dev);
1573 dmaengine_terminate_all(dma->chan_using);
1574 f7_msg->result = -ETIMEDOUT;
1575 }
1576
1577 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1578
1579 if (status & STM32F7_I2C_ISR_TC) {
1580 if (f7_msg->smbus) {
1581 stm32f7_i2c_smbus_rep_start(i2c_dev);
1582 } else {
1583 i2c_dev->msg_id++;
1584 i2c_dev->msg++;
1585 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1586 }
1587 } else {
1588 i2c_dev->master_mode = false;
1589 complete(&i2c_dev->complete);
1590 }
1591
1592 return IRQ_HANDLED;
1593 }
1594
stm32f7_i2c_isr_error(int irq, void *data)1595 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1596 {
1597 struct stm32f7_i2c_dev *i2c_dev = data;
1598 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1599 void __iomem *base = i2c_dev->base;
1600 struct device *dev = i2c_dev->dev;
1601 struct stm32_i2c_dma *dma = i2c_dev->dma;
1602 u32 status;
1603
1604 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1605
1606 /* Bus error */
1607 if (status & STM32F7_I2C_ISR_BERR) {
1608 dev_err(dev, "<%s>: Bus error\n", __func__);
1609 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1610 stm32f7_i2c_release_bus(&i2c_dev->adap);
1611 f7_msg->result = -EIO;
1612 }
1613
1614 /* Arbitration loss */
1615 if (status & STM32F7_I2C_ISR_ARLO) {
1616 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1617 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1618 f7_msg->result = -EAGAIN;
1619 }
1620
1621 if (status & STM32F7_I2C_ISR_PECERR) {
1622 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1623 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1624 f7_msg->result = -EINVAL;
1625 }
1626
1627 if (!i2c_dev->slave_running) {
1628 u32 mask;
1629 /* Disable interrupts */
1630 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1631 mask = STM32F7_I2C_XFER_IRQ_MASK;
1632 else
1633 mask = STM32F7_I2C_ALL_IRQ_MASK;
1634 stm32f7_i2c_disable_irq(i2c_dev, mask);
1635 }
1636
1637 /* Disable dma */
1638 if (i2c_dev->use_dma) {
1639 stm32f7_i2c_disable_dma_req(i2c_dev);
1640 dmaengine_terminate_all(dma->chan_using);
1641 }
1642
1643 i2c_dev->master_mode = false;
1644 complete(&i2c_dev->complete);
1645
1646 return IRQ_HANDLED;
1647 }
1648
stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num)1649 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1650 struct i2c_msg msgs[], int num)
1651 {
1652 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1653 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1654 struct stm32_i2c_dma *dma = i2c_dev->dma;
1655 unsigned long time_left;
1656 int ret;
1657
1658 i2c_dev->msg = msgs;
1659 i2c_dev->msg_num = num;
1660 i2c_dev->msg_id = 0;
1661 f7_msg->smbus = false;
1662
1663 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1664 if (ret < 0)
1665 return ret;
1666
1667 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1668 if (ret)
1669 goto pm_free;
1670
1671 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1672
1673 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1674 i2c_dev->adap.timeout);
1675 ret = f7_msg->result;
1676 if (ret) {
1677 /*
1678 * It is possible that some unsent data have already been
1679 * written into TXDR. To avoid sending old data in a
1680 * further transfer, flush TXDR in case of any error
1681 */
1682 writel_relaxed(STM32F7_I2C_ISR_TXE,
1683 i2c_dev->base + STM32F7_I2C_ISR);
1684 goto pm_free;
1685 }
1686
1687 if (!time_left) {
1688 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1689 i2c_dev->msg->addr);
1690 if (i2c_dev->use_dma)
1691 dmaengine_terminate_all(dma->chan_using);
1692 stm32f7_i2c_wait_free_bus(i2c_dev);
1693 ret = -ETIMEDOUT;
1694 }
1695
1696 pm_free:
1697 pm_runtime_mark_last_busy(i2c_dev->dev);
1698 pm_runtime_put_autosuspend(i2c_dev->dev);
1699
1700 return (ret < 0) ? ret : num;
1701 }
1702
stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, unsigned short flags, char read_write, u8 command, int size, union i2c_smbus_data *data)1703 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1704 unsigned short flags, char read_write,
1705 u8 command, int size,
1706 union i2c_smbus_data *data)
1707 {
1708 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1709 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1710 struct stm32_i2c_dma *dma = i2c_dev->dma;
1711 struct device *dev = i2c_dev->dev;
1712 unsigned long timeout;
1713 int i, ret;
1714
1715 f7_msg->addr = addr;
1716 f7_msg->size = size;
1717 f7_msg->read_write = read_write;
1718 f7_msg->smbus = true;
1719
1720 ret = pm_runtime_resume_and_get(dev);
1721 if (ret < 0)
1722 return ret;
1723
1724 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1725 if (ret)
1726 goto pm_free;
1727
1728 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1729 if (ret)
1730 goto pm_free;
1731
1732 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1733 i2c_dev->adap.timeout);
1734 ret = f7_msg->result;
1735 if (ret) {
1736 /*
1737 * It is possible that some unsent data have already been
1738 * written into TXDR. To avoid sending old data in a
1739 * further transfer, flush TXDR in case of any error
1740 */
1741 writel_relaxed(STM32F7_I2C_ISR_TXE,
1742 i2c_dev->base + STM32F7_I2C_ISR);
1743 goto pm_free;
1744 }
1745
1746 if (!timeout) {
1747 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1748 if (i2c_dev->use_dma)
1749 dmaengine_terminate_all(dma->chan_using);
1750 stm32f7_i2c_wait_free_bus(i2c_dev);
1751 ret = -ETIMEDOUT;
1752 goto pm_free;
1753 }
1754
1755 /* Check PEC */
1756 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1757 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1758 if (ret)
1759 goto pm_free;
1760 }
1761
1762 if (read_write && size != I2C_SMBUS_QUICK) {
1763 switch (size) {
1764 case I2C_SMBUS_BYTE:
1765 case I2C_SMBUS_BYTE_DATA:
1766 data->byte = f7_msg->smbus_buf[0];
1767 break;
1768 case I2C_SMBUS_WORD_DATA:
1769 case I2C_SMBUS_PROC_CALL:
1770 data->word = f7_msg->smbus_buf[0] |
1771 (f7_msg->smbus_buf[1] << 8);
1772 break;
1773 case I2C_SMBUS_BLOCK_DATA:
1774 case I2C_SMBUS_BLOCK_PROC_CALL:
1775 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1776 data->block[i] = f7_msg->smbus_buf[i];
1777 break;
1778 default:
1779 dev_err(dev, "Unsupported smbus transaction\n");
1780 ret = -EINVAL;
1781 }
1782 }
1783
1784 pm_free:
1785 pm_runtime_mark_last_busy(dev);
1786 pm_runtime_put_autosuspend(dev);
1787 return ret;
1788 }
1789
stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, bool enable)1790 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1791 bool enable)
1792 {
1793 void __iomem *base = i2c_dev->base;
1794 u32 mask = STM32F7_I2C_CR1_WUPEN;
1795
1796 if (!i2c_dev->wakeup_src)
1797 return;
1798
1799 if (enable) {
1800 device_set_wakeup_enable(i2c_dev->dev, true);
1801 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1802 } else {
1803 device_set_wakeup_enable(i2c_dev->dev, false);
1804 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1805 }
1806 }
1807
stm32f7_i2c_reg_slave(struct i2c_client *slave)1808 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1809 {
1810 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1811 void __iomem *base = i2c_dev->base;
1812 struct device *dev = i2c_dev->dev;
1813 u32 oar1, oar2, mask;
1814 int id, ret;
1815
1816 if (slave->flags & I2C_CLIENT_PEC) {
1817 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1818 return -EINVAL;
1819 }
1820
1821 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1822 dev_err(dev, "Too much slave registered\n");
1823 return -EBUSY;
1824 }
1825
1826 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1827 if (ret)
1828 return ret;
1829
1830 ret = pm_runtime_resume_and_get(dev);
1831 if (ret < 0)
1832 return ret;
1833
1834 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1835 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1836
1837 switch (id) {
1838 case 0:
1839 /* Slave SMBus Host */
1840 i2c_dev->slave[id] = slave;
1841 break;
1842
1843 case 1:
1844 /* Configure Own Address 1 */
1845 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1846 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1847 if (slave->flags & I2C_CLIENT_TEN) {
1848 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1849 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1850 } else {
1851 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1852 }
1853 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1854 i2c_dev->slave[id] = slave;
1855 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1856 break;
1857
1858 case 2:
1859 /* Configure Own Address 2 */
1860 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1861 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1862 if (slave->flags & I2C_CLIENT_TEN) {
1863 ret = -EOPNOTSUPP;
1864 goto pm_free;
1865 }
1866
1867 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1868 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1869 i2c_dev->slave[id] = slave;
1870 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1871 break;
1872
1873 default:
1874 dev_err(dev, "I2C slave id not supported\n");
1875 ret = -ENODEV;
1876 goto pm_free;
1877 }
1878
1879 /* Enable ACK */
1880 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1881
1882 /* Enable Address match interrupt, error interrupt and enable I2C */
1883 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1884 STM32F7_I2C_CR1_PE;
1885 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1886
1887 ret = 0;
1888 pm_free:
1889 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1890 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1891
1892 pm_runtime_mark_last_busy(dev);
1893 pm_runtime_put_autosuspend(dev);
1894
1895 return ret;
1896 }
1897
stm32f7_i2c_unreg_slave(struct i2c_client *slave)1898 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1899 {
1900 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1901 void __iomem *base = i2c_dev->base;
1902 u32 mask;
1903 int id, ret;
1904
1905 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1906 if (ret)
1907 return ret;
1908
1909 WARN_ON(!i2c_dev->slave[id]);
1910
1911 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1912 if (ret < 0)
1913 return ret;
1914
1915 if (id == 1) {
1916 mask = STM32F7_I2C_OAR1_OA1EN;
1917 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1918 } else if (id == 2) {
1919 mask = STM32F7_I2C_OAR2_OA2EN;
1920 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1921 }
1922
1923 i2c_dev->slave[id] = NULL;
1924
1925 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1926 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1927 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1928 }
1929
1930 pm_runtime_mark_last_busy(i2c_dev->dev);
1931 pm_runtime_put_autosuspend(i2c_dev->dev);
1932
1933 return 0;
1934 }
1935
stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, bool enable)1936 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1937 bool enable)
1938 {
1939 int ret;
1940
1941 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1942 IS_ERR_OR_NULL(i2c_dev->regmap))
1943 /* Optional */
1944 return 0;
1945
1946 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1947 ret = regmap_update_bits(i2c_dev->regmap,
1948 i2c_dev->fmp_sreg,
1949 i2c_dev->fmp_mask,
1950 enable ? i2c_dev->fmp_mask : 0);
1951 else
1952 ret = regmap_write(i2c_dev->regmap,
1953 enable ? i2c_dev->fmp_sreg :
1954 i2c_dev->fmp_creg,
1955 i2c_dev->fmp_mask);
1956
1957 return ret;
1958 }
1959
stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, struct stm32f7_i2c_dev *i2c_dev)1960 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1961 struct stm32f7_i2c_dev *i2c_dev)
1962 {
1963 struct device_node *np = pdev->dev.of_node;
1964 int ret;
1965
1966 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1967 if (IS_ERR(i2c_dev->regmap))
1968 /* Optional */
1969 return 0;
1970
1971 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
1972 &i2c_dev->fmp_sreg);
1973 if (ret)
1974 return ret;
1975
1976 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1977 i2c_dev->setup.fmp_clr_offset;
1978
1979 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1980 &i2c_dev->fmp_mask);
1981 }
1982
stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)1983 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1984 {
1985 struct i2c_adapter *adap = &i2c_dev->adap;
1986 void __iomem *base = i2c_dev->base;
1987 struct i2c_client *client;
1988
1989 client = i2c_new_slave_host_notify_device(adap);
1990 if (IS_ERR(client))
1991 return PTR_ERR(client);
1992
1993 i2c_dev->host_notify_client = client;
1994
1995 /* Enable SMBus Host address */
1996 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
1997
1998 return 0;
1999 }
2000
stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)2001 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2002 {
2003 void __iomem *base = i2c_dev->base;
2004
2005 if (i2c_dev->host_notify_client) {
2006 /* Disable SMBus Host address */
2007 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2008 STM32F7_I2C_CR1_SMBHEN);
2009 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2010 }
2011 }
2012
stm32f7_i2c_func(struct i2c_adapter *adap)2013 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2014 {
2015 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2016
2017 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2018 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2019 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2020 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2021 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2022 I2C_FUNC_SMBUS_I2C_BLOCK;
2023
2024 if (i2c_dev->smbus_mode)
2025 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2026
2027 return func;
2028 }
2029
2030 static const struct i2c_algorithm stm32f7_i2c_algo = {
2031 .master_xfer = stm32f7_i2c_xfer,
2032 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2033 .functionality = stm32f7_i2c_func,
2034 .reg_slave = stm32f7_i2c_reg_slave,
2035 .unreg_slave = stm32f7_i2c_unreg_slave,
2036 };
2037
stm32f7_i2c_probe(struct platform_device *pdev)2038 static int stm32f7_i2c_probe(struct platform_device *pdev)
2039 {
2040 struct stm32f7_i2c_dev *i2c_dev;
2041 const struct stm32f7_i2c_setup *setup;
2042 struct resource *res;
2043 struct i2c_adapter *adap;
2044 struct reset_control *rst;
2045 dma_addr_t phy_addr;
2046 int irq_error, irq_event, ret;
2047
2048 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2049 if (!i2c_dev)
2050 return -ENOMEM;
2051
2052 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2053 if (IS_ERR(i2c_dev->base))
2054 return PTR_ERR(i2c_dev->base);
2055 phy_addr = (dma_addr_t)res->start;
2056
2057 irq_event = platform_get_irq(pdev, 0);
2058 if (irq_event <= 0) {
2059 if (irq_event != -EPROBE_DEFER)
2060 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
2061 irq_event);
2062 return irq_event ? : -ENOENT;
2063 }
2064
2065 irq_error = platform_get_irq(pdev, 1);
2066 if (irq_error <= 0) {
2067 if (irq_error != -EPROBE_DEFER)
2068 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
2069 irq_error);
2070 return irq_error ? : -ENOENT;
2071 }
2072
2073 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2074 "wakeup-source");
2075
2076 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2077 if (IS_ERR(i2c_dev->clk))
2078 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2079 "Failed to get controller clock\n");
2080
2081 ret = clk_prepare_enable(i2c_dev->clk);
2082 if (ret) {
2083 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2084 return ret;
2085 }
2086
2087 rst = devm_reset_control_get(&pdev->dev, NULL);
2088 if (IS_ERR(rst)) {
2089 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2090 "Error: Missing reset ctrl\n");
2091 goto clk_free;
2092 }
2093 reset_control_assert(rst);
2094 udelay(2);
2095 reset_control_deassert(rst);
2096
2097 i2c_dev->dev = &pdev->dev;
2098
2099 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2100 stm32f7_i2c_isr_event,
2101 stm32f7_i2c_isr_event_thread,
2102 IRQF_ONESHOT,
2103 pdev->name, i2c_dev);
2104 if (ret) {
2105 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2106 irq_event);
2107 goto clk_free;
2108 }
2109
2110 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2111 pdev->name, i2c_dev);
2112 if (ret) {
2113 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2114 irq_error);
2115 goto clk_free;
2116 }
2117
2118 setup = of_device_get_match_data(&pdev->dev);
2119 if (!setup) {
2120 dev_err(&pdev->dev, "Can't get device data\n");
2121 ret = -ENODEV;
2122 goto clk_free;
2123 }
2124 i2c_dev->setup = *setup;
2125
2126 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2127 if (ret)
2128 goto clk_free;
2129
2130 /* Setup Fast mode plus if necessary */
2131 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2132 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2133 if (ret)
2134 goto clk_free;
2135 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2136 if (ret)
2137 goto clk_free;
2138 }
2139
2140 adap = &i2c_dev->adap;
2141 i2c_set_adapdata(adap, i2c_dev);
2142 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2143 &res->start);
2144 adap->owner = THIS_MODULE;
2145 adap->timeout = 2 * HZ;
2146 adap->retries = 3;
2147 adap->algo = &stm32f7_i2c_algo;
2148 adap->dev.parent = &pdev->dev;
2149 adap->dev.of_node = pdev->dev.of_node;
2150
2151 init_completion(&i2c_dev->complete);
2152
2153 /* Init DMA config if supported */
2154 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2155 STM32F7_I2C_TXDR,
2156 STM32F7_I2C_RXDR);
2157 if (IS_ERR(i2c_dev->dma)) {
2158 ret = PTR_ERR(i2c_dev->dma);
2159 /* DMA support is optional, only report other errors */
2160 if (ret != -ENODEV)
2161 goto fmp_clear;
2162 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2163 i2c_dev->dma = NULL;
2164 }
2165
2166 if (i2c_dev->wakeup_src) {
2167 device_set_wakeup_capable(i2c_dev->dev, true);
2168
2169 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2170 if (ret) {
2171 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2172 goto clr_wakeup_capable;
2173 }
2174 }
2175
2176 platform_set_drvdata(pdev, i2c_dev);
2177
2178 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2179 STM32F7_AUTOSUSPEND_DELAY);
2180 pm_runtime_use_autosuspend(i2c_dev->dev);
2181 pm_runtime_set_active(i2c_dev->dev);
2182 pm_runtime_enable(i2c_dev->dev);
2183
2184 pm_runtime_get_noresume(&pdev->dev);
2185
2186 stm32f7_i2c_hw_config(i2c_dev);
2187
2188 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2189
2190 ret = i2c_add_adapter(adap);
2191 if (ret)
2192 goto pm_disable;
2193
2194 if (i2c_dev->smbus_mode) {
2195 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2196 if (ret) {
2197 dev_err(i2c_dev->dev,
2198 "failed to enable SMBus Host-Notify protocol (%d)\n",
2199 ret);
2200 goto i2c_adapter_remove;
2201 }
2202 }
2203
2204 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2205
2206 pm_runtime_mark_last_busy(i2c_dev->dev);
2207 pm_runtime_put_autosuspend(i2c_dev->dev);
2208
2209 return 0;
2210
2211 i2c_adapter_remove:
2212 i2c_del_adapter(adap);
2213
2214 pm_disable:
2215 pm_runtime_put_noidle(i2c_dev->dev);
2216 pm_runtime_disable(i2c_dev->dev);
2217 pm_runtime_set_suspended(i2c_dev->dev);
2218 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2219
2220 if (i2c_dev->wakeup_src)
2221 dev_pm_clear_wake_irq(i2c_dev->dev);
2222
2223 clr_wakeup_capable:
2224 if (i2c_dev->wakeup_src)
2225 device_set_wakeup_capable(i2c_dev->dev, false);
2226
2227 if (i2c_dev->dma) {
2228 stm32_i2c_dma_free(i2c_dev->dma);
2229 i2c_dev->dma = NULL;
2230 }
2231
2232 fmp_clear:
2233 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2234
2235 clk_free:
2236 clk_disable_unprepare(i2c_dev->clk);
2237
2238 return ret;
2239 }
2240
stm32f7_i2c_remove(struct platform_device *pdev)2241 static int stm32f7_i2c_remove(struct platform_device *pdev)
2242 {
2243 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2244
2245 stm32f7_i2c_disable_smbus_host(i2c_dev);
2246
2247 i2c_del_adapter(&i2c_dev->adap);
2248 pm_runtime_get_sync(i2c_dev->dev);
2249
2250 if (i2c_dev->wakeup_src) {
2251 dev_pm_clear_wake_irq(i2c_dev->dev);
2252 /*
2253 * enforce that wakeup is disabled and that the device
2254 * is marked as non wakeup capable
2255 */
2256 device_init_wakeup(i2c_dev->dev, false);
2257 }
2258
2259 pm_runtime_put_noidle(i2c_dev->dev);
2260 pm_runtime_disable(i2c_dev->dev);
2261 pm_runtime_set_suspended(i2c_dev->dev);
2262 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2263
2264 if (i2c_dev->dma) {
2265 stm32_i2c_dma_free(i2c_dev->dma);
2266 i2c_dev->dma = NULL;
2267 }
2268
2269 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2270
2271 clk_disable_unprepare(i2c_dev->clk);
2272
2273 return 0;
2274 }
2275
stm32f7_i2c_runtime_suspend(struct device *dev)2276 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2277 {
2278 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2279
2280 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2281 clk_disable_unprepare(i2c_dev->clk);
2282
2283 return 0;
2284 }
2285
stm32f7_i2c_runtime_resume(struct device *dev)2286 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2287 {
2288 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2289 int ret;
2290
2291 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2292 ret = clk_prepare_enable(i2c_dev->clk);
2293 if (ret) {
2294 dev_err(dev, "failed to prepare_enable clock\n");
2295 return ret;
2296 }
2297 }
2298
2299 return 0;
2300 }
2301
2302 #ifdef CONFIG_PM_SLEEP
stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)2303 static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2304 {
2305 int ret;
2306 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2307
2308 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2309 if (ret < 0)
2310 return ret;
2311
2312 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2313 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2314 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2315 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2316 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2317 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2318
2319 pm_runtime_put_sync(i2c_dev->dev);
2320
2321 return ret;
2322 }
2323
stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)2324 static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2325 {
2326 u32 cr1;
2327 int ret;
2328 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2329
2330 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2331 if (ret < 0)
2332 return ret;
2333
2334 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2335 if (cr1 & STM32F7_I2C_CR1_PE)
2336 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2337 STM32F7_I2C_CR1_PE);
2338
2339 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2340 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2341 i2c_dev->base + STM32F7_I2C_CR1);
2342 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2343 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2344 STM32F7_I2C_CR1_PE);
2345 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2346 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2347 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2348 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2349
2350 pm_runtime_put_sync(i2c_dev->dev);
2351
2352 return ret;
2353 }
2354
stm32f7_i2c_suspend(struct device *dev)2355 static int stm32f7_i2c_suspend(struct device *dev)
2356 {
2357 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2358 int ret;
2359
2360 i2c_mark_adapter_suspended(&i2c_dev->adap);
2361
2362 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2363 ret = stm32f7_i2c_regs_backup(i2c_dev);
2364 if (ret < 0) {
2365 i2c_mark_adapter_resumed(&i2c_dev->adap);
2366 return ret;
2367 }
2368
2369 pinctrl_pm_select_sleep_state(dev);
2370 pm_runtime_force_suspend(dev);
2371 }
2372
2373 return 0;
2374 }
2375
stm32f7_i2c_resume(struct device *dev)2376 static int stm32f7_i2c_resume(struct device *dev)
2377 {
2378 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2379 int ret;
2380
2381 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2382 ret = pm_runtime_force_resume(dev);
2383 if (ret < 0)
2384 return ret;
2385 pinctrl_pm_select_default_state(dev);
2386
2387 ret = stm32f7_i2c_regs_restore(i2c_dev);
2388 if (ret < 0)
2389 return ret;
2390 }
2391
2392 i2c_mark_adapter_resumed(&i2c_dev->adap);
2393
2394 return 0;
2395 }
2396 #endif
2397
2398 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2399 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2400 stm32f7_i2c_runtime_resume, NULL)
2401 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2402 };
2403
2404 static const struct of_device_id stm32f7_i2c_match[] = {
2405 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2406 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2407 {},
2408 };
2409 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2410
2411 static struct platform_driver stm32f7_i2c_driver = {
2412 .driver = {
2413 .name = "stm32f7-i2c",
2414 .of_match_table = stm32f7_i2c_match,
2415 .pm = &stm32f7_i2c_pm_ops,
2416 },
2417 .probe = stm32f7_i2c_probe,
2418 .remove = stm32f7_i2c_remove,
2419 };
2420
2421 module_platform_driver(stm32f7_i2c_driver);
2422
2423 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2424 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2425 MODULE_LICENSE("GPL v2");
2426