1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8#include <linux/acpi.h> 9#include <linux/bitfield.h> 10#include <linux/delay.h> 11#include <linux/err.h> 12#include <linux/interrupt.h> 13#include <linux/i2c.h> 14#include <linux/io.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/mutex.h> 18#include <linux/of_device.h> 19#include <linux/platform_device.h> 20#include <linux/string.h> 21 22/* Defines what functionality is present. */ 23#define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 24 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 25 26#define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 27 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 28 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 29 I2C_FUNC_SMBUS_PROC_CALL) 30 31#define MLXBF_I2C_FUNC_ALL \ 32 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 33 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 34 35#define MLXBF_I2C_SMBUS_MAX 3 36 37/* Shared resources info in BlueField platforms. */ 38 39#define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 40#define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 41 42#define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 43#define MLXBF_I2C_GPIO_TYU_SIZE 0x100 44 45#define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 46#define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 47 48#define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 49#define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 50 51#define MLXBF_I2C_SHARED_RES_MAX 3 52 53/* 54 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 55 * refer to their respective offsets relative to the corresponding 56 * memory-mapped region whose addresses are specified in either the DT or 57 * the ACPI tables or above. 58 */ 59 60/* 61 * SMBus Master core clock frequency. Timing configurations are 62 * strongly dependent on the core clock frequency of the SMBus 63 * Master. Default value is set to 400MHz. 64 */ 65#define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 66/* Reference clock for Bluefield - 156 MHz. */ 67#define MLXBF_I2C_PLL_IN_FREQ 156250000ULL 68 69/* Constant used to determine the PLL frequency. */ 70#define MLNXBF_I2C_COREPLL_CONST 16384ULL 71 72#define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL 73 74/* PLL registers. */ 75#define MLXBF_I2C_CORE_PLL_REG1 0x4 76#define MLXBF_I2C_CORE_PLL_REG2 0x8 77 78/* OR cause register. */ 79#define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 80#define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 81 82/* Arbiter Cause Register. */ 83#define MLXBF_I2C_CAUSE_ARBITER 0x1c 84 85/* 86 * Cause Status flags. Note that those bits might be considered 87 * as interrupt enabled bits. 88 */ 89 90/* Transaction ended with STOP. */ 91#define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 92/* Master arbitration lost. */ 93#define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 94/* Unexpected start detected. */ 95#define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 96/* Unexpected stop detected. */ 97#define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 98/* Wait for transfer continuation. */ 99#define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 100/* Failed to generate STOP. */ 101#define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 102/* Failed to generate START. */ 103#define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 104/* Clock toggle completed. */ 105#define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 106/* Transfer timeout occurred. */ 107#define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 108/* Master busy bit reset. */ 109#define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 110 111#define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 112 113#define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 114 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 115 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 116 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 117 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 118 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 119 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 120 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 121 122/* 123 * Slave cause status flags. Note that those bits might be considered 124 * as interrupt enabled bits. 125 */ 126 127/* Write transaction received successfully. */ 128#define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 129/* Read transaction received, waiting for response. */ 130#define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 131/* Slave busy bit reset. */ 132#define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 133 134#define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0) 135 136/* Cause coalesce registers. */ 137#define MLXBF_I2C_CAUSE_COALESCE_0 0x00 138#define MLXBF_I2C_CAUSE_COALESCE_1 0x04 139#define MLXBF_I2C_CAUSE_COALESCE_2 0x08 140 141#define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX 142#define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 143 144/* Functional enable register. */ 145#define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 146/* Force OE enable register. */ 147#define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 148/* 149 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 150 * SDA/SCL lines: 151 * 152 * SMBUS GW0 -> bits[26:25] 153 * SMBUS GW1 -> bits[28:27] 154 * SMBUS GW2 -> bits[30:29] 155 */ 156#define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 157 158/* Note that gw_id can be 0,1 or 2. */ 159#define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 160 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 161 162#define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 163 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 164 165#define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 166 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 167 168/* SMBus timing parameters. */ 169#define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 170#define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 171#define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 172#define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 173#define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 174#define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 175#define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 176 177enum { 178 MLXBF_I2C_TIMING_100KHZ = 100000, 179 MLXBF_I2C_TIMING_400KHZ = 400000, 180 MLXBF_I2C_TIMING_1000KHZ = 1000000, 181}; 182 183/* 184 * Defines SMBus operating frequency and core clock frequency. 185 * According to ADB files, default values are compliant to 100KHz SMBus 186 * @ 400MHz core clock. The driver should be able to calculate core 187 * frequency based on PLL parameters. 188 */ 189#define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 190 191/* Core PLL TYU configuration. */ 192#define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3) 193#define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16) 194#define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20) 195 196/* Core PLL YU configuration. */ 197#define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 198#define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 199#define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26) 200 201 202/* Core PLL frequency. */ 203static u64 mlxbf_i2c_corepll_frequency; 204 205/* SMBus Master GW. */ 206#define MLXBF_I2C_SMBUS_MASTER_GW 0x200 207/* Number of bytes received and sent. */ 208#define MLXBF_I2C_SMBUS_RS_BYTES 0x300 209/* Packet error check (PEC) value. */ 210#define MLXBF_I2C_SMBUS_MASTER_PEC 0x304 211/* Status bits (ACK/NACK/FW Timeout). */ 212#define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308 213/* SMbus Master Finite State Machine. */ 214#define MLXBF_I2C_SMBUS_MASTER_FSM 0x310 215 216/* 217 * When enabled, the master will issue a stop condition in case of 218 * timeout while waiting for FW response. 219 */ 220#define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c 221 222/* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 223#define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 224#define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 225#define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 226#define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 227#define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 228#define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 229 230#define MLXBF_I2C_MASTER_ENABLE \ 231 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 232 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) 233 234#define MLXBF_I2C_MASTER_ENABLE_WRITE \ 235 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 236 237#define MLXBF_I2C_MASTER_ENABLE_READ \ 238 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 239 240#define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */ 241#define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */ 242#define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */ 243#define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */ 244#define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */ 245 246/* SMBus master GW Data descriptor. */ 247#define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280 248#define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 249 250/* Maximum bytes to read/write per SMBus transaction. */ 251#define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 252#define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 253 254/* All bytes were transmitted. */ 255#define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 256/* NACK received. */ 257#define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 258/* Slave's byte count >128 bytes. */ 259#define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 260/* Timeout occurred. */ 261#define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 262 263#define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 264 265#define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 266 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 267 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 268 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 269 270#define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 271#define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 272 273/* SMBus slave GW. */ 274#define MLXBF_I2C_SMBUS_SLAVE_GW 0x400 275/* Number of bytes received and sent from/to master. */ 276#define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500 277/* Packet error check (PEC) value. */ 278#define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504 279/* SMBus slave Finite State Machine (FSM). */ 280#define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510 281/* 282 * Should be set when all raised causes handled, and cleared by HW on 283 * every new cause. 284 */ 285#define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c 286 287/* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 288#define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 289#define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 290 291#define MLXBF_I2C_SLAVE_ENABLE \ 292 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 293 294#define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 295#define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 296 297/* SMBus slave GW Data descriptor. */ 298#define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480 299#define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 300 301/* SMbus slave configuration registers. */ 302#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514 303#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 304#define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7 305#define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 306 307#define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \ 308 ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) 309 310/* 311 * Timeout is given in microsends. Note also that timeout handling is not 312 * exact. 313 */ 314#define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 315#define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */ 316 317/* Encapsulates timing parameters. */ 318struct mlxbf_i2c_timings { 319 u16 scl_high; /* Clock high period. */ 320 u16 scl_low; /* Clock low period. */ 321 u8 sda_rise; /* Data rise time. */ 322 u8 sda_fall; /* Data fall time. */ 323 u8 scl_rise; /* Clock rise time. */ 324 u8 scl_fall; /* Clock fall time. */ 325 u16 hold_start; /* Hold time after (REPEATED) START. */ 326 u16 hold_data; /* Data hold time. */ 327 u16 setup_start; /* REPEATED START condition setup time. */ 328 u16 setup_stop; /* STOP condition setup time. */ 329 u16 setup_data; /* Data setup time. */ 330 u16 pad; /* Padding. */ 331 u16 buf; /* Bus free time between STOP and START. */ 332 u16 thigh_max; /* Thigh max. */ 333 u32 timeout; /* Detect clock low timeout. */ 334}; 335 336enum { 337 MLXBF_I2C_F_READ = BIT(0), 338 MLXBF_I2C_F_WRITE = BIT(1), 339 MLXBF_I2C_F_NORESTART = BIT(3), 340 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 341 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 342 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 343 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 344}; 345 346struct mlxbf_i2c_smbus_operation { 347 u32 flags; 348 u32 length; /* Buffer length in bytes. */ 349 u8 *buffer; 350}; 351 352#define MLXBF_I2C_SMBUS_OP_CNT_1 1 353#define MLXBF_I2C_SMBUS_OP_CNT_2 2 354#define MLXBF_I2C_SMBUS_OP_CNT_3 3 355#define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 356 357struct mlxbf_i2c_smbus_request { 358 u8 slave; 359 u8 operation_cnt; 360 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 361}; 362 363struct mlxbf_i2c_resource { 364 void __iomem *io; 365 struct resource *params; 366 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 367 u8 type; 368}; 369 370/* List of chip resources that are being accessed by the driver. */ 371enum { 372 MLXBF_I2C_SMBUS_RES, 373 MLXBF_I2C_MST_CAUSE_RES, 374 MLXBF_I2C_SLV_CAUSE_RES, 375 MLXBF_I2C_COALESCE_RES, 376 MLXBF_I2C_COREPLL_RES, 377 MLXBF_I2C_GPIO_RES, 378 MLXBF_I2C_END_RES, 379}; 380 381/* Helper macro to define an I2C resource parameters. */ 382#define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 383 { \ 384 .start = (addr), \ 385 .end = (addr) + (size) - 1, \ 386 .name = (str) \ 387 } 388 389static struct resource mlxbf_i2c_coalesce_tyu_params = 390 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 391 MLXBF_I2C_COALESCE_TYU_SIZE, 392 "COALESCE_MEM"); 393static struct resource mlxbf_i2c_corepll_tyu_params = 394 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 395 MLXBF_I2C_COREPLL_TYU_SIZE, 396 "COREPLL_MEM"); 397static struct resource mlxbf_i2c_corepll_yu_params = 398 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 399 MLXBF_I2C_COREPLL_YU_SIZE, 400 "COREPLL_MEM"); 401static struct resource mlxbf_i2c_gpio_tyu_params = 402 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 403 MLXBF_I2C_GPIO_TYU_SIZE, 404 "GPIO_MEM"); 405 406static struct mutex mlxbf_i2c_coalesce_lock; 407static struct mutex mlxbf_i2c_corepll_lock; 408static struct mutex mlxbf_i2c_gpio_lock; 409 410/* Mellanox BlueField chip type. */ 411enum mlxbf_i2c_chip_type { 412 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 413 MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */ 414}; 415 416struct mlxbf_i2c_chip_info { 417 enum mlxbf_i2c_chip_type type; 418 /* Chip shared resources that are being used by the I2C controller. */ 419 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 420 421 /* Callback to calculate the core PLL frequency. */ 422 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 423}; 424 425struct mlxbf_i2c_priv { 426 const struct mlxbf_i2c_chip_info *chip; 427 struct i2c_adapter adap; 428 struct mlxbf_i2c_resource *smbus; 429 struct mlxbf_i2c_resource *mst_cause; 430 struct mlxbf_i2c_resource *slv_cause; 431 struct mlxbf_i2c_resource *coalesce; 432 u64 frequency; /* Core frequency in Hz. */ 433 int bus; /* Physical bus identifier. */ 434 int irq; 435 struct i2c_client *slave; 436}; 437 438static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 439 [MLXBF_I2C_CHIP_TYPE_1] = { 440 .params = &mlxbf_i2c_coalesce_tyu_params, 441 .lock = &mlxbf_i2c_coalesce_lock, 442 .type = MLXBF_I2C_COALESCE_RES 443 }, 444 {} 445}; 446 447static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 448 [MLXBF_I2C_CHIP_TYPE_1] = { 449 .params = &mlxbf_i2c_corepll_tyu_params, 450 .lock = &mlxbf_i2c_corepll_lock, 451 .type = MLXBF_I2C_COREPLL_RES 452 }, 453 [MLXBF_I2C_CHIP_TYPE_2] = { 454 .params = &mlxbf_i2c_corepll_yu_params, 455 .lock = &mlxbf_i2c_corepll_lock, 456 .type = MLXBF_I2C_COREPLL_RES, 457 } 458}; 459 460static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 461 [MLXBF_I2C_CHIP_TYPE_1] = { 462 .params = &mlxbf_i2c_gpio_tyu_params, 463 .lock = &mlxbf_i2c_gpio_lock, 464 .type = MLXBF_I2C_GPIO_RES 465 }, 466 {} 467}; 468 469static u8 mlxbf_i2c_bus_count; 470 471static struct mutex mlxbf_i2c_bus_lock; 472 473/* Polling frequency in microseconds. */ 474#define MLXBF_I2C_POLL_FREQ_IN_USEC 200 475 476#define MLXBF_I2C_SHIFT_0 0 477#define MLXBF_I2C_SHIFT_8 8 478#define MLXBF_I2C_SHIFT_16 16 479#define MLXBF_I2C_SHIFT_24 24 480 481#define MLXBF_I2C_MASK_8 GENMASK(7, 0) 482#define MLXBF_I2C_MASK_16 GENMASK(15, 0) 483 484/* 485 * Function to poll a set of bits at a specific address; it checks whether 486 * the bits are equal to zero when eq_zero is set to 'true', and not equal 487 * to zero when eq_zero is set to 'false'. 488 * Note that the timeout is given in microseconds. 489 */ 490static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask, 491 bool eq_zero, u32 timeout) 492{ 493 u32 bits; 494 495 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1; 496 497 do { 498 bits = readl(io + addr) & mask; 499 if (eq_zero ? bits == 0 : bits != 0) 500 return eq_zero ? 1 : bits; 501 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC); 502 } while (timeout-- != 0); 503 504 return 0; 505} 506 507/* 508 * SW must make sure that the SMBus Master GW is idle before starting 509 * a transaction. Accordingly, this function polls the Master FSM stop 510 * bit; it returns false when the bit is asserted, true if not. 511 */ 512static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv) 513{ 514 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK; 515 u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM; 516 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT; 517 518 if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout)) 519 return true; 520 521 return false; 522} 523 524/* 525 * wait for the lock to be released before acquiring it. 526 */ 527static bool mlxbf_i2c_smbus_master_lock(struct mlxbf_i2c_priv *priv) 528{ 529 if (mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, 530 MLXBF_I2C_MASTER_LOCK_BIT, true, 531 MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT)) 532 return true; 533 534 return false; 535} 536 537static void mlxbf_i2c_smbus_master_unlock(struct mlxbf_i2c_priv *priv) 538{ 539 /* Clear the gw to clear the lock */ 540 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW); 541} 542 543static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 544 u32 cause_status) 545{ 546 /* 547 * When transaction ended with STOP, all bytes were transmitted, 548 * and no NACK received, then the transaction ended successfully. 549 * On the other hand, when the GW is configured with the stop bit 550 * de-asserted then the SMBus expects the following GW configuration 551 * for transfer continuation. 552 */ 553 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 554 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 555 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 556 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 557 return true; 558 559 return false; 560} 561 562/* 563 * Poll SMBus master status and return transaction status, 564 * i.e. whether succeeded or failed. I2C and SMBus fault codes 565 * are returned as negative numbers from most calls, with zero 566 * or some positive number indicating a non-fault return. 567 */ 568static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 569{ 570 u32 master_status_bits; 571 u32 cause_status_bits; 572 573 /* 574 * GW busy bit is raised by the driver and cleared by the HW 575 * when the transaction is completed. The busy bit is a good 576 * indicator of transaction status. So poll the busy bit, and 577 * then read the cause and master status bits to determine if 578 * errors occurred during the transaction. 579 */ 580 mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, 581 MLXBF_I2C_MASTER_BUSY_BIT, true, 582 MLXBF_I2C_SMBUS_TIMEOUT); 583 584 /* Read cause status bits. */ 585 cause_status_bits = readl(priv->mst_cause->io + 586 MLXBF_I2C_CAUSE_ARBITER); 587 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 588 589 /* 590 * Parse both Cause and Master GW bits, then return transaction status. 591 */ 592 593 master_status_bits = readl(priv->smbus->io + 594 MLXBF_I2C_SMBUS_MASTER_STATUS); 595 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 596 597 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 598 cause_status_bits)) 599 return 0; 600 601 /* 602 * In case of timeout on GW busy, the ISR will clear busy bit but 603 * transaction ended bits cause will not be set so the transaction 604 * fails. Then, we must check Master GW status bits. 605 */ 606 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 607 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 608 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 609 return -EIO; 610 611 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 612 return -EAGAIN; 613 614 return -ETIMEDOUT; 615} 616 617static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 618 const u8 *data, u8 length, u32 addr) 619{ 620 u8 offset, aligned_length; 621 u32 data32; 622 623 aligned_length = round_up(length, 4); 624 625 /* 626 * Copy data bytes from 4-byte aligned source buffer. 627 * Data copied to the Master GW Data Descriptor MUST be shifted 628 * left so the data starts at the MSB of the descriptor registers 629 * as required by the underlying hardware. Enable byte swapping 630 * when writing data bytes to the 32 * 32-bit HW Data registers 631 * a.k.a Master GW Data Descriptor. 632 */ 633 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 634 data32 = *((u32 *)(data + offset)); 635 iowrite32be(data32, priv->smbus->io + addr + offset); 636 } 637} 638 639static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 640 u8 *data, u8 length, u32 addr) 641{ 642 u32 data32, mask; 643 u8 byte, offset; 644 645 mask = sizeof(u32) - 1; 646 647 /* 648 * Data bytes in the Master GW Data Descriptor are shifted left 649 * so the data starts at the MSB of the descriptor registers as 650 * set by the underlying hardware. Enable byte swapping while 651 * reading data bytes from the 32 * 32-bit HW Data registers 652 * a.k.a Master GW Data Descriptor. 653 */ 654 655 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 656 data32 = ioread32be(priv->smbus->io + addr + offset); 657 *((u32 *)(data + offset)) = data32; 658 } 659 660 if (!(length & mask)) 661 return; 662 663 data32 = ioread32be(priv->smbus->io + addr + offset); 664 665 for (byte = 0; byte < (length & mask); byte++) { 666 data[offset + byte] = data32 & GENMASK(7, 0); 667 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 668 } 669} 670 671static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 672 u8 len, u8 block_en, u8 pec_en, bool read) 673{ 674 u32 command; 675 676 /* Set Master GW control word. */ 677 if (read) { 678 command = MLXBF_I2C_MASTER_ENABLE_READ; 679 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 680 } else { 681 command = MLXBF_I2C_MASTER_ENABLE_WRITE; 682 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 683 } 684 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 685 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 686 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 687 688 /* Clear status bits. */ 689 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 690 /* Set the cause data. */ 691 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 692 /* Zero PEC byte. */ 693 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC); 694 /* Zero byte count. */ 695 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES); 696 697 /* GW activation. */ 698 writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW); 699 700 /* 701 * Poll master status and check status bits. An ACK is sent when 702 * completing writing data to the bus (Master 'byte_count_done' bit 703 * is set to 1). 704 */ 705 return mlxbf_i2c_smbus_check_status(priv); 706} 707 708static int 709mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 710 struct mlxbf_i2c_smbus_request *request) 711{ 712 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 713 u8 op_idx, data_idx, data_len, write_len, read_len; 714 struct mlxbf_i2c_smbus_operation *operation; 715 u8 read_en, write_en, block_en, pec_en; 716 u8 slave, flags, addr; 717 u8 *read_buf; 718 int ret = 0; 719 720 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 721 return -EINVAL; 722 723 read_buf = NULL; 724 data_idx = 0; 725 read_en = 0; 726 write_en = 0; 727 write_len = 0; 728 read_len = 0; 729 block_en = 0; 730 pec_en = 0; 731 slave = request->slave & GENMASK(6, 0); 732 addr = slave << 1; 733 734 /* 735 * Try to acquire the smbus gw lock before any reads of the GW register since 736 * a read sets the lock. 737 */ 738 if (WARN_ON(!mlxbf_i2c_smbus_master_lock(priv))) 739 return -EBUSY; 740 741 /* Check whether the HW is idle */ 742 if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) { 743 ret = -EBUSY; 744 goto out_unlock; 745 } 746 747 /* Set first byte. */ 748 data_desc[data_idx++] = addr; 749 750 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 751 operation = &request->operation[op_idx]; 752 flags = operation->flags; 753 754 /* 755 * Note that read and write operations might be handled by a 756 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 757 * then write command byte and set the optional SMBus specific 758 * bits such as block_en and pec_en. These bits MUST be 759 * submitted by the first operation only. 760 */ 761 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 762 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 763 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 764 } 765 766 if (flags & MLXBF_I2C_F_WRITE) { 767 write_en = 1; 768 write_len += operation->length; 769 if (data_idx + operation->length > 770 MLXBF_I2C_MASTER_DATA_DESC_SIZE) { 771 ret = -ENOBUFS; 772 goto out_unlock; 773 } 774 memcpy(data_desc + data_idx, 775 operation->buffer, operation->length); 776 data_idx += operation->length; 777 } 778 /* 779 * We assume that read operations are performed only once per 780 * SMBus transaction. *TBD* protect this statement so it won't 781 * be executed twice? or return an error if we try to read more 782 * than once? 783 */ 784 if (flags & MLXBF_I2C_F_READ) { 785 read_en = 1; 786 /* Subtract 1 as required by HW. */ 787 read_len = operation->length - 1; 788 read_buf = operation->buffer; 789 } 790 } 791 792 /* Set Master GW data descriptor. */ 793 data_len = write_len + 1; /* Add one byte of the slave address. */ 794 /* 795 * Note that data_len cannot be 0. Indeed, the slave address byte 796 * must be written to the data registers. 797 */ 798 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 799 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 800 801 if (write_en) { 802 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 803 pec_en, 0); 804 if (ret) 805 goto out_unlock; 806 } 807 808 if (read_en) { 809 /* Write slave address to Master GW data descriptor. */ 810 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 811 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 812 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 813 pec_en, 1); 814 if (!ret) { 815 /* Get Master GW data descriptor. */ 816 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 817 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 818 819 /* Get data from Master GW data descriptor. */ 820 memcpy(read_buf, data_desc, read_len + 1); 821 } 822 823 /* 824 * After a read operation the SMBus FSM ps (present state) 825 * needs to be 'manually' reset. This should be removed in 826 * next tag integration. 827 */ 828 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 829 priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM); 830 } 831 832out_unlock: 833 mlxbf_i2c_smbus_master_unlock(priv); 834 835 return ret; 836} 837 838/* I2C SMBus protocols. */ 839 840static void 841mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 842 u8 read) 843{ 844 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 845 846 request->operation[0].length = 0; 847 request->operation[0].flags = MLXBF_I2C_F_WRITE; 848 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 849} 850 851static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 852 u8 *data, bool read, bool pec_check) 853{ 854 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 855 856 request->operation[0].length = 1; 857 request->operation[0].length += pec_check; 858 859 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 860 request->operation[0].flags |= read ? 861 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 862 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 863 864 request->operation[0].buffer = data; 865} 866 867static void 868mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 869 u8 *command, u8 *data, bool read, bool pec_check) 870{ 871 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 872 873 request->operation[0].length = 1; 874 request->operation[0].flags = 875 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 876 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 877 request->operation[0].buffer = command; 878 879 request->operation[1].length = 1; 880 request->operation[1].length += pec_check; 881 request->operation[1].flags = read ? 882 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 883 request->operation[1].buffer = data; 884} 885 886static void 887mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 888 u8 *command, u8 *data, bool read, bool pec_check) 889{ 890 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 891 892 request->operation[0].length = 1; 893 request->operation[0].flags = 894 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 895 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 896 request->operation[0].buffer = command; 897 898 request->operation[1].length = 2; 899 request->operation[1].length += pec_check; 900 request->operation[1].flags = read ? 901 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 902 request->operation[1].buffer = data; 903} 904 905static void 906mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 907 u8 *command, u8 *data, u8 *data_len, bool read, 908 bool pec_check) 909{ 910 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 911 912 request->operation[0].length = 1; 913 request->operation[0].flags = 914 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 915 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 916 request->operation[0].buffer = command; 917 918 /* 919 * As specified in the standard, the max number of bytes to read/write 920 * per block operation is 32 bytes. In Golan code, the controller can 921 * read up to 128 bytes and write up to 127 bytes. 922 */ 923 request->operation[1].length = 924 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 925 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 926 request->operation[1].flags = read ? 927 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 928 /* 929 * Skip the first data byte, which corresponds to the number of bytes 930 * to read/write. 931 */ 932 request->operation[1].buffer = data + 1; 933 934 *data_len = request->operation[1].length; 935 936 /* Set the number of byte to read. This will be used by userspace. */ 937 if (read) 938 data[0] = *data_len; 939} 940 941static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 942 u8 *command, u8 *data, u8 *data_len, 943 bool read, bool pec_check) 944{ 945 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 946 947 request->operation[0].length = 1; 948 request->operation[0].flags = 949 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 950 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 951 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 952 request->operation[0].buffer = command; 953 954 request->operation[1].length = 955 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 956 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 957 request->operation[1].flags = read ? 958 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 959 request->operation[1].buffer = data + 1; 960 961 *data_len = request->operation[1].length; 962 963 /* Set the number of bytes to read. This will be used by userspace. */ 964 if (read) 965 data[0] = *data_len; 966} 967 968static void 969mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 970 u8 *command, u8 *data, bool pec_check) 971{ 972 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 973 974 request->operation[0].length = 1; 975 request->operation[0].flags = 976 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 977 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 978 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 979 request->operation[0].buffer = command; 980 981 request->operation[1].length = 2; 982 request->operation[1].flags = MLXBF_I2C_F_WRITE; 983 request->operation[1].buffer = data; 984 985 request->operation[2].length = 3; 986 request->operation[2].flags = MLXBF_I2C_F_READ; 987 request->operation[2].buffer = data; 988} 989 990static void 991mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 992 u8 *command, u8 *data, u8 *data_len, 993 bool pec_check) 994{ 995 u32 length; 996 997 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 998 999 request->operation[0].length = 1; 1000 request->operation[0].flags = 1001 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 1002 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 1003 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 1004 request->operation[0].buffer = command; 1005 1006 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 1007 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 1008 1009 request->operation[1].length = length - pec_check; 1010 request->operation[1].flags = MLXBF_I2C_F_WRITE; 1011 request->operation[1].buffer = data; 1012 1013 request->operation[2].length = length; 1014 request->operation[2].flags = MLXBF_I2C_F_READ; 1015 request->operation[2].buffer = data; 1016 1017 *data_len = length; /* including PEC byte. */ 1018} 1019 1020/* Initialization functions. */ 1021 1022static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 1023{ 1024 return priv->chip->type == type; 1025} 1026 1027static struct mlxbf_i2c_resource * 1028mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 1029{ 1030 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1031 struct mlxbf_i2c_resource *res; 1032 u8 res_idx = 0; 1033 1034 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 1035 res = chip->shared_res[res_idx]; 1036 if (res && res->type == type) 1037 return res; 1038 } 1039 1040 return NULL; 1041} 1042 1043static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1044 struct mlxbf_i2c_resource **res, 1045 u8 type) 1046{ 1047 struct mlxbf_i2c_resource *tmp_res; 1048 struct device *dev = &pdev->dev; 1049 1050 if (!res || *res || type >= MLXBF_I2C_END_RES) 1051 return -EINVAL; 1052 1053 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1054 GFP_KERNEL); 1055 if (!tmp_res) 1056 return -ENOMEM; 1057 1058 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type); 1059 if (!tmp_res->params) { 1060 devm_kfree(dev, tmp_res); 1061 return -EIO; 1062 } 1063 1064 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params); 1065 if (IS_ERR(tmp_res->io)) { 1066 devm_kfree(dev, tmp_res); 1067 return PTR_ERR(tmp_res->io); 1068 } 1069 1070 tmp_res->type = type; 1071 1072 *res = tmp_res; 1073 1074 return 0; 1075} 1076 1077static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1078 bool minimum) 1079{ 1080 u64 frequency; 1081 u32 ticks; 1082 1083 /* 1084 * Compute ticks as follow: 1085 * 1086 * Ticks 1087 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1088 * Frequency 1089 */ 1090 frequency = priv->frequency; 1091 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ; 1092 /* 1093 * The number of ticks is rounded down and if minimum is equal to 1 1094 * then add one tick. 1095 */ 1096 if (minimum) 1097 ticks++; 1098 1099 return ticks; 1100} 1101 1102static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1103 u32 mask, u8 shift) 1104{ 1105 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1106 1107 return val; 1108} 1109 1110static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1111 const struct mlxbf_i2c_timings *timings) 1112{ 1113 u32 timer; 1114 1115 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1116 false, MLXBF_I2C_MASK_16, 1117 MLXBF_I2C_SHIFT_0); 1118 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1119 false, MLXBF_I2C_MASK_16, 1120 MLXBF_I2C_SHIFT_16); 1121 writel(timer, priv->smbus->io + 1122 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1123 1124 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1125 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1126 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1127 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1128 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1129 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1130 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1131 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1132 writel(timer, priv->smbus->io + 1133 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1134 1135 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1136 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1137 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1138 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1139 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1140 1141 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1142 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1143 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1144 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1145 writel(timer, priv->smbus->io + 1146 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1147 1148 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1149 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1150 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1151 1152 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1153 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1154 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1155 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1156 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1157 1158 timer = timings->timeout; 1159 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1160} 1161 1162enum mlxbf_i2c_timings_config { 1163 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1164 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1165 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1166}; 1167 1168/* 1169 * Note that the mlxbf_i2c_timings->timeout value is not related to the 1170 * bus frequency, it is impacted by the time it takes the driver to 1171 * complete data transmission before transaction abort. 1172 */ 1173static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1174 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1175 .scl_high = 4810, 1176 .scl_low = 5000, 1177 .hold_start = 4000, 1178 .setup_start = 4800, 1179 .setup_stop = 4000, 1180 .setup_data = 250, 1181 .sda_rise = 50, 1182 .sda_fall = 50, 1183 .scl_rise = 50, 1184 .scl_fall = 50, 1185 .hold_data = 300, 1186 .buf = 20000, 1187 .thigh_max = 5000, 1188 .timeout = 106500 1189 }, 1190 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1191 .scl_high = 1011, 1192 .scl_low = 1300, 1193 .hold_start = 600, 1194 .setup_start = 700, 1195 .setup_stop = 600, 1196 .setup_data = 100, 1197 .sda_rise = 50, 1198 .sda_fall = 50, 1199 .scl_rise = 50, 1200 .scl_fall = 50, 1201 .hold_data = 300, 1202 .buf = 20000, 1203 .thigh_max = 5000, 1204 .timeout = 106500 1205 }, 1206 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1207 .scl_high = 600, 1208 .scl_low = 1300, 1209 .hold_start = 600, 1210 .setup_start = 600, 1211 .setup_stop = 600, 1212 .setup_data = 100, 1213 .sda_rise = 50, 1214 .sda_fall = 50, 1215 .scl_rise = 50, 1216 .scl_fall = 50, 1217 .hold_data = 300, 1218 .buf = 20000, 1219 .thigh_max = 5000, 1220 .timeout = 106500 1221 } 1222}; 1223 1224static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1225 struct mlxbf_i2c_priv *priv) 1226{ 1227 enum mlxbf_i2c_timings_config config_idx; 1228 struct device *dev = &pdev->dev; 1229 u32 config_khz; 1230 1231 int ret; 1232 1233 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1234 if (ret < 0) 1235 config_khz = MLXBF_I2C_TIMING_100KHZ; 1236 1237 switch (config_khz) { 1238 default: 1239 /* Default settings is 100 KHz. */ 1240 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1241 config_khz); 1242 fallthrough; 1243 case MLXBF_I2C_TIMING_100KHZ: 1244 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1245 break; 1246 1247 case MLXBF_I2C_TIMING_400KHZ: 1248 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1249 break; 1250 1251 case MLXBF_I2C_TIMING_1000KHZ: 1252 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1253 break; 1254 } 1255 1256 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1257 1258 return 0; 1259} 1260 1261static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1262 struct mlxbf_i2c_priv *priv) 1263{ 1264 struct mlxbf_i2c_resource *gpio_res; 1265 struct device *dev = &pdev->dev; 1266 struct resource *params; 1267 resource_size_t size; 1268 1269 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1270 if (!gpio_res) 1271 return -EPERM; 1272 1273 /* 1274 * The GPIO region in TYU space is shared among I2C busses. 1275 * This function MUST be serialized to avoid racing when 1276 * claiming the memory region and/or setting up the GPIO. 1277 */ 1278 lockdep_assert_held(gpio_res->lock); 1279 1280 /* Check whether the memory map exist. */ 1281 if (gpio_res->io) 1282 return 0; 1283 1284 params = gpio_res->params; 1285 size = resource_size(params); 1286 1287 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1288 return -EFAULT; 1289 1290 gpio_res->io = devm_ioremap(dev, params->start, size); 1291 if (!gpio_res->io) { 1292 devm_release_mem_region(dev, params->start, size); 1293 return -ENOMEM; 1294 } 1295 1296 return 0; 1297} 1298 1299static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1300 struct mlxbf_i2c_priv *priv) 1301{ 1302 struct mlxbf_i2c_resource *gpio_res; 1303 struct device *dev = &pdev->dev; 1304 struct resource *params; 1305 1306 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1307 if (!gpio_res) 1308 return 0; 1309 1310 mutex_lock(gpio_res->lock); 1311 1312 if (gpio_res->io) { 1313 /* Release the GPIO resource. */ 1314 params = gpio_res->params; 1315 devm_iounmap(dev, gpio_res->io); 1316 devm_release_mem_region(dev, params->start, 1317 resource_size(params)); 1318 } 1319 1320 mutex_unlock(gpio_res->lock); 1321 1322 return 0; 1323} 1324 1325static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1326 struct mlxbf_i2c_priv *priv) 1327{ 1328 struct mlxbf_i2c_resource *corepll_res; 1329 struct device *dev = &pdev->dev; 1330 struct resource *params; 1331 resource_size_t size; 1332 1333 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1334 MLXBF_I2C_COREPLL_RES); 1335 if (!corepll_res) 1336 return -EPERM; 1337 1338 /* 1339 * The COREPLL region in TYU space is shared among I2C busses. 1340 * This function MUST be serialized to avoid racing when 1341 * claiming the memory region. 1342 */ 1343 lockdep_assert_held(corepll_res->lock); 1344 1345 /* Check whether the memory map exist. */ 1346 if (corepll_res->io) 1347 return 0; 1348 1349 params = corepll_res->params; 1350 size = resource_size(params); 1351 1352 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1353 return -EFAULT; 1354 1355 corepll_res->io = devm_ioremap(dev, params->start, size); 1356 if (!corepll_res->io) { 1357 devm_release_mem_region(dev, params->start, size); 1358 return -ENOMEM; 1359 } 1360 1361 return 0; 1362} 1363 1364static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1365 struct mlxbf_i2c_priv *priv) 1366{ 1367 struct mlxbf_i2c_resource *corepll_res; 1368 struct device *dev = &pdev->dev; 1369 struct resource *params; 1370 1371 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1372 MLXBF_I2C_COREPLL_RES); 1373 1374 mutex_lock(corepll_res->lock); 1375 1376 if (corepll_res->io) { 1377 /* Release the CorePLL resource. */ 1378 params = corepll_res->params; 1379 devm_iounmap(dev, corepll_res->io); 1380 devm_release_mem_region(dev, params->start, 1381 resource_size(params)); 1382 } 1383 1384 mutex_unlock(corepll_res->lock); 1385 1386 return 0; 1387} 1388 1389static int mlxbf_i2c_init_master(struct platform_device *pdev, 1390 struct mlxbf_i2c_priv *priv) 1391{ 1392 struct mlxbf_i2c_resource *gpio_res; 1393 struct device *dev = &pdev->dev; 1394 u32 config_reg; 1395 int ret; 1396 1397 /* This configuration is only needed for BlueField 1. */ 1398 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1399 return 0; 1400 1401 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1402 if (!gpio_res) 1403 return -EPERM; 1404 1405 /* 1406 * The GPIO region in TYU space is shared among I2C busses. 1407 * This function MUST be serialized to avoid racing when 1408 * claiming the memory region and/or setting up the GPIO. 1409 */ 1410 1411 mutex_lock(gpio_res->lock); 1412 1413 ret = mlxbf_i2c_get_gpio(pdev, priv); 1414 if (ret < 0) { 1415 dev_err(dev, "Failed to get gpio resource"); 1416 mutex_unlock(gpio_res->lock); 1417 return ret; 1418 } 1419 1420 /* 1421 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1422 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1423 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1424 * instead of HW_OE. 1425 * For now, we do not reset the GPIO state when the driver is removed. 1426 * First, it is not necessary to disable the bus since we are using 1427 * the same busses. Then, some busses might be shared among Linux and 1428 * platform firmware; disabling the bus might compromise the system 1429 * functionality. 1430 */ 1431 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1432 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1433 config_reg); 1434 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1435 1436 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1437 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1438 config_reg); 1439 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1440 1441 mutex_unlock(gpio_res->lock); 1442 1443 return 0; 1444} 1445 1446static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1447{ 1448 u64 core_frequency; 1449 u8 core_od, core_r; 1450 u32 corepll_val; 1451 u16 core_f; 1452 1453 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1454 1455 /* Get Core PLL configuration bits. */ 1456 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val); 1457 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val); 1458 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val); 1459 1460 /* 1461 * Compute PLL output frequency as follow: 1462 * 1463 * CORE_F + 1 1464 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1465 * (CORE_R + 1) * (CORE_OD + 1) 1466 * 1467 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1468 * and PadFrequency, respectively. 1469 */ 1470 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f); 1471 core_frequency /= (++core_r) * (++core_od); 1472 1473 return core_frequency; 1474} 1475 1476static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1477{ 1478 u32 corepll_reg1_val, corepll_reg2_val; 1479 u64 corepll_frequency; 1480 u8 core_od, core_r; 1481 u32 core_f; 1482 1483 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1484 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1485 1486 /* Get Core PLL configuration bits */ 1487 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val); 1488 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val); 1489 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val); 1490 1491 /* 1492 * Compute PLL output frequency as follow: 1493 * 1494 * CORE_F / 16384 1495 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1496 * (CORE_R + 1) * (CORE_OD + 1) 1497 * 1498 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1499 * and PadFrequency, respectively. 1500 */ 1501 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST; 1502 corepll_frequency /= (++core_r) * (++core_od); 1503 1504 return corepll_frequency; 1505} 1506 1507static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1508 struct mlxbf_i2c_priv *priv) 1509{ 1510 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1511 struct mlxbf_i2c_resource *corepll_res; 1512 struct device *dev = &pdev->dev; 1513 u64 *freq = &priv->frequency; 1514 int ret; 1515 1516 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1517 MLXBF_I2C_COREPLL_RES); 1518 if (!corepll_res) 1519 return -EPERM; 1520 1521 /* 1522 * First, check whether the TYU core Clock frequency is set. 1523 * The TYU core frequency is the same for all I2C busses; when 1524 * the first device gets probed the frequency is determined and 1525 * stored into a globally visible variable. So, first of all, 1526 * check whether the frequency is already set. Here, we assume 1527 * that the frequency is expected to be greater than 0. 1528 */ 1529 mutex_lock(corepll_res->lock); 1530 if (!mlxbf_i2c_corepll_frequency) { 1531 if (!chip->calculate_freq) { 1532 mutex_unlock(corepll_res->lock); 1533 return -EPERM; 1534 } 1535 1536 ret = mlxbf_i2c_get_corepll(pdev, priv); 1537 if (ret < 0) { 1538 dev_err(dev, "Failed to get corePLL resource"); 1539 mutex_unlock(corepll_res->lock); 1540 return ret; 1541 } 1542 1543 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1544 } 1545 mutex_unlock(corepll_res->lock); 1546 1547 *freq = mlxbf_i2c_corepll_frequency; 1548 1549 return 0; 1550} 1551 1552static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr) 1553{ 1554 u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask; 1555 u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail; 1556 bool avail, disabled; 1557 1558 disabled = false; 1559 avail = false; 1560 1561 if (!priv) 1562 return -EPERM; 1563 1564 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1565 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1566 1567 /* 1568 * Read the slave registers. There are 4 * 32-bit slave registers. 1569 * Each slave register can hold up to 4 * 8-bit slave configuration 1570 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1571 */ 1572 for (reg = 0; reg < reg_cnt; reg++) { 1573 slave_reg = readl(priv->smbus->io + 1574 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1575 /* 1576 * Each register holds 4 slave addresses. So, we have to keep 1577 * the byte order consistent with the value read in order to 1578 * update the register correctly, if needed. 1579 */ 1580 slave_reg_tmp = slave_reg; 1581 for (byte = 0; byte < 4; byte++) { 1582 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1583 1584 /* 1585 * Mark the first available slave address slot, i.e. its 1586 * enabled bit should be unset. This slot might be used 1587 * later on to register our slave. 1588 */ 1589 if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) { 1590 avail = true; 1591 reg_avail = reg; 1592 byte_avail = byte; 1593 slave_reg_avail = slave_reg; 1594 } 1595 1596 /* 1597 * Parse slave address bytes and check whether the 1598 * slave address already exists and it's enabled, 1599 * i.e. most significant bit is set. 1600 */ 1601 if ((addr_tmp & slave_addr_mask) == addr) { 1602 if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) 1603 return 0; 1604 disabled = true; 1605 break; 1606 } 1607 1608 /* Parse next byte. */ 1609 slave_reg_tmp >>= 8; 1610 } 1611 1612 /* Exit the loop if the slave address is found. */ 1613 if (disabled) 1614 break; 1615 } 1616 1617 if (!avail && !disabled) 1618 return -EINVAL; /* No room for a new slave address. */ 1619 1620 if (avail && !disabled) { 1621 reg = reg_avail; 1622 byte = byte_avail; 1623 /* Set the slave address. */ 1624 slave_reg_avail &= ~(slave_addr_mask << (byte * 8)); 1625 slave_reg_avail |= addr << (byte * 8); 1626 slave_reg = slave_reg_avail; 1627 } 1628 1629 /* Enable the slave address and update the register. */ 1630 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8); 1631 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1632 reg * 0x4); 1633 1634 return 0; 1635} 1636 1637static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv) 1638{ 1639 u32 slave_reg, slave_reg_tmp, slave_addr_mask; 1640 u8 addr, addr_tmp, reg, reg_cnt, slave_byte; 1641 struct i2c_client *client = priv->slave; 1642 bool exist; 1643 1644 exist = false; 1645 1646 addr = client->addr; 1647 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1648 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1649 1650 /* 1651 * Read the slave registers. There are 4 * 32-bit slave registers. 1652 * Each slave register can hold up to 4 * 8-bit slave configuration 1653 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1654 */ 1655 for (reg = 0; reg < reg_cnt; reg++) { 1656 slave_reg = readl(priv->smbus->io + 1657 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1658 1659 /* Check whether the address slots are empty. */ 1660 if (slave_reg == 0) 1661 continue; 1662 1663 /* 1664 * Each register holds 4 slave addresses. So, we have to keep 1665 * the byte order consistent with the value read in order to 1666 * update the register correctly, if needed. 1667 */ 1668 slave_reg_tmp = slave_reg; 1669 slave_byte = 0; 1670 while (slave_reg_tmp != 0) { 1671 addr_tmp = slave_reg_tmp & slave_addr_mask; 1672 /* 1673 * Parse slave address bytes and check whether the 1674 * slave address already exists. 1675 */ 1676 if (addr_tmp == addr) { 1677 exist = true; 1678 break; 1679 } 1680 1681 /* Parse next byte. */ 1682 slave_reg_tmp >>= 8; 1683 slave_byte += 1; 1684 } 1685 1686 /* Exit the loop if the slave address is found. */ 1687 if (exist) 1688 break; 1689 } 1690 1691 if (!exist) 1692 return 0; /* Slave is not registered, nothing to do. */ 1693 1694 /* Cleanup the slave address slot. */ 1695 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8)); 1696 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1697 reg * 0x4); 1698 1699 return 0; 1700} 1701 1702static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1703 struct mlxbf_i2c_priv *priv) 1704{ 1705 struct mlxbf_i2c_resource *coalesce_res; 1706 struct resource *params; 1707 resource_size_t size; 1708 int ret = 0; 1709 1710 /* 1711 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1712 * resource in the next generations of BlueField. 1713 */ 1714 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1715 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1716 MLXBF_I2C_COALESCE_RES); 1717 if (!coalesce_res) 1718 return -EPERM; 1719 1720 /* 1721 * The Cause Coalesce group in TYU space is shared among 1722 * I2C busses. This function MUST be serialized to avoid 1723 * racing when claiming the memory region. 1724 */ 1725 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1726 1727 /* Check whether the memory map exist. */ 1728 if (coalesce_res->io) { 1729 priv->coalesce = coalesce_res; 1730 return 0; 1731 } 1732 1733 params = coalesce_res->params; 1734 size = resource_size(params); 1735 1736 if (!request_mem_region(params->start, size, params->name)) 1737 return -EFAULT; 1738 1739 coalesce_res->io = ioremap(params->start, size); 1740 if (!coalesce_res->io) { 1741 release_mem_region(params->start, size); 1742 return -ENOMEM; 1743 } 1744 1745 priv->coalesce = coalesce_res; 1746 1747 } else { 1748 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1749 MLXBF_I2C_COALESCE_RES); 1750 } 1751 1752 return ret; 1753} 1754 1755static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1756 struct mlxbf_i2c_priv *priv) 1757{ 1758 struct mlxbf_i2c_resource *coalesce_res; 1759 struct device *dev = &pdev->dev; 1760 struct resource *params; 1761 resource_size_t size; 1762 1763 coalesce_res = priv->coalesce; 1764 1765 if (coalesce_res->io) { 1766 params = coalesce_res->params; 1767 size = resource_size(params); 1768 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1769 mutex_lock(coalesce_res->lock); 1770 iounmap(coalesce_res->io); 1771 release_mem_region(params->start, size); 1772 mutex_unlock(coalesce_res->lock); 1773 } else { 1774 devm_release_mem_region(dev, params->start, size); 1775 } 1776 } 1777 1778 return 0; 1779} 1780 1781static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1782 struct mlxbf_i2c_priv *priv) 1783{ 1784 struct device *dev = &pdev->dev; 1785 u32 int_reg; 1786 int ret; 1787 1788 /* Reset FSM. */ 1789 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1790 1791 /* 1792 * Enable slave cause interrupt bits. Drive 1793 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1794 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1795 * masters issue a Read and Write, respectively. But, clear all 1796 * interrupts first. 1797 */ 1798 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1799 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1800 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1801 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1802 1803 /* Finally, set the 'ready' bit to start handling transactions. */ 1804 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1805 1806 /* Initialize the cause coalesce resource. */ 1807 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1808 if (ret < 0) { 1809 dev_err(dev, "failed to initialize cause coalesce\n"); 1810 return ret; 1811 } 1812 1813 return 0; 1814} 1815 1816static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1817 bool *write) 1818{ 1819 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1820 u32 coalesce0_reg, cause_reg; 1821 u8 slave_shift, is_set; 1822 1823 *write = false; 1824 *read = false; 1825 1826 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1827 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1828 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1829 1830 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1831 is_set = coalesce0_reg & (1 << slave_shift); 1832 1833 if (!is_set) 1834 return false; 1835 1836 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1837 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1838 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1839 *read = true; 1840 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1841 *write = true; 1842 1843 /* Clear cause bits. */ 1844 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1845 1846 return true; 1847} 1848 1849static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv, 1850 u32 timeout) 1851{ 1852 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL; 1853 u32 addr = MLXBF_I2C_CAUSE_ARBITER; 1854 1855 if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout)) 1856 return true; 1857 1858 return false; 1859} 1860 1861/* Send byte to 'external' smbus master. */ 1862static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1863{ 1864 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1865 u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size; 1866 struct i2c_client *slave = priv->slave; 1867 u32 control32, data32; 1868 int ret; 1869 1870 if (!slave) 1871 return -EINVAL; 1872 1873 addr = 0; 1874 byte = 0; 1875 desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE; 1876 1877 /* 1878 * Read bytes received from the external master. These bytes should 1879 * be located in the first data descriptor register of the slave GW. 1880 * These bytes are the slave address byte and the internal register 1881 * address, if supplied. 1882 */ 1883 if (recv_bytes > 0) { 1884 data32 = ioread32be(priv->smbus->io + 1885 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1886 1887 /* Parse the received bytes. */ 1888 switch (recv_bytes) { 1889 case 2: 1890 byte = (data32 >> 8) & GENMASK(7, 0); 1891 fallthrough; 1892 case 1: 1893 addr = (data32 & GENMASK(7, 0)) >> 1; 1894 } 1895 1896 /* Check whether it's our slave address. */ 1897 if (slave->addr != addr) 1898 return -EINVAL; 1899 } 1900 1901 /* 1902 * I2C read transactions may start by a WRITE followed by a READ. 1903 * Indeed, most slave devices would expect the internal address 1904 * following the slave address byte. So, write that byte first, 1905 * and then, send the requested data bytes to the master. 1906 */ 1907 if (recv_bytes > 1) { 1908 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1909 value = byte; 1910 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1911 &value); 1912 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1913 1914 if (ret < 0) 1915 return ret; 1916 } 1917 1918 /* 1919 * Now, send data to the master; currently, the driver supports 1920 * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the 1921 * hardware can send up to 128 bytes per transfer. That is the 1922 * size of its data registers. 1923 */ 1924 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1925 1926 for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) { 1927 data_desc[byte_cnt] = value; 1928 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1929 } 1930 1931 /* Send a stop condition to the backend. */ 1932 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1933 1934 /* Handle the actual transfer. */ 1935 1936 /* Set the number of bytes to write to master. */ 1937 write_size = (byte_cnt - 1) & 0x7f; 1938 1939 /* Write data to Slave GW data descriptor. */ 1940 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1941 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1942 1943 pec_en = 0; /* Disable PEC since it is not supported. */ 1944 1945 /* Prepare control word. */ 1946 control32 = MLXBF_I2C_SLAVE_ENABLE; 1947 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1948 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1949 1950 writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1951 1952 /* 1953 * Wait until the transfer is completed; the driver will wait 1954 * until the GW is idle, a cause will rise on fall of GW busy. 1955 */ 1956 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT); 1957 1958 /* Release the Slave GW. */ 1959 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1960 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1961 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1962 1963 return 0; 1964} 1965 1966/* Receive bytes from 'external' smbus master. */ 1967static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1968{ 1969 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1970 struct i2c_client *slave = priv->slave; 1971 u8 value, byte, addr; 1972 int ret = 0; 1973 1974 if (!slave) 1975 return -EINVAL; 1976 1977 /* Read data from Slave GW data descriptor. */ 1978 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1979 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1980 1981 /* Check whether its our slave address. */ 1982 addr = data_desc[0] >> 1; 1983 if (slave->addr != addr) 1984 return -EINVAL; 1985 1986 /* 1987 * Notify the slave backend; another I2C master wants to write data 1988 * to us. This event is sent once the slave address and the write bit 1989 * is detected. 1990 */ 1991 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1992 1993 /* Send the received data to the slave backend. */ 1994 for (byte = 1; byte < recv_bytes; byte++) { 1995 value = data_desc[byte]; 1996 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1997 &value); 1998 if (ret < 0) 1999 break; 2000 } 2001 2002 /* Send a stop condition to the backend. */ 2003 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 2004 2005 /* Release the Slave GW. */ 2006 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2007 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 2008 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 2009 2010 return ret; 2011} 2012 2013static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr) 2014{ 2015 struct mlxbf_i2c_priv *priv = ptr; 2016 bool read, write, irq_is_set; 2017 u32 rw_bytes_reg; 2018 u8 recv_bytes; 2019 2020 /* 2021 * Read TYU interrupt register and determine the source of the 2022 * interrupt. Based on the source of the interrupt one of the 2023 * following actions are performed: 2024 * - Receive data and send response to master. 2025 * - Send data and release slave GW. 2026 * 2027 * Handle read/write transaction only. CRmaster and Iarp requests 2028 * are ignored for now. 2029 */ 2030 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 2031 if (!irq_is_set || (!read && !write)) { 2032 /* Nothing to do here, interrupt was not from this device. */ 2033 return IRQ_NONE; 2034 } 2035 2036 /* 2037 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 2038 * bytes from/to master. These are defined by 8-bits each. If the lower 2039 * 8 bits are set, then the master expect to read N bytes from the 2040 * slave, if the higher 8 bits are sent then the slave expect N bytes 2041 * from the master. 2042 */ 2043 rw_bytes_reg = readl(priv->smbus->io + 2044 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2045 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2046 2047 /* 2048 * For now, the slave supports 128 bytes transfer. Discard remaining 2049 * data bytes if the master wrote more than 2050 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 2051 * data descriptor. 2052 * 2053 * Note that we will never expect to transfer more than 128 bytes; as 2054 * specified in the SMBus standard, block transactions cannot exceed 2055 * 32 bytes. 2056 */ 2057 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2058 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2059 2060 if (read) 2061 mlxbf_smbus_irq_send(priv, recv_bytes); 2062 else 2063 mlxbf_smbus_irq_recv(priv, recv_bytes); 2064 2065 return IRQ_HANDLED; 2066} 2067 2068/* Return negative errno on error. */ 2069static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2070 unsigned short flags, char read_write, 2071 u8 command, int size, 2072 union i2c_smbus_data *data) 2073{ 2074 struct mlxbf_i2c_smbus_request request = { 0 }; 2075 struct mlxbf_i2c_priv *priv; 2076 bool read, pec; 2077 u8 byte_cnt; 2078 2079 request.slave = addr; 2080 2081 read = (read_write == I2C_SMBUS_READ); 2082 pec = flags & I2C_FUNC_SMBUS_PEC; 2083 2084 switch (size) { 2085 case I2C_SMBUS_QUICK: 2086 mlxbf_i2c_smbus_quick_command(&request, read); 2087 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2088 break; 2089 2090 case I2C_SMBUS_BYTE: 2091 mlxbf_i2c_smbus_byte_func(&request, 2092 read ? &data->byte : &command, read, 2093 pec); 2094 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2095 read ? "read" : "write", addr); 2096 break; 2097 2098 case I2C_SMBUS_BYTE_DATA: 2099 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2100 read, pec); 2101 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2102 read ? "read" : "write", command, addr); 2103 break; 2104 2105 case I2C_SMBUS_WORD_DATA: 2106 mlxbf_i2c_smbus_data_word_func(&request, &command, 2107 (u8 *)&data->word, read, pec); 2108 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2109 read ? "read" : "write", command, addr); 2110 break; 2111 2112 case I2C_SMBUS_I2C_BLOCK_DATA: 2113 byte_cnt = data->block[0]; 2114 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2115 &byte_cnt, read, pec); 2116 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2117 read ? "read" : "write", byte_cnt, command, addr); 2118 break; 2119 2120 case I2C_SMBUS_BLOCK_DATA: 2121 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2122 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2123 &byte_cnt, read, pec); 2124 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2125 read ? "read" : "write", byte_cnt, command, addr); 2126 break; 2127 2128 case I2C_FUNC_SMBUS_PROC_CALL: 2129 mlxbf_i2c_smbus_process_call_func(&request, &command, 2130 (u8 *)&data->word, pec); 2131 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2132 command, addr); 2133 break; 2134 2135 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2136 byte_cnt = data->block[0]; 2137 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2138 data->block, &byte_cnt, 2139 pec); 2140 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2141 byte_cnt, addr); 2142 break; 2143 2144 default: 2145 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2146 size); 2147 return -EOPNOTSUPP; 2148 } 2149 2150 priv = i2c_get_adapdata(adap); 2151 2152 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2153} 2154 2155static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2156{ 2157 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2158 int ret; 2159 2160 if (priv->slave) 2161 return -EBUSY; 2162 2163 /* 2164 * Do not support ten bit chip address and do not use Packet Error 2165 * Checking (PEC). 2166 */ 2167 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) 2168 return -EAFNOSUPPORT; 2169 2170 ret = mlxbf_slave_enable(priv, slave->addr); 2171 if (ret < 0) 2172 return ret; 2173 2174 priv->slave = slave; 2175 2176 return 0; 2177} 2178 2179static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2180{ 2181 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2182 int ret; 2183 2184 WARN_ON(!priv->slave); 2185 2186 /* Unregister slave, i.e. disable the slave address in hardware. */ 2187 ret = mlxbf_slave_disable(priv); 2188 if (ret < 0) 2189 return ret; 2190 2191 priv->slave = NULL; 2192 2193 return 0; 2194} 2195 2196static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2197{ 2198 return MLXBF_I2C_FUNC_ALL; 2199} 2200 2201static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2202 [MLXBF_I2C_CHIP_TYPE_1] = { 2203 .type = MLXBF_I2C_CHIP_TYPE_1, 2204 .shared_res = { 2205 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2206 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2207 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2208 }, 2209 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu 2210 }, 2211 [MLXBF_I2C_CHIP_TYPE_2] = { 2212 .type = MLXBF_I2C_CHIP_TYPE_2, 2213 .shared_res = { 2214 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2215 }, 2216 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu 2217 } 2218}; 2219 2220static const struct i2c_algorithm mlxbf_i2c_algo = { 2221 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2222 .functionality = mlxbf_i2c_functionality, 2223 .reg_slave = mlxbf_i2c_reg_slave, 2224 .unreg_slave = mlxbf_i2c_unreg_slave, 2225}; 2226 2227static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2228 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2229 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2230}; 2231 2232static const struct of_device_id mlxbf_i2c_dt_ids[] = { 2233 { 2234 .compatible = "mellanox,i2c-mlxbf1", 2235 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] 2236 }, 2237 { 2238 .compatible = "mellanox,i2c-mlxbf2", 2239 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] 2240 }, 2241 {}, 2242}; 2243 2244MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids); 2245 2246#ifdef CONFIG_ACPI 2247static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2248 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2249 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2250 {}, 2251}; 2252 2253MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2254 2255static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2256{ 2257 const struct acpi_device_id *aid; 2258 struct acpi_device *adev; 2259 unsigned long bus_id = 0; 2260 const char *uid; 2261 int ret; 2262 2263 if (acpi_disabled) 2264 return -ENOENT; 2265 2266 adev = ACPI_COMPANION(dev); 2267 if (!adev) 2268 return -ENXIO; 2269 2270 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2271 if (!aid) 2272 return -ENODEV; 2273 2274 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2275 2276 uid = acpi_device_uid(adev); 2277 if (!uid || !(*uid)) { 2278 dev_err(dev, "Cannot retrieve UID\n"); 2279 return -ENODEV; 2280 } 2281 2282 ret = kstrtoul(uid, 0, &bus_id); 2283 if (!ret) 2284 priv->bus = bus_id; 2285 2286 return ret; 2287} 2288#else 2289static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2290{ 2291 return -ENOENT; 2292} 2293#endif /* CONFIG_ACPI */ 2294 2295static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2296{ 2297 const struct of_device_id *oid; 2298 int bus_id = -1; 2299 2300 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 2301 oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node); 2302 if (!oid) 2303 return -ENODEV; 2304 2305 priv->chip = oid->data; 2306 2307 bus_id = of_alias_get_id(dev->of_node, "i2c"); 2308 if (bus_id >= 0) 2309 priv->bus = bus_id; 2310 } 2311 2312 if (bus_id < 0) { 2313 dev_err(dev, "Cannot get bus id"); 2314 return bus_id; 2315 } 2316 2317 return 0; 2318} 2319 2320static int mlxbf_i2c_probe(struct platform_device *pdev) 2321{ 2322 struct device *dev = &pdev->dev; 2323 struct mlxbf_i2c_priv *priv; 2324 struct i2c_adapter *adap; 2325 int irq, ret; 2326 2327 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2328 if (!priv) 2329 return -ENOMEM; 2330 2331 ret = mlxbf_i2c_acpi_probe(dev, priv); 2332 if (ret < 0 && ret != -ENOENT && ret != -ENXIO) 2333 ret = mlxbf_i2c_of_probe(dev, priv); 2334 2335 if (ret < 0) 2336 return ret; 2337 2338 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2339 MLXBF_I2C_SMBUS_RES); 2340 if (ret < 0) { 2341 dev_err(dev, "Cannot fetch smbus resource info"); 2342 return ret; 2343 } 2344 2345 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2346 MLXBF_I2C_MST_CAUSE_RES); 2347 if (ret < 0) { 2348 dev_err(dev, "Cannot fetch cause master resource info"); 2349 return ret; 2350 } 2351 2352 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2353 MLXBF_I2C_SLV_CAUSE_RES); 2354 if (ret < 0) { 2355 dev_err(dev, "Cannot fetch cause slave resource info"); 2356 return ret; 2357 } 2358 2359 adap = &priv->adap; 2360 adap->owner = THIS_MODULE; 2361 adap->class = I2C_CLASS_HWMON; 2362 adap->algo = &mlxbf_i2c_algo; 2363 adap->quirks = &mlxbf_i2c_quirks; 2364 adap->dev.parent = dev; 2365 adap->dev.of_node = dev->of_node; 2366 adap->nr = priv->bus; 2367 2368 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2369 i2c_set_adapdata(adap, priv); 2370 2371 /* Read Core PLL frequency. */ 2372 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2373 if (ret < 0) { 2374 dev_err(dev, "cannot get core clock frequency\n"); 2375 /* Set to default value. */ 2376 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2377 } 2378 2379 /* 2380 * Initialize master. 2381 * Note that a physical bus might be shared among Linux and firmware 2382 * (e.g., ATF). Thus, the bus should be initialized and ready and 2383 * bus initialization would be unnecessary. This requires additional 2384 * knowledge about physical busses. But, since an extra initialization 2385 * does not really hurt, then keep the code as is. 2386 */ 2387 ret = mlxbf_i2c_init_master(pdev, priv); 2388 if (ret < 0) { 2389 dev_err(dev, "failed to initialize smbus master %d", 2390 priv->bus); 2391 return ret; 2392 } 2393 2394 mlxbf_i2c_init_timings(pdev, priv); 2395 2396 mlxbf_i2c_init_slave(pdev, priv); 2397 2398 irq = platform_get_irq(pdev, 0); 2399 if (irq < 0) 2400 return irq; 2401 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq, 2402 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED, 2403 dev_name(dev), priv); 2404 if (ret < 0) { 2405 dev_err(dev, "Cannot get irq %d\n", irq); 2406 return ret; 2407 } 2408 2409 priv->irq = irq; 2410 2411 platform_set_drvdata(pdev, priv); 2412 2413 ret = i2c_add_numbered_adapter(adap); 2414 if (ret < 0) 2415 return ret; 2416 2417 mutex_lock(&mlxbf_i2c_bus_lock); 2418 mlxbf_i2c_bus_count++; 2419 mutex_unlock(&mlxbf_i2c_bus_lock); 2420 2421 return 0; 2422} 2423 2424static int mlxbf_i2c_remove(struct platform_device *pdev) 2425{ 2426 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2427 struct device *dev = &pdev->dev; 2428 struct resource *params; 2429 2430 params = priv->smbus->params; 2431 devm_release_mem_region(dev, params->start, resource_size(params)); 2432 2433 params = priv->mst_cause->params; 2434 devm_release_mem_region(dev, params->start, resource_size(params)); 2435 2436 params = priv->slv_cause->params; 2437 devm_release_mem_region(dev, params->start, resource_size(params)); 2438 2439 /* 2440 * Release shared resources. This should be done when releasing 2441 * the I2C controller. 2442 */ 2443 mutex_lock(&mlxbf_i2c_bus_lock); 2444 if (--mlxbf_i2c_bus_count == 0) { 2445 mlxbf_i2c_release_coalesce(pdev, priv); 2446 mlxbf_i2c_release_corepll(pdev, priv); 2447 mlxbf_i2c_release_gpio(pdev, priv); 2448 } 2449 mutex_unlock(&mlxbf_i2c_bus_lock); 2450 2451 devm_free_irq(dev, priv->irq, priv); 2452 2453 i2c_del_adapter(&priv->adap); 2454 2455 return 0; 2456} 2457 2458static struct platform_driver mlxbf_i2c_driver = { 2459 .probe = mlxbf_i2c_probe, 2460 .remove = mlxbf_i2c_remove, 2461 .driver = { 2462 .name = "i2c-mlxbf", 2463 .of_match_table = mlxbf_i2c_dt_ids, 2464#ifdef CONFIG_ACPI 2465 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2466#endif /* CONFIG_ACPI */ 2467 }, 2468}; 2469 2470static int __init mlxbf_i2c_init(void) 2471{ 2472 mutex_init(&mlxbf_i2c_coalesce_lock); 2473 mutex_init(&mlxbf_i2c_corepll_lock); 2474 mutex_init(&mlxbf_i2c_gpio_lock); 2475 2476 mutex_init(&mlxbf_i2c_bus_lock); 2477 2478 return platform_driver_register(&mlxbf_i2c_driver); 2479} 2480module_init(mlxbf_i2c_init); 2481 2482static void __exit mlxbf_i2c_exit(void) 2483{ 2484 platform_driver_unregister(&mlxbf_i2c_driver); 2485 2486 mutex_destroy(&mlxbf_i2c_bus_lock); 2487 2488 mutex_destroy(&mlxbf_i2c_gpio_lock); 2489 mutex_destroy(&mlxbf_i2c_corepll_lock); 2490 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2491} 2492module_exit(mlxbf_i2c_exit); 2493 2494MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2495MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2496MODULE_LICENSE("GPL v2"); 2497