1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Synopsys DesignWare I2C adapter driver (master only).
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/export.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #include "i2c-designware-core.h"
25
i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)26 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
27 {
28 /* Configure Tx/Rx FIFO threshold levels */
29 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
30 regmap_write(dev->map, DW_IC_RX_TL, 0);
31
32 /* Configure the I2C master */
33 regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
34 }
35
i2c_dw_set_timings_master(struct dw_i2c_dev *dev)36 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
37 {
38 const char *mode_str, *fp_str = "";
39 u32 comp_param1;
40 u32 sda_falling_time, scl_falling_time;
41 struct i2c_timings *t = &dev->timings;
42 u32 ic_clk;
43 int ret;
44
45 ret = i2c_dw_acquire_lock(dev);
46 if (ret)
47 return ret;
48
49 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
50 i2c_dw_release_lock(dev);
51 if (ret)
52 return ret;
53
54 /* Set standard and fast speed dividers for high/low periods */
55 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
56 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
57
58 /* Calculate SCL timing parameters for standard mode if not set */
59 if (!dev->ss_hcnt || !dev->ss_lcnt) {
60 ic_clk = i2c_dw_clk_rate(dev);
61 dev->ss_hcnt =
62 i2c_dw_scl_hcnt(ic_clk,
63 4000, /* tHD;STA = tHIGH = 4.0 us */
64 sda_falling_time,
65 0, /* 0: DW default, 1: Ideal */
66 0); /* No offset */
67 dev->ss_lcnt =
68 i2c_dw_scl_lcnt(ic_clk,
69 4700, /* tLOW = 4.7 us */
70 scl_falling_time,
71 0); /* No offset */
72 }
73 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
74 dev->ss_hcnt, dev->ss_lcnt);
75
76 /*
77 * Set SCL timing parameters for fast mode or fast mode plus. Only
78 * difference is the timing parameter values since the registers are
79 * the same.
80 */
81 if (t->bus_freq_hz == 1000000) {
82 /*
83 * Check are Fast Mode Plus parameters available. Calculate
84 * SCL timing parameters for Fast Mode Plus if not set.
85 */
86 if (dev->fp_hcnt && dev->fp_lcnt) {
87 dev->fs_hcnt = dev->fp_hcnt;
88 dev->fs_lcnt = dev->fp_lcnt;
89 } else {
90 ic_clk = i2c_dw_clk_rate(dev);
91 dev->fs_hcnt =
92 i2c_dw_scl_hcnt(ic_clk,
93 260, /* tHIGH = 260 ns */
94 sda_falling_time,
95 0, /* DW default */
96 0); /* No offset */
97 dev->fs_lcnt =
98 i2c_dw_scl_lcnt(ic_clk,
99 500, /* tLOW = 500 ns */
100 scl_falling_time,
101 0); /* No offset */
102 }
103 fp_str = " Plus";
104 }
105 /*
106 * Calculate SCL timing parameters for fast mode if not set. They are
107 * needed also in high speed mode.
108 */
109 if (!dev->fs_hcnt || !dev->fs_lcnt) {
110 ic_clk = i2c_dw_clk_rate(dev);
111 dev->fs_hcnt =
112 i2c_dw_scl_hcnt(ic_clk,
113 600, /* tHD;STA = tHIGH = 0.6 us */
114 sda_falling_time,
115 0, /* 0: DW default, 1: Ideal */
116 0); /* No offset */
117 dev->fs_lcnt =
118 i2c_dw_scl_lcnt(ic_clk,
119 1300, /* tLOW = 1.3 us */
120 scl_falling_time,
121 0); /* No offset */
122 }
123 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
124 fp_str, dev->fs_hcnt, dev->fs_lcnt);
125
126 /* Check is high speed possible and fall back to fast mode if not */
127 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
128 DW_IC_CON_SPEED_HIGH) {
129 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
130 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
131 dev_err(dev->dev, "High Speed not supported!\n");
132 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
133 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
134 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
135 dev->hs_hcnt = 0;
136 dev->hs_lcnt = 0;
137 } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
138 ic_clk = i2c_dw_clk_rate(dev);
139 dev->hs_hcnt =
140 i2c_dw_scl_hcnt(ic_clk,
141 160, /* tHIGH = 160 ns */
142 sda_falling_time,
143 0, /* DW default */
144 0); /* No offset */
145 dev->hs_lcnt =
146 i2c_dw_scl_lcnt(ic_clk,
147 320, /* tLOW = 320 ns */
148 scl_falling_time,
149 0); /* No offset */
150 }
151 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
152 dev->hs_hcnt, dev->hs_lcnt);
153 }
154
155 ret = i2c_dw_set_sda_hold(dev);
156 if (ret)
157 goto out;
158
159 switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
160 case DW_IC_CON_SPEED_STD:
161 mode_str = "Standard Mode";
162 break;
163 case DW_IC_CON_SPEED_HIGH:
164 mode_str = "High Speed Mode";
165 break;
166 default:
167 mode_str = "Fast Mode";
168 }
169 dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
170
171 out:
172 return ret;
173 }
174
175 /**
176 * i2c_dw_init() - Initialize the designware I2C master hardware
177 * @dev: device private data
178 *
179 * This functions configures and enables the I2C master.
180 * This function is called during I2C init function, and in case of timeout at
181 * run time.
182 */
i2c_dw_init_master(struct dw_i2c_dev *dev)183 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
184 {
185 int ret;
186
187 ret = i2c_dw_acquire_lock(dev);
188 if (ret)
189 return ret;
190
191 /* Disable the adapter */
192 __i2c_dw_disable(dev);
193
194 /* Write standard speed timing parameters */
195 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
196 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
197
198 /* Write fast mode/fast mode plus timing parameters */
199 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
200 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
201
202 /* Write high speed timing parameters if supported */
203 if (dev->hs_hcnt && dev->hs_lcnt) {
204 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
205 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
206 }
207
208 /* Write SDA hold time if supported */
209 if (dev->sda_hold_time)
210 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
211
212 i2c_dw_configure_fifo_master(dev);
213 i2c_dw_release_lock(dev);
214
215 return 0;
216 }
217
i2c_dw_xfer_init(struct dw_i2c_dev *dev)218 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
219 {
220 struct i2c_msg *msgs = dev->msgs;
221 u32 ic_con = 0, ic_tar = 0;
222 u32 dummy;
223
224 /* Disable the adapter */
225 __i2c_dw_disable(dev);
226
227 /* If the slave address is ten bit address, enable 10BITADDR */
228 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
229 ic_con = DW_IC_CON_10BITADDR_MASTER;
230 /*
231 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
232 * mode has to be enabled via bit 12 of IC_TAR register.
233 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
234 * detected from registers.
235 */
236 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
237 }
238
239 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
240 ic_con);
241
242 /*
243 * Set the slave (target) address and enable 10-bit addressing mode
244 * if applicable.
245 */
246 regmap_write(dev->map, DW_IC_TAR,
247 msgs[dev->msg_write_idx].addr | ic_tar);
248
249 /* Enforce disabled interrupts (due to HW issues) */
250 i2c_dw_disable_int(dev);
251
252 /* Enable the adapter */
253 __i2c_dw_enable(dev);
254
255 /* Dummy read to avoid the register getting stuck on Bay Trail */
256 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
257
258 /* Clear and enable interrupts */
259 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
260 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
261 }
262
263 /*
264 * Initiate (and continue) low level master read/write transaction.
265 * This function is only called from i2c_dw_isr, and pumping i2c_msg
266 * messages into the tx buffer. Even if the size of i2c_msg data is
267 * longer than the size of the tx buffer, it handles everything.
268 */
269 static void
i2c_dw_xfer_msg(struct dw_i2c_dev *dev)270 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
271 {
272 struct i2c_msg *msgs = dev->msgs;
273 u32 intr_mask;
274 int tx_limit, rx_limit;
275 u32 addr = msgs[dev->msg_write_idx].addr;
276 u32 buf_len = dev->tx_buf_len;
277 u8 *buf = dev->tx_buf;
278 bool need_restart = false;
279 unsigned int flr;
280
281 intr_mask = DW_IC_INTR_MASTER_MASK;
282
283 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
284 u32 flags = msgs[dev->msg_write_idx].flags;
285
286 /*
287 * If target address has changed, we need to
288 * reprogram the target address in the I2C
289 * adapter when we are done with this transfer.
290 */
291 if (msgs[dev->msg_write_idx].addr != addr) {
292 dev_err(dev->dev,
293 "%s: invalid target address\n", __func__);
294 dev->msg_err = -EINVAL;
295 break;
296 }
297
298 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
299 /* new i2c_msg */
300 buf = msgs[dev->msg_write_idx].buf;
301 buf_len = msgs[dev->msg_write_idx].len;
302
303 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
304 * IC_RESTART_EN are set, we must manually
305 * set restart bit between messages.
306 */
307 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
308 (dev->msg_write_idx > 0))
309 need_restart = true;
310 }
311
312 regmap_read(dev->map, DW_IC_TXFLR, &flr);
313 tx_limit = dev->tx_fifo_depth - flr;
314
315 regmap_read(dev->map, DW_IC_RXFLR, &flr);
316 rx_limit = dev->rx_fifo_depth - flr;
317
318 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
319 u32 cmd = 0;
320
321 /*
322 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
323 * manually set the stop bit. However, it cannot be
324 * detected from the registers so we set it always
325 * when writing/reading the last byte.
326 */
327
328 /*
329 * i2c-core always sets the buffer length of
330 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
331 * be adjusted when receiving the first byte.
332 * Thus we can't stop the transaction here.
333 */
334 if (dev->msg_write_idx == dev->msgs_num - 1 &&
335 buf_len == 1 && !(flags & I2C_M_RECV_LEN))
336 cmd |= BIT(9);
337
338 if (need_restart) {
339 cmd |= BIT(10);
340 need_restart = false;
341 }
342
343 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
344
345 /* Avoid rx buffer overrun */
346 if (dev->rx_outstanding >= dev->rx_fifo_depth)
347 break;
348
349 regmap_write(dev->map, DW_IC_DATA_CMD,
350 cmd | 0x100);
351 rx_limit--;
352 dev->rx_outstanding++;
353 } else {
354 regmap_write(dev->map, DW_IC_DATA_CMD,
355 cmd | *buf++);
356 }
357 tx_limit--; buf_len--;
358 }
359
360 dev->tx_buf = buf;
361 dev->tx_buf_len = buf_len;
362
363 /*
364 * Because we don't know the buffer length in the
365 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop the
366 * transaction here. Also disable the TX_EMPTY IRQ
367 * while waiting for the data length byte to avoid the
368 * bogus interrupts flood.
369 */
370 if (flags & I2C_M_RECV_LEN) {
371 dev->status |= STATUS_WRITE_IN_PROGRESS;
372 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
373 break;
374 } else if (buf_len > 0) {
375 /* more bytes to be written */
376 dev->status |= STATUS_WRITE_IN_PROGRESS;
377 break;
378 } else
379 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
380 }
381
382 /*
383 * If i2c_msg index search is completed, we don't need TX_EMPTY
384 * interrupt any more.
385 */
386 if (dev->msg_write_idx == dev->msgs_num)
387 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
388
389 if (dev->msg_err)
390 intr_mask = 0;
391
392 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
393 }
394
395 static u8
i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)396 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
397 {
398 struct i2c_msg *msgs = dev->msgs;
399 u32 flags = msgs[dev->msg_read_idx].flags;
400
401 /*
402 * Adjust the buffer length and mask the flag
403 * after receiving the first byte.
404 */
405 len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
406 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
407 msgs[dev->msg_read_idx].len = len;
408 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
409
410 /*
411 * Received buffer length, re-enable TX_EMPTY interrupt
412 * to resume the SMBUS transaction.
413 */
414 regmap_update_bits(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_TX_EMPTY,
415 DW_IC_INTR_TX_EMPTY);
416
417 return len;
418 }
419
420 static void
i2c_dw_read(struct dw_i2c_dev *dev)421 i2c_dw_read(struct dw_i2c_dev *dev)
422 {
423 struct i2c_msg *msgs = dev->msgs;
424 unsigned int rx_valid;
425
426 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
427 u32 len, tmp;
428 u8 *buf;
429
430 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
431 continue;
432
433 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
434 len = msgs[dev->msg_read_idx].len;
435 buf = msgs[dev->msg_read_idx].buf;
436 } else {
437 len = dev->rx_buf_len;
438 buf = dev->rx_buf;
439 }
440
441 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
442
443 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
444 u32 flags = msgs[dev->msg_read_idx].flags;
445
446 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
447 /* Ensure length byte is a valid value */
448 if (flags & I2C_M_RECV_LEN) {
449 /*
450 * if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be
451 * detected from the registers, the controller can be
452 * disabled if the STOP bit is set. But it is only set
453 * after receiving block data response length in
454 * I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read
455 * another byte with STOP bit set when the block data
456 * response length is invalid to complete the transaction.
457 */
458 if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX)
459 tmp = 1;
460
461 len = i2c_dw_recv_len(dev, tmp);
462 }
463 *buf++ = tmp;
464 dev->rx_outstanding--;
465 }
466
467 if (len > 0) {
468 dev->status |= STATUS_READ_IN_PROGRESS;
469 dev->rx_buf_len = len;
470 dev->rx_buf = buf;
471 return;
472 } else
473 dev->status &= ~STATUS_READ_IN_PROGRESS;
474 }
475 }
476
477 /*
478 * Prepare controller for a transaction and call i2c_dw_xfer_msg.
479 */
480 static int
i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)481 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
482 {
483 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
484 int ret;
485
486 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
487
488 pm_runtime_get_sync(dev->dev);
489
490 if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
491 ret = -ESHUTDOWN;
492 goto done_nolock;
493 }
494
495 reinit_completion(&dev->cmd_complete);
496 dev->msgs = msgs;
497 dev->msgs_num = num;
498 dev->cmd_err = 0;
499 dev->msg_write_idx = 0;
500 dev->msg_read_idx = 0;
501 dev->msg_err = 0;
502 dev->status = STATUS_IDLE;
503 dev->abort_source = 0;
504 dev->rx_outstanding = 0;
505
506 ret = i2c_dw_acquire_lock(dev);
507 if (ret)
508 goto done_nolock;
509
510 ret = i2c_dw_wait_bus_not_busy(dev);
511 if (ret < 0)
512 goto done;
513
514 /* Start the transfers */
515 i2c_dw_xfer_init(dev);
516
517 /* Wait for tx to complete */
518 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
519 dev_err(dev->dev, "controller timed out\n");
520 /* i2c_dw_init implicitly disables the adapter */
521 i2c_recover_bus(&dev->adapter);
522 i2c_dw_init_master(dev);
523 ret = -ETIMEDOUT;
524 goto done;
525 }
526
527 /*
528 * We must disable the adapter before returning and signaling the end
529 * of the current transfer. Otherwise the hardware might continue
530 * generating interrupts which in turn causes a race condition with
531 * the following transfer. Needs some more investigation if the
532 * additional interrupts are a hardware bug or this driver doesn't
533 * handle them correctly yet.
534 */
535 __i2c_dw_disable_nowait(dev);
536
537 if (dev->msg_err) {
538 ret = dev->msg_err;
539 goto done;
540 }
541
542 /* No error */
543 if (likely(!dev->cmd_err && !dev->status)) {
544 ret = num;
545 goto done;
546 }
547
548 /* We have an error */
549 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
550 ret = i2c_dw_handle_tx_abort(dev);
551 goto done;
552 }
553
554 if (dev->status)
555 dev_err(dev->dev,
556 "transfer terminated early - interrupt latency too high?\n");
557
558 ret = -EIO;
559
560 done:
561 i2c_dw_release_lock(dev);
562
563 done_nolock:
564 pm_runtime_mark_last_busy(dev->dev);
565 pm_runtime_put_autosuspend(dev->dev);
566
567 return ret;
568 }
569
570 static const struct i2c_algorithm i2c_dw_algo = {
571 .master_xfer = i2c_dw_xfer,
572 .functionality = i2c_dw_func,
573 };
574
575 static const struct i2c_adapter_quirks i2c_dw_quirks = {
576 .flags = I2C_AQ_NO_ZERO_LEN,
577 };
578
i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)579 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
580 {
581 u32 stat, dummy;
582
583 /*
584 * The IC_INTR_STAT register just indicates "enabled" interrupts.
585 * The unmasked raw version of interrupt status bits is available
586 * in the IC_RAW_INTR_STAT register.
587 *
588 * That is,
589 * stat = readl(IC_INTR_STAT);
590 * equals to,
591 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
592 *
593 * The raw version might be useful for debugging purposes.
594 */
595 regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
596
597 /*
598 * Do not use the IC_CLR_INTR register to clear interrupts, or
599 * you'll miss some interrupts, triggered during the period from
600 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
601 *
602 * Instead, use the separately-prepared IC_CLR_* registers.
603 */
604 if (stat & DW_IC_INTR_RX_UNDER)
605 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
606 if (stat & DW_IC_INTR_RX_OVER)
607 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
608 if (stat & DW_IC_INTR_TX_OVER)
609 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
610 if (stat & DW_IC_INTR_RD_REQ)
611 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
612 if (stat & DW_IC_INTR_TX_ABRT) {
613 /*
614 * The IC_TX_ABRT_SOURCE register is cleared whenever
615 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
616 */
617 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
618 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
619 }
620 if (stat & DW_IC_INTR_RX_DONE)
621 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
622 if (stat & DW_IC_INTR_ACTIVITY)
623 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
624 if (stat & DW_IC_INTR_STOP_DET)
625 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
626 if (stat & DW_IC_INTR_START_DET)
627 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
628 if (stat & DW_IC_INTR_GEN_CALL)
629 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
630
631 return stat;
632 }
633
634 /*
635 * Interrupt service routine. This gets called whenever an I2C master interrupt
636 * occurs.
637 */
i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)638 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
639 {
640 u32 stat;
641
642 stat = i2c_dw_read_clear_intrbits(dev);
643 if (stat & DW_IC_INTR_TX_ABRT) {
644 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
645 dev->status = STATUS_IDLE;
646
647 /*
648 * Anytime TX_ABRT is set, the contents of the tx/rx
649 * buffers are flushed. Make sure to skip them.
650 */
651 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
652 goto tx_aborted;
653 }
654
655 if (stat & DW_IC_INTR_RX_FULL)
656 i2c_dw_read(dev);
657
658 if (stat & DW_IC_INTR_TX_EMPTY)
659 i2c_dw_xfer_msg(dev);
660
661 /*
662 * No need to modify or disable the interrupt mask here.
663 * i2c_dw_xfer_msg() will take care of it according to
664 * the current transmit status.
665 */
666
667 tx_aborted:
668 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
669 complete(&dev->cmd_complete);
670 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
671 /* Workaround to trigger pending interrupt */
672 regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
673 i2c_dw_disable_int(dev);
674 regmap_write(dev->map, DW_IC_INTR_MASK, stat);
675 }
676
677 return 0;
678 }
679
i2c_dw_isr(int this_irq, void *dev_id)680 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
681 {
682 struct dw_i2c_dev *dev = dev_id;
683 u32 stat, enabled;
684
685 regmap_read(dev->map, DW_IC_ENABLE, &enabled);
686 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
687 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
688 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
689 return IRQ_NONE;
690
691 i2c_dw_irq_handler_master(dev);
692
693 return IRQ_HANDLED;
694 }
695
i2c_dw_configure_master(struct dw_i2c_dev *dev)696 void i2c_dw_configure_master(struct dw_i2c_dev *dev)
697 {
698 struct i2c_timings *t = &dev->timings;
699
700 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
701
702 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
703 DW_IC_CON_RESTART_EN;
704
705 dev->mode = DW_IC_MASTER;
706
707 switch (t->bus_freq_hz) {
708 case I2C_MAX_STANDARD_MODE_FREQ:
709 dev->master_cfg |= DW_IC_CON_SPEED_STD;
710 break;
711 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
712 dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
713 break;
714 default:
715 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
716 }
717 }
718 EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
719
i2c_dw_prepare_recovery(struct i2c_adapter *adap)720 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
721 {
722 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
723
724 i2c_dw_disable(dev);
725 reset_control_assert(dev->rst);
726 i2c_dw_prepare_clk(dev, false);
727 }
728
i2c_dw_unprepare_recovery(struct i2c_adapter *adap)729 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
730 {
731 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
732
733 i2c_dw_prepare_clk(dev, true);
734 reset_control_deassert(dev->rst);
735 i2c_dw_init_master(dev);
736 }
737
i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)738 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
739 {
740 struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
741 struct i2c_adapter *adap = &dev->adapter;
742 struct gpio_desc *gpio;
743
744 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
745 if (IS_ERR_OR_NULL(gpio))
746 return PTR_ERR_OR_ZERO(gpio);
747
748 rinfo->scl_gpiod = gpio;
749
750 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
751 if (IS_ERR(gpio))
752 return PTR_ERR(gpio);
753 rinfo->sda_gpiod = gpio;
754
755 rinfo->recover_bus = i2c_generic_scl_recovery;
756 rinfo->prepare_recovery = i2c_dw_prepare_recovery;
757 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
758 adap->bus_recovery_info = rinfo;
759
760 dev_info(dev->dev, "running with gpio recovery mode! scl%s",
761 rinfo->sda_gpiod ? ",sda" : "");
762
763 return 0;
764 }
765
i2c_dw_probe_master(struct dw_i2c_dev *dev)766 int i2c_dw_probe_master(struct dw_i2c_dev *dev)
767 {
768 struct i2c_adapter *adap = &dev->adapter;
769 unsigned long irq_flags;
770 int ret;
771
772 init_completion(&dev->cmd_complete);
773
774 dev->init = i2c_dw_init_master;
775 dev->disable = i2c_dw_disable;
776 dev->disable_int = i2c_dw_disable_int;
777
778 ret = i2c_dw_init_regmap(dev);
779 if (ret)
780 return ret;
781
782 ret = i2c_dw_set_timings_master(dev);
783 if (ret)
784 return ret;
785
786 ret = i2c_dw_set_fifo_size(dev);
787 if (ret)
788 return ret;
789
790 ret = dev->init(dev);
791 if (ret)
792 return ret;
793
794 snprintf(adap->name, sizeof(adap->name),
795 "Synopsys DesignWare I2C adapter");
796 adap->retries = 3;
797 adap->algo = &i2c_dw_algo;
798 adap->quirks = &i2c_dw_quirks;
799 adap->dev.parent = dev->dev;
800 i2c_set_adapdata(adap, dev);
801
802 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
803 irq_flags = IRQF_NO_SUSPEND;
804 } else {
805 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
806 }
807
808 i2c_dw_disable_int(dev);
809 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
810 dev_name(dev->dev), dev);
811 if (ret) {
812 dev_err(dev->dev, "failure requesting irq %i: %d\n",
813 dev->irq, ret);
814 return ret;
815 }
816
817 ret = i2c_dw_init_recovery_info(dev);
818 if (ret)
819 return ret;
820
821 /*
822 * Increment PM usage count during adapter registration in order to
823 * avoid possible spurious runtime suspend when adapter device is
824 * registered to the device core and immediate resume in case bus has
825 * registered I2C slaves that do I2C transfers in their probe.
826 */
827 pm_runtime_get_noresume(dev->dev);
828 ret = i2c_add_numbered_adapter(adap);
829 if (ret)
830 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
831 pm_runtime_put_noidle(dev->dev);
832
833 return ret;
834 }
835 EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
836
837 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
838 MODULE_LICENSE("GPL");
839