1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/overflow.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19
20 #include <drm/drm.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_uapi.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_flip_work.h>
25 #include <drm/drm_fourcc.h>
26 #include <drm/drm_gem_framebuffer_helper.h>
27 #include <drm/drm_plane_helper.h>
28 #include <drm/drm_probe_helper.h>
29 #include <drm/drm_self_refresh_helper.h>
30 #include <drm/drm_vblank.h>
31
32 #ifdef CONFIG_DRM_ANALOGIX_DP
33 #include <drm/bridge/analogix_dp.h>
34 #endif
35
36 #include "rockchip_drm_drv.h"
37 #include "rockchip_drm_gem.h"
38 #include "rockchip_drm_fb.h"
39 #include "rockchip_drm_vop.h"
40 #include "rockchip_rgb.h"
41
42 #define VOP_WIN_SET(vop, win, name, v) \
43 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
44 #define VOP_SCL_SET(vop, win, name, v) \
45 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
46 #define VOP_SCL_SET_EXT(vop, win, name, v) \
47 vop_reg_set(vop, &win->phy->scl->ext->name, \
48 win->base, ~0, v, #name)
49
50 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
51 do { \
52 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
53 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
54 } while (0)
55
56 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
57 do { \
58 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
59 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
60 } while (0)
61
62 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
63 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
64
65 #define VOP_REG_SET(vop, group, name, v) \
66 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
67
68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
69 do { \
70 int i, reg = 0, mask = 0; \
71 for (i = 0; i < vop->data->intr->nintrs; i++) { \
72 if (vop->data->intr->intrs[i] & type) { \
73 reg |= (v) << i; \
74 mask |= 1 << i; \
75 } \
76 } \
77 VOP_INTR_SET_MASK(vop, name, mask, reg); \
78 } while (0)
79 #define VOP_INTR_GET_TYPE(vop, name, type) \
80 vop_get_intr_type(vop, &vop->data->intr->name, type)
81
82 #define VOP_WIN_GET(vop, win, name) \
83 vop_read_reg(vop, win->base, &win->phy->name)
84
85 #define VOP_WIN_HAS_REG(win, name) \
86 (!!(win->phy->name.mask))
87
88 #define VOP_WIN_GET_YRGBADDR(vop, win) \
89 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
90
91 #define VOP_WIN_TO_INDEX(vop_win) \
92 ((vop_win) - (vop_win)->vop->win)
93
94 #define VOP_AFBC_SET(vop, name, v) \
95 do { \
96 if ((vop)->data->afbc) \
97 vop_reg_set((vop), &(vop)->data->afbc->name, \
98 0, ~0, v, #name); \
99 } while (0)
100
101 #define to_vop(x) container_of(x, struct vop, crtc)
102 #define to_vop_win(x) container_of(x, struct vop_win, base)
103
104 #define AFBC_FMT_RGB565 0x0
105 #define AFBC_FMT_U8U8U8U8 0x5
106 #define AFBC_FMT_U8U8U8 0x4
107
108 #define AFBC_TILE_16x16 BIT(4)
109
110 /*
111 * The coefficients of the following matrix are all fixed points.
112 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
113 * They are all represented in two's complement.
114 */
115 static const uint32_t bt601_yuv2rgb[] = {
116 0x4A8, 0x0, 0x662,
117 0x4A8, 0x1E6F, 0x1CBF,
118 0x4A8, 0x812, 0x0,
119 0x321168, 0x0877CF, 0x2EB127
120 };
121
122 enum vop_pending {
123 VOP_PENDING_FB_UNREF,
124 };
125
126 struct vop_win {
127 struct drm_plane base;
128 const struct vop_win_data *data;
129 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
130 struct vop *vop;
131 };
132
133 struct rockchip_rgb;
134 struct vop {
135 struct drm_crtc crtc;
136 struct device *dev;
137 struct drm_device *drm_dev;
138 bool is_enabled;
139
140 struct completion dsp_hold_completion;
141 unsigned int win_enabled;
142
143 /* protected by dev->event_lock */
144 struct drm_pending_vblank_event *event;
145
146 struct drm_flip_work fb_unref_work;
147 unsigned long pending;
148
149 struct completion line_flag_completion;
150
151 const struct vop_data *data;
152
153 uint32_t *regsbak;
154 void __iomem *regs;
155 void __iomem *lut_regs;
156
157 /* physical map length of vop register */
158 uint32_t len;
159
160 /* one time only one process allowed to config the register */
161 spinlock_t reg_lock;
162 /* lock vop irq reg */
163 spinlock_t irq_lock;
164 /* protects crtc enable/disable */
165 struct mutex vop_lock;
166
167 unsigned int irq;
168
169 /* vop AHP clk */
170 struct clk *hclk;
171 /* vop dclk */
172 struct clk *dclk;
173 /* vop share memory frequency */
174 struct clk *aclk;
175
176 /* vop dclk reset */
177 struct reset_control *dclk_rst;
178
179 /* optional internal rgb encoder */
180 struct rockchip_rgb *rgb;
181
182 struct vop_win win[];
183 };
184
vop_writel(struct vop *vop, uint32_t offset, uint32_t v)185 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
186 {
187 writel(v, vop->regs + offset);
188 vop->regsbak[offset >> 2] = v;
189 }
190
vop_readl(struct vop *vop, uint32_t offset)191 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
192 {
193 return readl(vop->regs + offset);
194 }
195
vop_read_reg(struct vop *vop, uint32_t base, const struct vop_reg *reg)196 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
197 const struct vop_reg *reg)
198 {
199 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
200 }
201
vop_reg_set(struct vop *vop, const struct vop_reg *reg, uint32_t _offset, uint32_t _mask, uint32_t v, const char *reg_name)202 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
203 uint32_t _offset, uint32_t _mask, uint32_t v,
204 const char *reg_name)
205 {
206 int offset, mask, shift;
207
208 if (!reg || !reg->mask) {
209 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
210 return;
211 }
212
213 offset = reg->offset + _offset;
214 mask = reg->mask & _mask;
215 shift = reg->shift;
216
217 if (reg->write_mask) {
218 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
219 } else {
220 uint32_t cached_val = vop->regsbak[offset >> 2];
221
222 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
223 vop->regsbak[offset >> 2] = v;
224 }
225
226 if (reg->relaxed)
227 writel_relaxed(v, vop->regs + offset);
228 else
229 writel(v, vop->regs + offset);
230 }
231
vop_get_intr_type(struct vop *vop, const struct vop_reg *reg, int type)232 static inline uint32_t vop_get_intr_type(struct vop *vop,
233 const struct vop_reg *reg, int type)
234 {
235 uint32_t i, ret = 0;
236 uint32_t regs = vop_read_reg(vop, 0, reg);
237
238 for (i = 0; i < vop->data->intr->nintrs; i++) {
239 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
240 ret |= vop->data->intr->intrs[i];
241 }
242
243 return ret;
244 }
245
vop_cfg_done(struct vop *vop)246 static inline void vop_cfg_done(struct vop *vop)
247 {
248 VOP_REG_SET(vop, common, cfg_done, 1);
249 }
250
has_rb_swapped(uint32_t version, uint32_t format)251 static bool has_rb_swapped(uint32_t version, uint32_t format)
252 {
253 switch (format) {
254 case DRM_FORMAT_XBGR8888:
255 case DRM_FORMAT_ABGR8888:
256 case DRM_FORMAT_BGR565:
257 return true;
258 /*
259 * full framework (IP version 3.x) only need rb swapped for RGB888 and
260 * little framework (IP version 2.x) only need rb swapped for BGR888,
261 * check for 3.x to also only rb swap BGR888 for unknown vop version
262 */
263 case DRM_FORMAT_RGB888:
264 return VOP_MAJOR(version) == 3;
265 case DRM_FORMAT_BGR888:
266 return VOP_MAJOR(version) != 3;
267 default:
268 return false;
269 }
270 }
271
vop_convert_format(uint32_t format)272 static enum vop_data_format vop_convert_format(uint32_t format)
273 {
274 switch (format) {
275 case DRM_FORMAT_XRGB8888:
276 case DRM_FORMAT_ARGB8888:
277 case DRM_FORMAT_XBGR8888:
278 case DRM_FORMAT_ABGR8888:
279 return VOP_FMT_ARGB8888;
280 case DRM_FORMAT_RGB888:
281 case DRM_FORMAT_BGR888:
282 return VOP_FMT_RGB888;
283 case DRM_FORMAT_RGB565:
284 case DRM_FORMAT_BGR565:
285 return VOP_FMT_RGB565;
286 case DRM_FORMAT_NV12:
287 return VOP_FMT_YUV420SP;
288 case DRM_FORMAT_NV16:
289 return VOP_FMT_YUV422SP;
290 case DRM_FORMAT_NV24:
291 return VOP_FMT_YUV444SP;
292 default:
293 DRM_ERROR("unsupported format[%08x]\n", format);
294 return -EINVAL;
295 }
296 }
297
vop_convert_afbc_format(uint32_t format)298 static int vop_convert_afbc_format(uint32_t format)
299 {
300 switch (format) {
301 case DRM_FORMAT_XRGB8888:
302 case DRM_FORMAT_ARGB8888:
303 case DRM_FORMAT_XBGR8888:
304 case DRM_FORMAT_ABGR8888:
305 return AFBC_FMT_U8U8U8U8;
306 case DRM_FORMAT_RGB888:
307 case DRM_FORMAT_BGR888:
308 return AFBC_FMT_U8U8U8;
309 case DRM_FORMAT_RGB565:
310 case DRM_FORMAT_BGR565:
311 return AFBC_FMT_RGB565;
312 /* either of the below should not be reachable */
313 default:
314 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format);
315 return -EINVAL;
316 }
317
318 return -EINVAL;
319 }
320
scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t dst, bool is_horizontal, int vsu_mode, int *vskiplines)321 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
322 uint32_t dst, bool is_horizontal,
323 int vsu_mode, int *vskiplines)
324 {
325 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
326
327 if (vskiplines)
328 *vskiplines = 0;
329
330 if (is_horizontal) {
331 if (mode == SCALE_UP)
332 val = GET_SCL_FT_BIC(src, dst);
333 else if (mode == SCALE_DOWN)
334 val = GET_SCL_FT_BILI_DN(src, dst);
335 } else {
336 if (mode == SCALE_UP) {
337 if (vsu_mode == SCALE_UP_BIL)
338 val = GET_SCL_FT_BILI_UP(src, dst);
339 else
340 val = GET_SCL_FT_BIC(src, dst);
341 } else if (mode == SCALE_DOWN) {
342 if (vskiplines) {
343 *vskiplines = scl_get_vskiplines(src, dst);
344 val = scl_get_bili_dn_vskip(src, dst,
345 *vskiplines);
346 } else {
347 val = GET_SCL_FT_BILI_DN(src, dst);
348 }
349 }
350 }
351
352 return val;
353 }
354
scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, const struct drm_format_info *info)355 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
356 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
357 uint32_t dst_h, const struct drm_format_info *info)
358 {
359 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
360 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
361 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
362 bool is_yuv = false;
363 uint16_t cbcr_src_w = src_w / info->hsub;
364 uint16_t cbcr_src_h = src_h / info->vsub;
365 uint16_t vsu_mode;
366 uint16_t lb_mode;
367 uint32_t val;
368 int vskiplines;
369
370 if (info->is_yuv)
371 is_yuv = true;
372
373 if (dst_w > 3840) {
374 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
375 return;
376 }
377
378 if (!win->phy->scl->ext) {
379 VOP_SCL_SET(vop, win, scale_yrgb_x,
380 scl_cal_scale2(src_w, dst_w));
381 VOP_SCL_SET(vop, win, scale_yrgb_y,
382 scl_cal_scale2(src_h, dst_h));
383 if (is_yuv) {
384 VOP_SCL_SET(vop, win, scale_cbcr_x,
385 scl_cal_scale2(cbcr_src_w, dst_w));
386 VOP_SCL_SET(vop, win, scale_cbcr_y,
387 scl_cal_scale2(cbcr_src_h, dst_h));
388 }
389 return;
390 }
391
392 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
393 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
394
395 if (is_yuv) {
396 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
397 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
398 if (cbcr_hor_scl_mode == SCALE_DOWN)
399 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
400 else
401 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
402 } else {
403 if (yrgb_hor_scl_mode == SCALE_DOWN)
404 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
405 else
406 lb_mode = scl_vop_cal_lb_mode(src_w, false);
407 }
408
409 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
410 if (lb_mode == LB_RGB_3840X2) {
411 if (yrgb_ver_scl_mode != SCALE_NONE) {
412 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
413 return;
414 }
415 if (cbcr_ver_scl_mode != SCALE_NONE) {
416 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
417 return;
418 }
419 vsu_mode = SCALE_UP_BIL;
420 } else if (lb_mode == LB_RGB_2560X4) {
421 vsu_mode = SCALE_UP_BIL;
422 } else {
423 vsu_mode = SCALE_UP_BIC;
424 }
425
426 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
427 true, 0, NULL);
428 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
429 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
430 false, vsu_mode, &vskiplines);
431 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
432
433 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
434 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
435
436 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
437 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
438 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
439 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
440 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
441 if (is_yuv) {
442 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
443 dst_w, true, 0, NULL);
444 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
445 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
446 dst_h, false, vsu_mode, &vskiplines);
447 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
448
449 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
450 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
451 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
452 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
453 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
454 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
455 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
456 }
457 }
458
vop_dsp_hold_valid_irq_enable(struct vop *vop)459 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
460 {
461 unsigned long flags;
462
463 if (WARN_ON(!vop->is_enabled))
464 return;
465
466 spin_lock_irqsave(&vop->irq_lock, flags);
467
468 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
469 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
470
471 spin_unlock_irqrestore(&vop->irq_lock, flags);
472 }
473
vop_dsp_hold_valid_irq_disable(struct vop *vop)474 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
475 {
476 unsigned long flags;
477
478 if (WARN_ON(!vop->is_enabled))
479 return;
480
481 spin_lock_irqsave(&vop->irq_lock, flags);
482
483 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
484
485 spin_unlock_irqrestore(&vop->irq_lock, flags);
486 }
487
488 /*
489 * (1) each frame starts at the start of the Vsync pulse which is signaled by
490 * the "FRAME_SYNC" interrupt.
491 * (2) the active data region of each frame ends at dsp_vact_end
492 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
493 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
494 *
495 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
496 * Interrupts
497 * LINE_FLAG -------------------------------+
498 * FRAME_SYNC ----+ |
499 * | |
500 * v v
501 * | Vsync | Vbp | Vactive | Vfp |
502 * ^ ^ ^ ^
503 * | | | |
504 * | | | |
505 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
506 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
507 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
508 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
509 */
vop_line_flag_irq_is_enabled(struct vop *vop)510 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
511 {
512 uint32_t line_flag_irq;
513 unsigned long flags;
514
515 spin_lock_irqsave(&vop->irq_lock, flags);
516
517 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
518
519 spin_unlock_irqrestore(&vop->irq_lock, flags);
520
521 return !!line_flag_irq;
522 }
523
vop_line_flag_irq_enable(struct vop *vop)524 static void vop_line_flag_irq_enable(struct vop *vop)
525 {
526 unsigned long flags;
527
528 if (WARN_ON(!vop->is_enabled))
529 return;
530
531 spin_lock_irqsave(&vop->irq_lock, flags);
532
533 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
534 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
535
536 spin_unlock_irqrestore(&vop->irq_lock, flags);
537 }
538
vop_line_flag_irq_disable(struct vop *vop)539 static void vop_line_flag_irq_disable(struct vop *vop)
540 {
541 unsigned long flags;
542
543 if (WARN_ON(!vop->is_enabled))
544 return;
545
546 spin_lock_irqsave(&vop->irq_lock, flags);
547
548 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
549
550 spin_unlock_irqrestore(&vop->irq_lock, flags);
551 }
552
vop_core_clks_enable(struct vop *vop)553 static int vop_core_clks_enable(struct vop *vop)
554 {
555 int ret;
556
557 ret = clk_enable(vop->hclk);
558 if (ret < 0)
559 return ret;
560
561 ret = clk_enable(vop->aclk);
562 if (ret < 0)
563 goto err_disable_hclk;
564
565 return 0;
566
567 err_disable_hclk:
568 clk_disable(vop->hclk);
569 return ret;
570 }
571
vop_core_clks_disable(struct vop *vop)572 static void vop_core_clks_disable(struct vop *vop)
573 {
574 clk_disable(vop->aclk);
575 clk_disable(vop->hclk);
576 }
577
vop_win_disable(struct vop *vop, const struct vop_win *vop_win)578 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
579 {
580 const struct vop_win_data *win = vop_win->data;
581
582 if (win->phy->scl && win->phy->scl->ext) {
583 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
584 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
585 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
586 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
587 }
588
589 VOP_WIN_SET(vop, win, enable, 0);
590 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
591 }
592
vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)593 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
594 {
595 struct vop *vop = to_vop(crtc);
596 int ret, i;
597
598 ret = pm_runtime_get_sync(vop->dev);
599 if (ret < 0) {
600 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
601 return ret;
602 }
603
604 ret = vop_core_clks_enable(vop);
605 if (WARN_ON(ret < 0))
606 goto err_put_pm_runtime;
607
608 ret = clk_enable(vop->dclk);
609 if (WARN_ON(ret < 0))
610 goto err_disable_core;
611
612 /*
613 * Slave iommu shares power, irq and clock with vop. It was associated
614 * automatically with this master device via common driver code.
615 * Now that we have enabled the clock we attach it to the shared drm
616 * mapping.
617 */
618 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
619 if (ret) {
620 DRM_DEV_ERROR(vop->dev,
621 "failed to attach dma mapping, %d\n", ret);
622 goto err_disable_dclk;
623 }
624
625 spin_lock(&vop->reg_lock);
626 for (i = 0; i < vop->len; i += 4)
627 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
628
629 /*
630 * We need to make sure that all windows are disabled before we
631 * enable the crtc. Otherwise we might try to scan from a destroyed
632 * buffer later.
633 *
634 * In the case of enable-after-PSR, we don't need to worry about this
635 * case since the buffer is guaranteed to be valid and disabling the
636 * window will result in screen glitches on PSR exit.
637 */
638 if (!old_state || !old_state->self_refresh_active) {
639 for (i = 0; i < vop->data->win_size; i++) {
640 struct vop_win *vop_win = &vop->win[i];
641
642 vop_win_disable(vop, vop_win);
643 }
644 }
645
646 if (vop->data->afbc) {
647 struct rockchip_crtc_state *s;
648 /*
649 * Disable AFBC and forget there was a vop window with AFBC
650 */
651 VOP_AFBC_SET(vop, enable, 0);
652 s = to_rockchip_crtc_state(crtc->state);
653 s->enable_afbc = false;
654 }
655
656 vop_cfg_done(vop);
657
658 spin_unlock(&vop->reg_lock);
659
660 /*
661 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
662 */
663 vop->is_enabled = true;
664
665 spin_lock(&vop->reg_lock);
666
667 VOP_REG_SET(vop, common, standby, 1);
668
669 spin_unlock(&vop->reg_lock);
670
671 drm_crtc_vblank_on(crtc);
672
673 return 0;
674
675 err_disable_dclk:
676 clk_disable(vop->dclk);
677 err_disable_core:
678 vop_core_clks_disable(vop);
679 err_put_pm_runtime:
680 pm_runtime_put_sync(vop->dev);
681 return ret;
682 }
683
rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)684 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
685 {
686 struct vop *vop = to_vop(crtc);
687 int i;
688
689 spin_lock(&vop->reg_lock);
690
691 for (i = 0; i < vop->data->win_size; i++) {
692 struct vop_win *vop_win = &vop->win[i];
693 const struct vop_win_data *win = vop_win->data;
694
695 VOP_WIN_SET(vop, win, enable,
696 enabled && (vop->win_enabled & BIT(i)));
697 }
698 vop_cfg_done(vop);
699
700 spin_unlock(&vop->reg_lock);
701 }
702
vop_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)703 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
704 struct drm_crtc_state *old_state)
705 {
706 struct vop *vop = to_vop(crtc);
707
708 WARN_ON(vop->event);
709
710 if (crtc->state->self_refresh_active)
711 rockchip_drm_set_win_enabled(crtc, false);
712
713 if (crtc->state->self_refresh_active)
714 goto out;
715
716 mutex_lock(&vop->vop_lock);
717
718 drm_crtc_vblank_off(crtc);
719
720 /*
721 * Vop standby will take effect at end of current frame,
722 * if dsp hold valid irq happen, it means standby complete.
723 *
724 * we must wait standby complete when we want to disable aclk,
725 * if not, memory bus maybe dead.
726 */
727 reinit_completion(&vop->dsp_hold_completion);
728 vop_dsp_hold_valid_irq_enable(vop);
729
730 spin_lock(&vop->reg_lock);
731
732 VOP_REG_SET(vop, common, standby, 1);
733
734 spin_unlock(&vop->reg_lock);
735
736 wait_for_completion(&vop->dsp_hold_completion);
737
738 vop_dsp_hold_valid_irq_disable(vop);
739
740 vop->is_enabled = false;
741
742 /*
743 * vop standby complete, so iommu detach is safe.
744 */
745 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
746
747 clk_disable(vop->dclk);
748 vop_core_clks_disable(vop);
749 pm_runtime_put(vop->dev);
750
751 mutex_unlock(&vop->vop_lock);
752
753 out:
754 if (crtc->state->event && !crtc->state->active) {
755 spin_lock_irq(&crtc->dev->event_lock);
756 drm_crtc_send_vblank_event(crtc, crtc->state->event);
757 spin_unlock_irq(&crtc->dev->event_lock);
758
759 crtc->state->event = NULL;
760 }
761 }
762
vop_plane_destroy(struct drm_plane *plane)763 static void vop_plane_destroy(struct drm_plane *plane)
764 {
765 drm_plane_cleanup(plane);
766 }
767
rockchip_afbc(u64 modifier)768 static inline bool rockchip_afbc(u64 modifier)
769 {
770 return modifier == ROCKCHIP_AFBC_MOD;
771 }
772
rockchip_mod_supported(struct drm_plane *plane, u32 format, u64 modifier)773 static bool rockchip_mod_supported(struct drm_plane *plane,
774 u32 format, u64 modifier)
775 {
776 if (modifier == DRM_FORMAT_MOD_LINEAR)
777 return true;
778
779 if (!rockchip_afbc(modifier)) {
780 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
781
782 return false;
783 }
784
785 return vop_convert_afbc_format(format) >= 0;
786 }
787
vop_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)788 static int vop_plane_atomic_check(struct drm_plane *plane,
789 struct drm_plane_state *state)
790 {
791 struct drm_crtc *crtc = state->crtc;
792 struct drm_crtc_state *crtc_state;
793 struct drm_framebuffer *fb = state->fb;
794 struct vop_win *vop_win = to_vop_win(plane);
795 const struct vop_win_data *win = vop_win->data;
796 int ret;
797 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
798 DRM_PLANE_HELPER_NO_SCALING;
799 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
800 DRM_PLANE_HELPER_NO_SCALING;
801
802 if (!crtc || WARN_ON(!fb))
803 return 0;
804
805 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
806 if (WARN_ON(!crtc_state))
807 return -EINVAL;
808
809 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
810 min_scale, max_scale,
811 true, true);
812 if (ret)
813 return ret;
814
815 if (!state->visible)
816 return 0;
817
818 ret = vop_convert_format(fb->format->format);
819 if (ret < 0)
820 return ret;
821
822 /*
823 * Src.x1 can be odd when do clip, but yuv plane start point
824 * need align with 2 pixel.
825 */
826 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
827 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
828 return -EINVAL;
829 }
830
831 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
832 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
833 return -EINVAL;
834 }
835
836 if (rockchip_afbc(fb->modifier)) {
837 struct vop *vop = to_vop(crtc);
838
839 if (!vop->data->afbc) {
840 DRM_ERROR("vop does not support AFBC\n");
841 return -EINVAL;
842 }
843
844 ret = vop_convert_afbc_format(fb->format->format);
845 if (ret < 0)
846 return ret;
847
848 if (state->src.x1 || state->src.y1) {
849 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", state->src.x1, state->src.y1, fb->offsets[0]);
850 return -EINVAL;
851 }
852
853 if (state->rotation && state->rotation != DRM_MODE_ROTATE_0) {
854 DRM_ERROR("No rotation support in AFBC, rotation=%d\n",
855 state->rotation);
856 return -EINVAL;
857 }
858 }
859
860 return 0;
861 }
862
vop_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state)863 static void vop_plane_atomic_disable(struct drm_plane *plane,
864 struct drm_plane_state *old_state)
865 {
866 struct vop_win *vop_win = to_vop_win(plane);
867 struct vop *vop = to_vop(old_state->crtc);
868
869 if (!old_state->crtc)
870 return;
871
872 spin_lock(&vop->reg_lock);
873
874 vop_win_disable(vop, vop_win);
875
876 spin_unlock(&vop->reg_lock);
877 }
878
vop_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state)879 static void vop_plane_atomic_update(struct drm_plane *plane,
880 struct drm_plane_state *old_state)
881 {
882 struct drm_plane_state *state = plane->state;
883 struct drm_crtc *crtc = state->crtc;
884 struct vop_win *vop_win = to_vop_win(plane);
885 const struct vop_win_data *win = vop_win->data;
886 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
887 struct vop *vop = to_vop(state->crtc);
888 struct drm_framebuffer *fb = state->fb;
889 unsigned int actual_w, actual_h;
890 unsigned int dsp_stx, dsp_sty;
891 uint32_t act_info, dsp_info, dsp_st;
892 struct drm_rect *src = &state->src;
893 struct drm_rect *dest = &state->dst;
894 struct drm_gem_object *obj, *uv_obj;
895 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
896 unsigned long offset;
897 dma_addr_t dma_addr;
898 uint32_t val;
899 bool rb_swap;
900 int win_index = VOP_WIN_TO_INDEX(vop_win);
901 int format;
902 int is_yuv = fb->format->is_yuv;
903 int i;
904
905 /*
906 * can't update plane when vop is disabled.
907 */
908 if (WARN_ON(!crtc))
909 return;
910
911 if (WARN_ON(!vop->is_enabled))
912 return;
913
914 if (!state->visible) {
915 vop_plane_atomic_disable(plane, old_state);
916 return;
917 }
918
919 obj = fb->obj[0];
920 rk_obj = to_rockchip_obj(obj);
921
922 actual_w = drm_rect_width(src) >> 16;
923 actual_h = drm_rect_height(src) >> 16;
924 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
925
926 dsp_info = (drm_rect_height(dest) - 1) << 16;
927 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
928
929 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
930 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
931 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
932
933 offset = (src->x1 >> 16) * fb->format->cpp[0];
934 offset += (src->y1 >> 16) * fb->pitches[0];
935 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
936
937 /*
938 * For y-mirroring we need to move address
939 * to the beginning of the last line.
940 */
941 if (state->rotation & DRM_MODE_REFLECT_Y)
942 dma_addr += (actual_h - 1) * fb->pitches[0];
943
944 format = vop_convert_format(fb->format->format);
945
946 spin_lock(&vop->reg_lock);
947
948 if (rockchip_afbc(fb->modifier)) {
949 int afbc_format = vop_convert_afbc_format(fb->format->format);
950
951 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
952 VOP_AFBC_SET(vop, hreg_block_split, 0);
953 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
954 VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
955 VOP_AFBC_SET(vop, pic_size, act_info);
956 }
957
958 VOP_WIN_SET(vop, win, format, format);
959 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
960 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
961 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
962 VOP_WIN_SET(vop, win, y_mir_en,
963 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
964 VOP_WIN_SET(vop, win, x_mir_en,
965 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
966
967 if (is_yuv) {
968 int hsub = fb->format->hsub;
969 int vsub = fb->format->vsub;
970 int bpp = fb->format->cpp[1];
971
972 uv_obj = fb->obj[1];
973 rk_uv_obj = to_rockchip_obj(uv_obj);
974
975 offset = (src->x1 >> 16) * bpp / hsub;
976 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
977
978 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
979 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
980 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
981
982 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
983 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
984 win_yuv2yuv,
985 y2r_coefficients[i],
986 bt601_yuv2rgb[i]);
987 }
988 }
989
990 if (win->phy->scl)
991 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
992 drm_rect_width(dest), drm_rect_height(dest),
993 fb->format);
994
995 VOP_WIN_SET(vop, win, act_info, act_info);
996 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
997 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
998
999 rb_swap = has_rb_swapped(vop->data->version, fb->format->format);
1000 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1001
1002 /*
1003 * Blending win0 with the background color doesn't seem to work
1004 * correctly. We only get the background color, no matter the contents
1005 * of the win0 framebuffer. However, blending pre-multiplied color
1006 * with the default opaque black default background color is a no-op,
1007 * so we can just disable blending to get the correct result.
1008 */
1009 if (fb->format->has_alpha && win_index > 0) {
1010 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1011 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1012 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1013 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1014 SRC_BLEND_M0(ALPHA_PER_PIX) |
1015 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1016 SRC_FACTOR_M0(ALPHA_ONE);
1017 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1018
1019 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1020 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1021 VOP_WIN_SET(vop, win, alpha_en, 1);
1022 } else {
1023 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1024 VOP_WIN_SET(vop, win, alpha_en, 0);
1025 }
1026
1027 VOP_WIN_SET(vop, win, enable, 1);
1028 vop->win_enabled |= BIT(win_index);
1029 spin_unlock(&vop->reg_lock);
1030 }
1031
vop_plane_atomic_async_check(struct drm_plane *plane, struct drm_plane_state *state)1032 static int vop_plane_atomic_async_check(struct drm_plane *plane,
1033 struct drm_plane_state *state)
1034 {
1035 struct vop_win *vop_win = to_vop_win(plane);
1036 const struct vop_win_data *win = vop_win->data;
1037 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1038 DRM_PLANE_HELPER_NO_SCALING;
1039 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1040 DRM_PLANE_HELPER_NO_SCALING;
1041 struct drm_crtc_state *crtc_state;
1042
1043 if (plane != state->crtc->cursor)
1044 return -EINVAL;
1045
1046 if (!plane->state)
1047 return -EINVAL;
1048
1049 if (!plane->state->fb)
1050 return -EINVAL;
1051
1052 if (state->state)
1053 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
1054 state->crtc);
1055 else /* Special case for asynchronous cursor updates. */
1056 crtc_state = plane->crtc->state;
1057
1058 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
1059 min_scale, max_scale,
1060 true, true);
1061 }
1062
vop_plane_atomic_async_update(struct drm_plane *plane, struct drm_plane_state *new_state)1063 static void vop_plane_atomic_async_update(struct drm_plane *plane,
1064 struct drm_plane_state *new_state)
1065 {
1066 struct vop *vop = to_vop(plane->state->crtc);
1067 struct drm_framebuffer *old_fb = plane->state->fb;
1068
1069 plane->state->crtc_x = new_state->crtc_x;
1070 plane->state->crtc_y = new_state->crtc_y;
1071 plane->state->crtc_h = new_state->crtc_h;
1072 plane->state->crtc_w = new_state->crtc_w;
1073 plane->state->src_x = new_state->src_x;
1074 plane->state->src_y = new_state->src_y;
1075 plane->state->src_h = new_state->src_h;
1076 plane->state->src_w = new_state->src_w;
1077 swap(plane->state->fb, new_state->fb);
1078
1079 if (vop->is_enabled) {
1080 vop_plane_atomic_update(plane, plane->state);
1081 spin_lock(&vop->reg_lock);
1082 vop_cfg_done(vop);
1083 spin_unlock(&vop->reg_lock);
1084
1085 /*
1086 * A scanout can still be occurring, so we can't drop the
1087 * reference to the old framebuffer. To solve this we get a
1088 * reference to old_fb and set a worker to release it later.
1089 * FIXME: if we perform 500 async_update calls before the
1090 * vblank, then we can have 500 different framebuffers waiting
1091 * to be released.
1092 */
1093 if (old_fb && plane->state->fb != old_fb) {
1094 drm_framebuffer_get(old_fb);
1095 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1096 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1097 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1098 }
1099 }
1100 }
1101
1102 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1103 .atomic_check = vop_plane_atomic_check,
1104 .atomic_update = vop_plane_atomic_update,
1105 .atomic_disable = vop_plane_atomic_disable,
1106 .atomic_async_check = vop_plane_atomic_async_check,
1107 .atomic_async_update = vop_plane_atomic_async_update,
1108 .prepare_fb = drm_gem_fb_prepare_fb,
1109 };
1110
1111 static const struct drm_plane_funcs vop_plane_funcs = {
1112 .update_plane = drm_atomic_helper_update_plane,
1113 .disable_plane = drm_atomic_helper_disable_plane,
1114 .destroy = vop_plane_destroy,
1115 .reset = drm_atomic_helper_plane_reset,
1116 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1117 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1118 .format_mod_supported = rockchip_mod_supported,
1119 };
1120
vop_crtc_enable_vblank(struct drm_crtc *crtc)1121 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1122 {
1123 struct vop *vop = to_vop(crtc);
1124 unsigned long flags;
1125
1126 if (WARN_ON(!vop->is_enabled))
1127 return -EPERM;
1128
1129 spin_lock_irqsave(&vop->irq_lock, flags);
1130
1131 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1132 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1133
1134 spin_unlock_irqrestore(&vop->irq_lock, flags);
1135
1136 return 0;
1137 }
1138
vop_crtc_disable_vblank(struct drm_crtc *crtc)1139 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1140 {
1141 struct vop *vop = to_vop(crtc);
1142 unsigned long flags;
1143
1144 if (WARN_ON(!vop->is_enabled))
1145 return;
1146
1147 spin_lock_irqsave(&vop->irq_lock, flags);
1148
1149 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1150
1151 spin_unlock_irqrestore(&vop->irq_lock, flags);
1152 }
1153
vop_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)1154 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1155 const struct drm_display_mode *mode,
1156 struct drm_display_mode *adjusted_mode)
1157 {
1158 struct vop *vop = to_vop(crtc);
1159 unsigned long rate;
1160
1161 /*
1162 * Clock craziness.
1163 *
1164 * Key points:
1165 *
1166 * - DRM works in in kHz.
1167 * - Clock framework works in Hz.
1168 * - Rockchip's clock driver picks the clock rate that is the
1169 * same _OR LOWER_ than the one requested.
1170 *
1171 * Action plan:
1172 *
1173 * 1. When DRM gives us a mode, we should add 999 Hz to it. That way
1174 * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to
1175 * make 60000 kHz then the clock framework will actually give us
1176 * the right clock.
1177 *
1178 * NOTE: if the PLL (maybe through a divider) could actually make
1179 * a clock rate 999 Hz higher instead of the one we want then this
1180 * could be a problem. Unfortunately there's not much we can do
1181 * since it's baked into DRM to use kHz. It shouldn't matter in
1182 * practice since Rockchip PLLs are controlled by tables and
1183 * even if there is a divider in the middle I wouldn't expect PLL
1184 * rates in the table that are just a few kHz different.
1185 *
1186 * 2. Get the clock framework to round the rate for us to tell us
1187 * what it will actually make.
1188 *
1189 * 3. Store the rounded up rate so that we don't need to worry about
1190 * this in the actual clk_set_rate().
1191 */
1192 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999);
1193 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
1194
1195 return true;
1196 }
1197
vop_dsp_lut_is_enabled(struct vop *vop)1198 static bool vop_dsp_lut_is_enabled(struct vop *vop)
1199 {
1200 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1201 }
1202
vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)1203 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1204 {
1205 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1206 unsigned int i;
1207
1208 for (i = 0; i < crtc->gamma_size; i++) {
1209 u32 word;
1210
1211 word = (drm_color_lut_extract(lut[i].red, 10) << 20) |
1212 (drm_color_lut_extract(lut[i].green, 10) << 10) |
1213 drm_color_lut_extract(lut[i].blue, 10);
1214 writel(word, vop->lut_regs + i * 4);
1215 }
1216 }
1217
vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, struct drm_crtc_state *old_state)1218 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1219 struct drm_crtc_state *old_state)
1220 {
1221 struct drm_crtc_state *state = crtc->state;
1222 unsigned int idle;
1223 int ret;
1224
1225 if (!vop->lut_regs)
1226 return;
1227 /*
1228 * To disable gamma (gamma_lut is null) or to write
1229 * an update to the LUT, clear dsp_lut_en.
1230 */
1231 spin_lock(&vop->reg_lock);
1232 VOP_REG_SET(vop, common, dsp_lut_en, 0);
1233 vop_cfg_done(vop);
1234 spin_unlock(&vop->reg_lock);
1235
1236 /*
1237 * In order to write the LUT to the internal memory,
1238 * we need to first make sure the dsp_lut_en bit is cleared.
1239 */
1240 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1241 idle, !idle, 5, 30 * 1000);
1242 if (ret) {
1243 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1244 return;
1245 }
1246
1247 if (!state->gamma_lut)
1248 return;
1249
1250 spin_lock(&vop->reg_lock);
1251 vop_crtc_write_gamma_lut(vop, crtc);
1252 VOP_REG_SET(vop, common, dsp_lut_en, 1);
1253 vop_cfg_done(vop);
1254 spin_unlock(&vop->reg_lock);
1255 }
1256
vop_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state)1257 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1258 struct drm_crtc_state *old_crtc_state)
1259 {
1260 struct vop *vop = to_vop(crtc);
1261
1262 /*
1263 * Only update GAMMA if the 'active' flag is not changed,
1264 * otherwise it's updated by .atomic_enable.
1265 */
1266 if (crtc->state->color_mgmt_changed &&
1267 !crtc->state->active_changed)
1268 vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1269 }
1270
vop_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)1271 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1272 struct drm_crtc_state *old_state)
1273 {
1274 struct vop *vop = to_vop(crtc);
1275 const struct vop_data *vop_data = vop->data;
1276 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1277 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1278 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1279 u16 hdisplay = adjusted_mode->hdisplay;
1280 u16 htotal = adjusted_mode->htotal;
1281 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1282 u16 hact_end = hact_st + hdisplay;
1283 u16 vdisplay = adjusted_mode->vdisplay;
1284 u16 vtotal = adjusted_mode->vtotal;
1285 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1286 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1287 u16 vact_end = vact_st + vdisplay;
1288 uint32_t pin_pol, val;
1289 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1290 int ret;
1291
1292 if (old_state && old_state->self_refresh_active) {
1293 drm_crtc_vblank_on(crtc);
1294 rockchip_drm_set_win_enabled(crtc, true);
1295 return;
1296 }
1297
1298 /*
1299 * If we have a GAMMA LUT in the state, then let's make sure
1300 * it's updated. We might be coming out of suspend,
1301 * which means the LUT internal memory needs to be re-written.
1302 */
1303 if (crtc->state->gamma_lut)
1304 vop_crtc_gamma_set(vop, crtc, old_state);
1305
1306 mutex_lock(&vop->vop_lock);
1307
1308 WARN_ON(vop->event);
1309
1310 ret = vop_enable(crtc, old_state);
1311 if (ret) {
1312 mutex_unlock(&vop->vop_lock);
1313 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1314 return;
1315 }
1316 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1317 BIT(HSYNC_POSITIVE) : 0;
1318 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1319 BIT(VSYNC_POSITIVE) : 0;
1320 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1321 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1322
1323 switch (s->output_type) {
1324 case DRM_MODE_CONNECTOR_LVDS:
1325 VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1326 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1327 VOP_REG_SET(vop, output, rgb_en, 1);
1328 break;
1329 case DRM_MODE_CONNECTOR_eDP:
1330 VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1331 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1332 VOP_REG_SET(vop, output, edp_en, 1);
1333 break;
1334 case DRM_MODE_CONNECTOR_HDMIA:
1335 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1336 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1337 VOP_REG_SET(vop, output, hdmi_en, 1);
1338 break;
1339 case DRM_MODE_CONNECTOR_DSI:
1340 VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1341 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1342 VOP_REG_SET(vop, output, mipi_en, 1);
1343 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1344 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1345 break;
1346 case DRM_MODE_CONNECTOR_DisplayPort:
1347 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1348 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1349 VOP_REG_SET(vop, output, dp_en, 1);
1350 break;
1351 default:
1352 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1353 s->output_type);
1354 }
1355
1356 /*
1357 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1358 */
1359 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1360 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1361 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1362
1363 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1364 VOP_REG_SET(vop, common, pre_dither_down, 1);
1365 else
1366 VOP_REG_SET(vop, common, pre_dither_down, 0);
1367
1368 if (dither_bpc == 6) {
1369 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1370 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1371 VOP_REG_SET(vop, common, dither_down_en, 1);
1372 } else {
1373 VOP_REG_SET(vop, common, dither_down_en, 0);
1374 }
1375
1376 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1377
1378 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1379 val = hact_st << 16;
1380 val |= hact_end;
1381 VOP_REG_SET(vop, modeset, hact_st_end, val);
1382 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1383
1384 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1385 val = vact_st << 16;
1386 val |= vact_end;
1387 VOP_REG_SET(vop, modeset, vact_st_end, val);
1388 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1389
1390 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1391
1392 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1393
1394 VOP_REG_SET(vop, common, standby, 0);
1395 mutex_unlock(&vop->vop_lock);
1396 }
1397
vop_fs_irq_is_pending(struct vop *vop)1398 static bool vop_fs_irq_is_pending(struct vop *vop)
1399 {
1400 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1401 }
1402
vop_wait_for_irq_handler(struct vop *vop)1403 static void vop_wait_for_irq_handler(struct vop *vop)
1404 {
1405 bool pending;
1406 int ret;
1407
1408 /*
1409 * Spin until frame start interrupt status bit goes low, which means
1410 * that interrupt handler was invoked and cleared it. The timeout of
1411 * 10 msecs is really too long, but it is just a safety measure if
1412 * something goes really wrong. The wait will only happen in the very
1413 * unlikely case of a vblank happening exactly at the same time and
1414 * shouldn't exceed microseconds range.
1415 */
1416 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1417 !pending, 0, 10 * 1000);
1418 if (ret)
1419 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1420
1421 synchronize_irq(vop->irq);
1422 }
1423
vop_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)1424 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1425 struct drm_crtc_state *crtc_state)
1426 {
1427 struct vop *vop = to_vop(crtc);
1428 struct drm_plane *plane;
1429 struct drm_plane_state *plane_state;
1430 struct rockchip_crtc_state *s;
1431 int afbc_planes = 0;
1432
1433 if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1434 crtc_state->gamma_lut) {
1435 unsigned int len;
1436
1437 len = drm_color_lut_size(crtc_state->gamma_lut);
1438 if (len != crtc->gamma_size) {
1439 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1440 len, crtc->gamma_size);
1441 return -EINVAL;
1442 }
1443 }
1444
1445 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1446 plane_state =
1447 drm_atomic_get_plane_state(crtc_state->state, plane);
1448 if (IS_ERR(plane_state)) {
1449 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n",
1450 plane->name);
1451 return PTR_ERR(plane_state);
1452 }
1453
1454 if (drm_is_afbc(plane_state->fb->modifier))
1455 ++afbc_planes;
1456 }
1457
1458 if (afbc_planes > 1) {
1459 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes);
1460 return -EINVAL;
1461 }
1462
1463 s = to_rockchip_crtc_state(crtc_state);
1464 s->enable_afbc = afbc_planes > 0;
1465
1466 return 0;
1467 }
1468
vop_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state)1469 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1470 struct drm_crtc_state *old_crtc_state)
1471 {
1472 struct drm_atomic_state *old_state = old_crtc_state->state;
1473 struct drm_plane_state *old_plane_state, *new_plane_state;
1474 struct vop *vop = to_vop(crtc);
1475 struct drm_plane *plane;
1476 struct rockchip_crtc_state *s;
1477 int i;
1478
1479 if (WARN_ON(!vop->is_enabled))
1480 return;
1481
1482 spin_lock(&vop->reg_lock);
1483
1484 /* Enable AFBC if there is some AFBC window, disable otherwise. */
1485 s = to_rockchip_crtc_state(crtc->state);
1486 VOP_AFBC_SET(vop, enable, s->enable_afbc);
1487 vop_cfg_done(vop);
1488
1489 spin_unlock(&vop->reg_lock);
1490
1491 /*
1492 * There is a (rather unlikely) possiblity that a vblank interrupt
1493 * fired before we set the cfg_done bit. To avoid spuriously
1494 * signalling flip completion we need to wait for it to finish.
1495 */
1496 vop_wait_for_irq_handler(vop);
1497
1498 spin_lock_irq(&crtc->dev->event_lock);
1499 if (crtc->state->event) {
1500 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1501 WARN_ON(vop->event);
1502
1503 vop->event = crtc->state->event;
1504 crtc->state->event = NULL;
1505 }
1506 spin_unlock_irq(&crtc->dev->event_lock);
1507
1508 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1509 new_plane_state, i) {
1510 if (!old_plane_state->fb)
1511 continue;
1512
1513 if (old_plane_state->fb == new_plane_state->fb)
1514 continue;
1515
1516 drm_framebuffer_get(old_plane_state->fb);
1517 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1518 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1519 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1520 }
1521 }
1522
1523 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1524 .mode_fixup = vop_crtc_mode_fixup,
1525 .atomic_check = vop_crtc_atomic_check,
1526 .atomic_begin = vop_crtc_atomic_begin,
1527 .atomic_flush = vop_crtc_atomic_flush,
1528 .atomic_enable = vop_crtc_atomic_enable,
1529 .atomic_disable = vop_crtc_atomic_disable,
1530 };
1531
vop_crtc_destroy(struct drm_crtc *crtc)1532 static void vop_crtc_destroy(struct drm_crtc *crtc)
1533 {
1534 drm_crtc_cleanup(crtc);
1535 }
1536
vop_crtc_duplicate_state(struct drm_crtc *crtc)1537 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1538 {
1539 struct rockchip_crtc_state *rockchip_state;
1540
1541 if (WARN_ON(!crtc->state))
1542 return NULL;
1543
1544 rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state),
1545 sizeof(*rockchip_state), GFP_KERNEL);
1546 if (!rockchip_state)
1547 return NULL;
1548
1549 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1550 return &rockchip_state->base;
1551 }
1552
vop_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)1553 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1554 struct drm_crtc_state *state)
1555 {
1556 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1557
1558 __drm_atomic_helper_crtc_destroy_state(&s->base);
1559 kfree(s);
1560 }
1561
vop_crtc_reset(struct drm_crtc *crtc)1562 static void vop_crtc_reset(struct drm_crtc *crtc)
1563 {
1564 struct rockchip_crtc_state *crtc_state =
1565 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1566
1567 if (crtc->state)
1568 vop_crtc_destroy_state(crtc, crtc->state);
1569
1570 if (crtc_state)
1571 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1572 else
1573 __drm_atomic_helper_crtc_reset(crtc, NULL);
1574 }
1575
1576 #ifdef CONFIG_DRM_ANALOGIX_DP
vop_get_edp_connector(struct vop *vop)1577 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1578 {
1579 struct drm_connector *connector;
1580 struct drm_connector_list_iter conn_iter;
1581
1582 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1583 drm_for_each_connector_iter(connector, &conn_iter) {
1584 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1585 drm_connector_list_iter_end(&conn_iter);
1586 return connector;
1587 }
1588 }
1589 drm_connector_list_iter_end(&conn_iter);
1590
1591 return NULL;
1592 }
1593
vop_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)1594 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1595 const char *source_name)
1596 {
1597 struct vop *vop = to_vop(crtc);
1598 struct drm_connector *connector;
1599 int ret;
1600
1601 connector = vop_get_edp_connector(vop);
1602 if (!connector)
1603 return -EINVAL;
1604
1605 if (source_name && strcmp(source_name, "auto") == 0)
1606 ret = analogix_dp_start_crc(connector);
1607 else if (!source_name)
1608 ret = analogix_dp_stop_crc(connector);
1609 else
1610 ret = -EINVAL;
1611
1612 return ret;
1613 }
1614
1615 static int
vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, size_t *values_cnt)1616 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1617 size_t *values_cnt)
1618 {
1619 if (source_name && strcmp(source_name, "auto") != 0)
1620 return -EINVAL;
1621
1622 *values_cnt = 3;
1623 return 0;
1624 }
1625
1626 #else
vop_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)1627 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1628 const char *source_name)
1629 {
1630 return -ENODEV;
1631 }
1632
1633 static int
vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, size_t *values_cnt)1634 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1635 size_t *values_cnt)
1636 {
1637 return -ENODEV;
1638 }
1639 #endif
1640
1641 static const struct drm_crtc_funcs vop_crtc_funcs = {
1642 .set_config = drm_atomic_helper_set_config,
1643 .page_flip = drm_atomic_helper_page_flip,
1644 .destroy = vop_crtc_destroy,
1645 .reset = vop_crtc_reset,
1646 .atomic_duplicate_state = vop_crtc_duplicate_state,
1647 .atomic_destroy_state = vop_crtc_destroy_state,
1648 .enable_vblank = vop_crtc_enable_vblank,
1649 .disable_vblank = vop_crtc_disable_vblank,
1650 .set_crc_source = vop_crtc_set_crc_source,
1651 .verify_crc_source = vop_crtc_verify_crc_source,
1652 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1653 };
1654
vop_fb_unref_worker(struct drm_flip_work *work, void *val)1655 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1656 {
1657 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1658 struct drm_framebuffer *fb = val;
1659
1660 drm_crtc_vblank_put(&vop->crtc);
1661 drm_framebuffer_put(fb);
1662 }
1663
vop_handle_vblank(struct vop *vop)1664 static void vop_handle_vblank(struct vop *vop)
1665 {
1666 struct drm_device *drm = vop->drm_dev;
1667 struct drm_crtc *crtc = &vop->crtc;
1668
1669 spin_lock(&drm->event_lock);
1670 if (vop->event) {
1671 drm_crtc_send_vblank_event(crtc, vop->event);
1672 drm_crtc_vblank_put(crtc);
1673 vop->event = NULL;
1674 }
1675 spin_unlock(&drm->event_lock);
1676
1677 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1678 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1679 }
1680
vop_isr(int irq, void *data)1681 static irqreturn_t vop_isr(int irq, void *data)
1682 {
1683 struct vop *vop = data;
1684 struct drm_crtc *crtc = &vop->crtc;
1685 uint32_t active_irqs;
1686 int ret = IRQ_NONE;
1687
1688 /*
1689 * The irq is shared with the iommu. If the runtime-pm state of the
1690 * vop-device is disabled the irq has to be targeted at the iommu.
1691 */
1692 if (!pm_runtime_get_if_in_use(vop->dev))
1693 return IRQ_NONE;
1694
1695 if (vop_core_clks_enable(vop)) {
1696 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1697 goto out;
1698 }
1699
1700 /*
1701 * interrupt register has interrupt status, enable and clear bits, we
1702 * must hold irq_lock to avoid a race with enable/disable_vblank().
1703 */
1704 spin_lock(&vop->irq_lock);
1705
1706 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1707 /* Clear all active interrupt sources */
1708 if (active_irqs)
1709 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1710
1711 spin_unlock(&vop->irq_lock);
1712
1713 /* This is expected for vop iommu irqs, since the irq is shared */
1714 if (!active_irqs)
1715 goto out_disable;
1716
1717 if (active_irqs & DSP_HOLD_VALID_INTR) {
1718 complete(&vop->dsp_hold_completion);
1719 active_irqs &= ~DSP_HOLD_VALID_INTR;
1720 ret = IRQ_HANDLED;
1721 }
1722
1723 if (active_irqs & LINE_FLAG_INTR) {
1724 complete(&vop->line_flag_completion);
1725 active_irqs &= ~LINE_FLAG_INTR;
1726 ret = IRQ_HANDLED;
1727 }
1728
1729 if (active_irqs & FS_INTR) {
1730 drm_crtc_handle_vblank(crtc);
1731 vop_handle_vblank(vop);
1732 active_irqs &= ~FS_INTR;
1733 ret = IRQ_HANDLED;
1734 }
1735
1736 /* Unhandled irqs are spurious. */
1737 if (active_irqs)
1738 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1739 active_irqs);
1740
1741 out_disable:
1742 vop_core_clks_disable(vop);
1743 out:
1744 pm_runtime_put(vop->dev);
1745 return ret;
1746 }
1747
vop_plane_add_properties(struct drm_plane *plane, const struct vop_win_data *win_data)1748 static void vop_plane_add_properties(struct drm_plane *plane,
1749 const struct vop_win_data *win_data)
1750 {
1751 unsigned int flags = 0;
1752
1753 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1754 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1755 if (flags)
1756 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1757 DRM_MODE_ROTATE_0 | flags);
1758 }
1759
vop_create_crtc(struct vop *vop)1760 static int vop_create_crtc(struct vop *vop)
1761 {
1762 const struct vop_data *vop_data = vop->data;
1763 struct device *dev = vop->dev;
1764 struct drm_device *drm_dev = vop->drm_dev;
1765 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1766 struct drm_crtc *crtc = &vop->crtc;
1767 struct device_node *port;
1768 int ret;
1769 int i;
1770
1771 /*
1772 * Create drm_plane for primary and cursor planes first, since we need
1773 * to pass them to drm_crtc_init_with_planes, which sets the
1774 * "possible_crtcs" to the newly initialized crtc.
1775 */
1776 for (i = 0; i < vop_data->win_size; i++) {
1777 struct vop_win *vop_win = &vop->win[i];
1778 const struct vop_win_data *win_data = vop_win->data;
1779
1780 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1781 win_data->type != DRM_PLANE_TYPE_CURSOR)
1782 continue;
1783
1784 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1785 0, &vop_plane_funcs,
1786 win_data->phy->data_formats,
1787 win_data->phy->nformats,
1788 win_data->phy->format_modifiers,
1789 win_data->type, NULL);
1790 if (ret) {
1791 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1792 ret);
1793 goto err_cleanup_planes;
1794 }
1795
1796 plane = &vop_win->base;
1797 drm_plane_helper_add(plane, &plane_helper_funcs);
1798 vop_plane_add_properties(plane, win_data);
1799 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1800 primary = plane;
1801 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1802 cursor = plane;
1803 }
1804
1805 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1806 &vop_crtc_funcs, NULL);
1807 if (ret)
1808 goto err_cleanup_planes;
1809
1810 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1811 if (vop->lut_regs) {
1812 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size);
1813 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1814 }
1815
1816 /*
1817 * Create drm_planes for overlay windows with possible_crtcs restricted
1818 * to the newly created crtc.
1819 */
1820 for (i = 0; i < vop_data->win_size; i++) {
1821 struct vop_win *vop_win = &vop->win[i];
1822 const struct vop_win_data *win_data = vop_win->data;
1823 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1824
1825 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1826 continue;
1827
1828 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1829 possible_crtcs,
1830 &vop_plane_funcs,
1831 win_data->phy->data_formats,
1832 win_data->phy->nformats,
1833 win_data->phy->format_modifiers,
1834 win_data->type, NULL);
1835 if (ret) {
1836 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1837 ret);
1838 goto err_cleanup_crtc;
1839 }
1840 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1841 vop_plane_add_properties(&vop_win->base, win_data);
1842 }
1843
1844 port = of_get_child_by_name(dev->of_node, "port");
1845 if (!port) {
1846 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1847 dev->of_node);
1848 ret = -ENOENT;
1849 goto err_cleanup_crtc;
1850 }
1851
1852 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1853 vop_fb_unref_worker);
1854
1855 init_completion(&vop->dsp_hold_completion);
1856 init_completion(&vop->line_flag_completion);
1857 crtc->port = port;
1858
1859 ret = drm_self_refresh_helper_init(crtc);
1860 if (ret)
1861 DRM_DEV_DEBUG_KMS(vop->dev,
1862 "Failed to init %s with SR helpers %d, ignoring\n",
1863 crtc->name, ret);
1864
1865 return 0;
1866
1867 err_cleanup_crtc:
1868 drm_crtc_cleanup(crtc);
1869 err_cleanup_planes:
1870 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1871 head)
1872 drm_plane_cleanup(plane);
1873 return ret;
1874 }
1875
vop_destroy_crtc(struct vop *vop)1876 static void vop_destroy_crtc(struct vop *vop)
1877 {
1878 struct drm_crtc *crtc = &vop->crtc;
1879 struct drm_device *drm_dev = vop->drm_dev;
1880 struct drm_plane *plane, *tmp;
1881
1882 drm_self_refresh_helper_cleanup(crtc);
1883
1884 of_node_put(crtc->port);
1885
1886 /*
1887 * We need to cleanup the planes now. Why?
1888 *
1889 * The planes are "&vop->win[i].base". That means the memory is
1890 * all part of the big "struct vop" chunk of memory. That memory
1891 * was devm allocated and associated with this component. We need to
1892 * free it ourselves before vop_unbind() finishes.
1893 */
1894 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1895 head)
1896 vop_plane_destroy(plane);
1897
1898 /*
1899 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1900 * references the CRTC.
1901 */
1902 drm_crtc_cleanup(crtc);
1903 drm_flip_work_cleanup(&vop->fb_unref_work);
1904 }
1905
vop_initial(struct vop *vop)1906 static int vop_initial(struct vop *vop)
1907 {
1908 struct reset_control *ahb_rst;
1909 int i, ret;
1910
1911 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1912 if (IS_ERR(vop->hclk)) {
1913 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1914 return PTR_ERR(vop->hclk);
1915 }
1916 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1917 if (IS_ERR(vop->aclk)) {
1918 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1919 return PTR_ERR(vop->aclk);
1920 }
1921 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1922 if (IS_ERR(vop->dclk)) {
1923 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1924 return PTR_ERR(vop->dclk);
1925 }
1926
1927 ret = pm_runtime_get_sync(vop->dev);
1928 if (ret < 0) {
1929 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1930 return ret;
1931 }
1932
1933 ret = clk_prepare(vop->dclk);
1934 if (ret < 0) {
1935 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1936 goto err_put_pm_runtime;
1937 }
1938
1939 /* Enable both the hclk and aclk to setup the vop */
1940 ret = clk_prepare_enable(vop->hclk);
1941 if (ret < 0) {
1942 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1943 goto err_unprepare_dclk;
1944 }
1945
1946 ret = clk_prepare_enable(vop->aclk);
1947 if (ret < 0) {
1948 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1949 goto err_disable_hclk;
1950 }
1951
1952 /*
1953 * do hclk_reset, reset all vop registers.
1954 */
1955 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1956 if (IS_ERR(ahb_rst)) {
1957 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1958 ret = PTR_ERR(ahb_rst);
1959 goto err_disable_aclk;
1960 }
1961 reset_control_assert(ahb_rst);
1962 usleep_range(10, 20);
1963 reset_control_deassert(ahb_rst);
1964
1965 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1966 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1967
1968 for (i = 0; i < vop->len; i += sizeof(u32))
1969 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1970
1971 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1972 VOP_REG_SET(vop, common, dsp_blank, 0);
1973
1974 for (i = 0; i < vop->data->win_size; i++) {
1975 struct vop_win *vop_win = &vop->win[i];
1976 const struct vop_win_data *win = vop_win->data;
1977 int channel = i * 2 + 1;
1978
1979 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1980 vop_win_disable(vop, vop_win);
1981 VOP_WIN_SET(vop, win, gate, 1);
1982 }
1983
1984 vop_cfg_done(vop);
1985
1986 /*
1987 * do dclk_reset, let all config take affect.
1988 */
1989 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1990 if (IS_ERR(vop->dclk_rst)) {
1991 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1992 ret = PTR_ERR(vop->dclk_rst);
1993 goto err_disable_aclk;
1994 }
1995 reset_control_assert(vop->dclk_rst);
1996 usleep_range(10, 20);
1997 reset_control_deassert(vop->dclk_rst);
1998
1999 clk_disable(vop->hclk);
2000 clk_disable(vop->aclk);
2001
2002 vop->is_enabled = false;
2003
2004 pm_runtime_put_sync(vop->dev);
2005
2006 return 0;
2007
2008 err_disable_aclk:
2009 clk_disable_unprepare(vop->aclk);
2010 err_disable_hclk:
2011 clk_disable_unprepare(vop->hclk);
2012 err_unprepare_dclk:
2013 clk_unprepare(vop->dclk);
2014 err_put_pm_runtime:
2015 pm_runtime_put_sync(vop->dev);
2016 return ret;
2017 }
2018
2019 /*
2020 * Initialize the vop->win array elements.
2021 */
vop_win_init(struct vop *vop)2022 static void vop_win_init(struct vop *vop)
2023 {
2024 const struct vop_data *vop_data = vop->data;
2025 unsigned int i;
2026
2027 for (i = 0; i < vop_data->win_size; i++) {
2028 struct vop_win *vop_win = &vop->win[i];
2029 const struct vop_win_data *win_data = &vop_data->win[i];
2030
2031 vop_win->data = win_data;
2032 vop_win->vop = vop;
2033
2034 if (vop_data->win_yuv2yuv)
2035 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2036 }
2037 }
2038
2039 /**
2040 * rockchip_drm_wait_vact_end
2041 * @crtc: CRTC to enable line flag
2042 * @mstimeout: millisecond for timeout
2043 *
2044 * Wait for vact_end line flag irq or timeout.
2045 *
2046 * Returns:
2047 * Zero on success, negative errno on failure.
2048 */
rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)2049 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
2050 {
2051 struct vop *vop = to_vop(crtc);
2052 unsigned long jiffies_left;
2053 int ret = 0;
2054
2055 if (!crtc || !vop->is_enabled)
2056 return -ENODEV;
2057
2058 mutex_lock(&vop->vop_lock);
2059 if (mstimeout <= 0) {
2060 ret = -EINVAL;
2061 goto out;
2062 }
2063
2064 if (vop_line_flag_irq_is_enabled(vop)) {
2065 ret = -EBUSY;
2066 goto out;
2067 }
2068
2069 reinit_completion(&vop->line_flag_completion);
2070 vop_line_flag_irq_enable(vop);
2071
2072 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2073 msecs_to_jiffies(mstimeout));
2074 vop_line_flag_irq_disable(vop);
2075
2076 if (jiffies_left == 0) {
2077 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2078 ret = -ETIMEDOUT;
2079 goto out;
2080 }
2081
2082 out:
2083 mutex_unlock(&vop->vop_lock);
2084 return ret;
2085 }
2086 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
2087
vop_bind(struct device *dev, struct device *master, void *data)2088 static int vop_bind(struct device *dev, struct device *master, void *data)
2089 {
2090 struct platform_device *pdev = to_platform_device(dev);
2091 const struct vop_data *vop_data;
2092 struct drm_device *drm_dev = data;
2093 struct vop *vop;
2094 struct resource *res;
2095 int ret, irq;
2096
2097 vop_data = of_device_get_match_data(dev);
2098 if (!vop_data)
2099 return -ENODEV;
2100
2101 /* Allocate vop struct and its vop_win array */
2102 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2103 GFP_KERNEL);
2104 if (!vop)
2105 return -ENOMEM;
2106
2107 vop->dev = dev;
2108 vop->data = vop_data;
2109 vop->drm_dev = drm_dev;
2110 dev_set_drvdata(dev, vop);
2111
2112 vop_win_init(vop);
2113
2114 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2115 vop->regs = devm_ioremap_resource(dev, res);
2116 if (IS_ERR(vop->regs))
2117 return PTR_ERR(vop->regs);
2118 vop->len = resource_size(res);
2119
2120 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2121 if (res) {
2122 if (!vop_data->lut_size) {
2123 DRM_DEV_ERROR(dev, "no gamma LUT size defined\n");
2124 return -EINVAL;
2125 }
2126 vop->lut_regs = devm_ioremap_resource(dev, res);
2127 if (IS_ERR(vop->lut_regs))
2128 return PTR_ERR(vop->lut_regs);
2129 }
2130
2131 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2132 if (!vop->regsbak)
2133 return -ENOMEM;
2134
2135 irq = platform_get_irq(pdev, 0);
2136 if (irq < 0) {
2137 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2138 return irq;
2139 }
2140 vop->irq = (unsigned int)irq;
2141
2142 spin_lock_init(&vop->reg_lock);
2143 spin_lock_init(&vop->irq_lock);
2144 mutex_init(&vop->vop_lock);
2145
2146 ret = vop_create_crtc(vop);
2147 if (ret)
2148 return ret;
2149
2150 pm_runtime_enable(&pdev->dev);
2151
2152 ret = vop_initial(vop);
2153 if (ret < 0) {
2154 DRM_DEV_ERROR(&pdev->dev,
2155 "cannot initial vop dev - err %d\n", ret);
2156 goto err_disable_pm_runtime;
2157 }
2158
2159 ret = devm_request_irq(dev, vop->irq, vop_isr,
2160 IRQF_SHARED, dev_name(dev), vop);
2161 if (ret)
2162 goto err_disable_pm_runtime;
2163
2164 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2165 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
2166 if (IS_ERR(vop->rgb)) {
2167 ret = PTR_ERR(vop->rgb);
2168 goto err_disable_pm_runtime;
2169 }
2170 }
2171
2172 return 0;
2173
2174 err_disable_pm_runtime:
2175 pm_runtime_disable(&pdev->dev);
2176 vop_destroy_crtc(vop);
2177 return ret;
2178 }
2179
vop_unbind(struct device *dev, struct device *master, void *data)2180 static void vop_unbind(struct device *dev, struct device *master, void *data)
2181 {
2182 struct vop *vop = dev_get_drvdata(dev);
2183
2184 if (vop->rgb)
2185 rockchip_rgb_fini(vop->rgb);
2186
2187 pm_runtime_disable(dev);
2188 vop_destroy_crtc(vop);
2189
2190 clk_unprepare(vop->aclk);
2191 clk_unprepare(vop->hclk);
2192 clk_unprepare(vop->dclk);
2193 }
2194
2195 const struct component_ops vop_component_ops = {
2196 .bind = vop_bind,
2197 .unbind = vop_unbind,
2198 };
2199 EXPORT_SYMBOL_GPL(vop_component_ops);
2200