1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "reg_helper.h"
29 #include "dcn30_dpp.h"
30 #include "basics/conversion.h"
31 #include "dcn30_cm_common.h"
32
33 #define REG(reg)\
34 dpp->tf_regs->reg
35
36 #define CTX \
37 dpp->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)44 void dpp30_read_state(struct dpp *dpp_base,
45 struct dcn_dpp_state *s)
46 {
47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
48
49 REG_GET(DPP_CONTROL,
50 DPP_CLOCK_ENABLE, &s->is_enabled);
51
52 // TODO: Implement for DCN3
53 }
54 /*program post scaler scs block in dpp CM*/
dpp3_program_post_csc( struct dpp *dpp_base, enum dc_color_space color_space, enum dcn10_input_csc_select input_select, const struct out_csc_color_matrix *tbl_entry)55 void dpp3_program_post_csc(
56 struct dpp *dpp_base,
57 enum dc_color_space color_space,
58 enum dcn10_input_csc_select input_select,
59 const struct out_csc_color_matrix *tbl_entry)
60 {
61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
62 int i;
63 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
64 const uint16_t *regval = NULL;
65 uint32_t cur_select = 0;
66 enum dcn10_input_csc_select select;
67 struct color_matrices_reg gam_regs;
68
69 if (input_select == INPUT_CSC_SELECT_BYPASS) {
70 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
71 return;
72 }
73
74 if (tbl_entry == NULL) {
75 for (i = 0; i < arr_size; i++)
76 if (dpp_input_csc_matrix[i].color_space == color_space) {
77 regval = dpp_input_csc_matrix[i].regval;
78 break;
79 }
80
81 if (regval == NULL) {
82 BREAK_TO_DEBUGGER();
83 return;
84 }
85 } else {
86 regval = tbl_entry->regval;
87 }
88
89 /* determine which CSC matrix (icsc or coma) we are using
90 * currently. select the alternate set to double buffer
91 * the CSC update so CSC is updated on frame boundary
92 */
93 REG_GET(CM_POST_CSC_CONTROL,
94 CM_POST_CSC_MODE_CURRENT, &cur_select);
95
96 if (cur_select != INPUT_CSC_SELECT_ICSC)
97 select = INPUT_CSC_SELECT_ICSC;
98 else
99 select = INPUT_CSC_SELECT_COMA;
100
101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
102 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
104 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
105
106 if (select == INPUT_CSC_SELECT_ICSC) {
107
108 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
109 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
110
111 } else {
112
113 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
114 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
115
116 }
117
118 cm_helper_program_color_matrices(
119 dpp->base.ctx,
120 regval,
121 &gam_regs);
122
123 REG_SET(CM_POST_CSC_CONTROL, 0,
124 CM_POST_CSC_MODE, select);
125 }
126
127
128 /*CNVC degam unit has read only LUTs*/
dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)129 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
130 {
131 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
132 int pre_degam_en = 1;
133 int degamma_lut_selection = 0;
134
135 switch (tr) {
136 case TRANSFER_FUNCTION_LINEAR:
137 case TRANSFER_FUNCTION_UNITY:
138 pre_degam_en = 0; //bypass
139 break;
140 case TRANSFER_FUNCTION_SRGB:
141 degamma_lut_selection = 0;
142 break;
143 case TRANSFER_FUNCTION_BT709:
144 degamma_lut_selection = 4;
145 break;
146 case TRANSFER_FUNCTION_PQ:
147 degamma_lut_selection = 5;
148 break;
149 case TRANSFER_FUNCTION_HLG:
150 degamma_lut_selection = 6;
151 break;
152 case TRANSFER_FUNCTION_GAMMA22:
153 degamma_lut_selection = 1;
154 break;
155 case TRANSFER_FUNCTION_GAMMA24:
156 degamma_lut_selection = 2;
157 break;
158 case TRANSFER_FUNCTION_GAMMA26:
159 degamma_lut_selection = 3;
160 break;
161 default:
162 pre_degam_en = 0;
163 break;
164 }
165
166 REG_SET_2(PRE_DEGAM, 0,
167 PRE_DEGAM_MODE, pre_degam_en,
168 PRE_DEGAM_SELECT, degamma_lut_selection);
169 }
170
dpp3_cnv_setup( struct dpp *dpp_base, enum surface_pixel_format format, enum expansion_mode mode, struct dc_csc_transform input_csc_color_matrix, enum dc_color_space input_color_space, struct cnv_alpha_2bit_lut *alpha_2bit_lut)171 static void dpp3_cnv_setup (
172 struct dpp *dpp_base,
173 enum surface_pixel_format format,
174 enum expansion_mode mode,
175 struct dc_csc_transform input_csc_color_matrix,
176 enum dc_color_space input_color_space,
177 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
178 {
179 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
180 uint32_t pixel_format = 0;
181 uint32_t alpha_en = 1;
182 enum dc_color_space color_space = COLOR_SPACE_SRGB;
183 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
184 bool force_disable_cursor = false;
185 uint32_t is_2bit = 0;
186 uint32_t alpha_plane_enable = 0;
187 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
188 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
189 uint32_t program_prealpha_dealpha = 0;
190 struct out_csc_color_matrix tbl_entry;
191 int i;
192
193 REG_SET_2(FORMAT_CONTROL, 0,
194 CNVC_BYPASS, 0,
195 FORMAT_EXPANSION_MODE, mode);
196
197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
201
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
205
206 switch (format) {
207 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
208 pixel_format = 1;
209 break;
210 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
211 pixel_format = 3;
212 alpha_en = 0;
213 break;
214 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
215 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
216 pixel_format = 8;
217 break;
218 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
219 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
220 pixel_format = 10;
221 is_2bit = 1;
222 break;
223 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
224 force_disable_cursor = false;
225 pixel_format = 65;
226 color_space = COLOR_SPACE_YCBCR709;
227 select = INPUT_CSC_SELECT_ICSC;
228 break;
229 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
230 force_disable_cursor = true;
231 pixel_format = 64;
232 color_space = COLOR_SPACE_YCBCR709;
233 select = INPUT_CSC_SELECT_ICSC;
234 break;
235 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
236 force_disable_cursor = true;
237 pixel_format = 67;
238 color_space = COLOR_SPACE_YCBCR709;
239 select = INPUT_CSC_SELECT_ICSC;
240 break;
241 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
242 force_disable_cursor = true;
243 pixel_format = 66;
244 color_space = COLOR_SPACE_YCBCR709;
245 select = INPUT_CSC_SELECT_ICSC;
246 break;
247 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
248 pixel_format = 22;
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
251 pixel_format = 24;
252 break;
253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
254 pixel_format = 25;
255 break;
256 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
257 pixel_format = 12;
258 color_space = COLOR_SPACE_YCBCR709;
259 select = INPUT_CSC_SELECT_ICSC;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
262 pixel_format = 112;
263 break;
264 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
265 pixel_format = 113;
266 break;
267 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
268 pixel_format = 114;
269 color_space = COLOR_SPACE_YCBCR709;
270 select = INPUT_CSC_SELECT_ICSC;
271 is_2bit = 1;
272 break;
273 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
274 pixel_format = 115;
275 color_space = COLOR_SPACE_YCBCR709;
276 select = INPUT_CSC_SELECT_ICSC;
277 is_2bit = 1;
278 break;
279 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
280 pixel_format = 116;
281 alpha_plane_enable = 0;
282 break;
283 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
284 pixel_format = 116;
285 alpha_plane_enable = 1;
286 break;
287 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
288 pixel_format = 118;
289 break;
290 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
291 pixel_format = 119;
292 break;
293 default:
294 break;
295 }
296
297 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
298 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
299 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
300 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
302 }
303
304 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
305 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
306 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
307 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
308
309 if (program_prealpha_dealpha) {
310 dealpha_en = 1;
311 realpha_en = 1;
312 }
313 REG_SET_2(PRE_DEALPHA, 0,
314 PRE_DEALPHA_EN, dealpha_en,
315 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
316 REG_SET_2(PRE_REALPHA, 0,
317 PRE_REALPHA_EN, realpha_en,
318 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
319
320 /* If input adjustment exists, program the ICSC with those values. */
321 if (input_csc_color_matrix.enable_adjustment == true) {
322 for (i = 0; i < 12; i++)
323 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
324
325 tbl_entry.color_space = input_color_space;
326
327 if (color_space >= COLOR_SPACE_YCBCR601)
328 select = INPUT_CSC_SELECT_ICSC;
329 else
330 select = INPUT_CSC_SELECT_BYPASS;
331
332 dpp3_program_post_csc(dpp_base, color_space, select,
333 &tbl_entry);
334 } else {
335 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
336 }
337
338 if (force_disable_cursor) {
339 REG_UPDATE(CURSOR_CONTROL,
340 CURSOR_ENABLE, 0);
341 REG_UPDATE(CURSOR0_CONTROL,
342 CUR0_ENABLE, 0);
343 }
344 }
345
346 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
347
dpp3_set_cursor_attributes( struct dpp *dpp_base, struct dc_cursor_attributes *cursor_attributes)348 void dpp3_set_cursor_attributes(
349 struct dpp *dpp_base,
350 struct dc_cursor_attributes *cursor_attributes)
351 {
352 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
353 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
354 int cur_rom_en = 0;
355
356 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
357 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
358 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
359 cur_rom_en = 1;
360 }
361 }
362
363 REG_UPDATE_3(CURSOR0_CONTROL,
364 CUR0_MODE, color_format,
365 CUR0_EXPANSION_MODE, 0,
366 CUR0_ROM_EN, cur_rom_en);
367
368 if (color_format == CURSOR_MODE_MONO) {
369 /* todo: clarify what to program these to */
370 REG_UPDATE(CURSOR0_COLOR0,
371 CUR0_COLOR0, 0x00000000);
372 REG_UPDATE(CURSOR0_COLOR1,
373 CUR0_COLOR1, 0xFFFFFFFF);
374 }
375 }
376
377
dpp3_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps)378 bool dpp3_get_optimal_number_of_taps(
379 struct dpp *dpp,
380 struct scaler_data *scl_data,
381 const struct scaling_taps *in_taps)
382 {
383 int num_part_y, num_part_c;
384 int max_taps_y, max_taps_c;
385 int min_taps_y, min_taps_c;
386 enum lb_memory_config lb_config;
387
388 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/
389 if (scl_data->viewport.width != scl_data->h_active &&
390 scl_data->viewport.height != scl_data->v_active &&
391 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
392 scl_data->format == PIXEL_FORMAT_FP16)
393 return false;
394
395 if (scl_data->viewport.width > scl_data->h_active &&
396 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
397 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
398 return false;
399
400 /*
401 * Set default taps if none are provided
402 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
403 * taps = 4 for upscaling
404 */
405 if (in_taps->h_taps == 0) {
406 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
407 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
408 else
409 scl_data->taps.h_taps = 4;
410 } else
411 scl_data->taps.h_taps = in_taps->h_taps;
412 if (in_taps->v_taps == 0) {
413 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
414 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
415 else
416 scl_data->taps.v_taps = 4;
417 } else
418 scl_data->taps.v_taps = in_taps->v_taps;
419 if (in_taps->v_taps_c == 0) {
420 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
421 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
422 else
423 scl_data->taps.v_taps_c = 4;
424 } else
425 scl_data->taps.v_taps_c = in_taps->v_taps_c;
426 if (in_taps->h_taps_c == 0) {
427 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
428 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
429 else
430 scl_data->taps.h_taps_c = 4;
431 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
432 /* Only 1 and even h_taps_c are supported by hw */
433 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
434 else
435 scl_data->taps.h_taps_c = in_taps->h_taps_c;
436
437 /*Ensure we can support the requested number of vtaps*/
438 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
439 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
440
441 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
442 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
443 lb_config = LB_MEMORY_CONFIG_3;
444 else
445 lb_config = LB_MEMORY_CONFIG_0;
446
447 dpp->caps->dscl_calc_lb_num_partitions(
448 scl_data, lb_config, &num_part_y, &num_part_c);
449
450 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
451 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
452 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
453 else
454 max_taps_y = num_part_y;
455
456 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
457 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
458 else
459 max_taps_c = num_part_c;
460
461 if (max_taps_y < min_taps_y)
462 return false;
463 else if (max_taps_c < min_taps_c)
464 return false;
465
466 if (scl_data->taps.v_taps > max_taps_y)
467 scl_data->taps.v_taps = max_taps_y;
468
469 if (scl_data->taps.v_taps_c > max_taps_c)
470 scl_data->taps.v_taps_c = max_taps_c;
471
472 if (!dpp->ctx->dc->debug.always_scale) {
473 if (IDENTITY_RATIO(scl_data->ratios.horz))
474 scl_data->taps.h_taps = 1;
475 if (IDENTITY_RATIO(scl_data->ratios.vert))
476 scl_data->taps.v_taps = 1;
477 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
478 scl_data->taps.h_taps_c = 1;
479 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
480 scl_data->taps.v_taps_c = 1;
481 }
482
483 return true;
484 }
485
dpp3_cnv_set_bias_scale( struct dpp *dpp_base, struct dc_bias_and_scale *bias_and_scale)486 void dpp3_cnv_set_bias_scale(
487 struct dpp *dpp_base,
488 struct dc_bias_and_scale *bias_and_scale)
489 {
490 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
491
492 REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
493 REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
494 REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
495 REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
496 REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
497 REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
498 }
499
dpp3_power_on_blnd_lut( struct dpp *dpp_base, bool power_on)500 static void dpp3_power_on_blnd_lut(
501 struct dpp *dpp_base,
502 bool power_on)
503 {
504 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
505
506 REG_SET(CM_MEM_PWR_CTRL, 0,
507 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
508
509 }
510
dpp3_configure_blnd_lut( struct dpp *dpp_base, bool is_ram_a)511 static void dpp3_configure_blnd_lut(
512 struct dpp *dpp_base,
513 bool is_ram_a)
514 {
515 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
516
517 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
518 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
519 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
520
521 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
522 }
523
dpp3_program_blnd_pwl( struct dpp *dpp_base, const struct pwl_result_data *rgb, uint32_t num)524 static void dpp3_program_blnd_pwl(
525 struct dpp *dpp_base,
526 const struct pwl_result_data *rgb,
527 uint32_t num)
528 {
529 uint32_t i;
530 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
531 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
532 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
533 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
534
535 if (is_rgb_equal(rgb, num)) {
536 for (i = 0 ; i < num; i++)
537 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
538 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
539 } else {
540 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
541 for (i = 0 ; i < num; i++)
542 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
543 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
544
545 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
546 for (i = 0 ; i < num; i++)
547 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
548 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
549
550 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
551 for (i = 0 ; i < num; i++)
552 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
553 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
554 }
555 }
556
dcn3_dpp_cm_get_reg_field( struct dcn3_dpp *dpp, struct dcn3_xfer_func_reg *reg)557 static void dcn3_dpp_cm_get_reg_field(
558 struct dcn3_dpp *dpp,
559 struct dcn3_xfer_func_reg *reg)
560 {
561 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
562 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
563 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
564 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
565 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
566 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
567 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
568 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
569
570 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
571 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
572 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
573 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
574 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
575 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
576 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
577 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
578 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
579 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
580 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
581 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
582 }
583
584 /*program blnd lut RAM A*/
dpp3_program_blnd_luta_settings( struct dpp *dpp_base, const struct pwl_params *params)585 static void dpp3_program_blnd_luta_settings(
586 struct dpp *dpp_base,
587 const struct pwl_params *params)
588 {
589 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
590 struct dcn3_xfer_func_reg gam_regs;
591
592 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
593
594 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
595 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
596 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
597 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
598 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
599 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
600 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
601 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
602 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
603 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
604 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
605 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
606 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
607 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
608
609 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
610 }
611
612 /*program blnd lut RAM B*/
dpp3_program_blnd_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params)613 static void dpp3_program_blnd_lutb_settings(
614 struct dpp *dpp_base,
615 const struct pwl_params *params)
616 {
617 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
618 struct dcn3_xfer_func_reg gam_regs;
619
620 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
621
622 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
623 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
624 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
625 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
626 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
627 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
628 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
629 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
630 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
631 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
632 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
633 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
634 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
635 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
636
637 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
638 }
639
dpp3_get_blndgam_current(struct dpp *dpp_base)640 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
641 {
642 enum dc_lut_mode mode;
643 uint32_t mode_current = 0;
644 uint32_t in_use = 0;
645
646 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
647
648 REG_GET(CM_BLNDGAM_CONTROL,
649 CM_BLNDGAM_MODE_CURRENT, &mode_current);
650 REG_GET(CM_BLNDGAM_CONTROL,
651 CM_BLNDGAM_SELECT_CURRENT, &in_use);
652
653 switch (mode_current) {
654 case 0:
655 case 1:
656 mode = LUT_BYPASS;
657 break;
658
659 case 2:
660 if (in_use == 0)
661 mode = LUT_RAM_A;
662 else
663 mode = LUT_RAM_B;
664 break;
665 default:
666 mode = LUT_BYPASS;
667 break;
668 }
669 return mode;
670 }
671
dpp3_program_blnd_lut( struct dpp *dpp_base, const struct pwl_params *params)672 bool dpp3_program_blnd_lut(
673 struct dpp *dpp_base, const struct pwl_params *params)
674 {
675 enum dc_lut_mode current_mode;
676 enum dc_lut_mode next_mode;
677 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
678
679 if (params == NULL) {
680 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
681 return false;
682 }
683
684 current_mode = dpp3_get_blndgam_current(dpp_base);
685 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
686 next_mode = LUT_RAM_A;
687 else
688 next_mode = LUT_RAM_B;
689
690 dpp3_power_on_blnd_lut(dpp_base, true);
691 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
692
693 if (next_mode == LUT_RAM_A)
694 dpp3_program_blnd_luta_settings(dpp_base, params);
695 else
696 dpp3_program_blnd_lutb_settings(dpp_base, params);
697
698 dpp3_program_blnd_pwl(
699 dpp_base, params->rgb_resulted, params->hw_points_num);
700
701 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
702 CM_BLNDGAM_MODE, 2,
703 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
704
705 return true;
706 }
707
708
dpp3_program_shaper_lut( struct dpp *dpp_base, const struct pwl_result_data *rgb, uint32_t num)709 static void dpp3_program_shaper_lut(
710 struct dpp *dpp_base,
711 const struct pwl_result_data *rgb,
712 uint32_t num)
713 {
714 uint32_t i, red, green, blue;
715 uint32_t red_delta, green_delta, blue_delta;
716 uint32_t red_value, green_value, blue_value;
717
718 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
719
720 for (i = 0 ; i < num; i++) {
721
722 red = rgb[i].red_reg;
723 green = rgb[i].green_reg;
724 blue = rgb[i].blue_reg;
725
726 red_delta = rgb[i].delta_red_reg;
727 green_delta = rgb[i].delta_green_reg;
728 blue_delta = rgb[i].delta_blue_reg;
729
730 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
731 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
732 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
733
734 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
735 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
736 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
737 }
738
739 }
740
dpp3_get_shaper_current(struct dpp *dpp_base)741 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
742 {
743 enum dc_lut_mode mode;
744 uint32_t state_mode;
745 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
746
747 REG_GET(CM_SHAPER_CONTROL,
748 CM_SHAPER_MODE_CURRENT, &state_mode);
749
750 switch (state_mode) {
751 case 0:
752 mode = LUT_BYPASS;
753 break;
754 case 1:
755 mode = LUT_RAM_A;
756 break;
757 case 2:
758 mode = LUT_RAM_B;
759 break;
760 default:
761 mode = LUT_BYPASS;
762 break;
763 }
764 return mode;
765 }
766
dpp3_configure_shaper_lut( struct dpp *dpp_base, bool is_ram_a)767 static void dpp3_configure_shaper_lut(
768 struct dpp *dpp_base,
769 bool is_ram_a)
770 {
771 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
772
773 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
774 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
775 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
776 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
777 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
778 }
779
780 /*program shaper RAM A*/
781
dpp3_program_shaper_luta_settings( struct dpp *dpp_base, const struct pwl_params *params)782 static void dpp3_program_shaper_luta_settings(
783 struct dpp *dpp_base,
784 const struct pwl_params *params)
785 {
786 const struct gamma_curve *curve;
787 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
788
789 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
790 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
791 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
792 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
793 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
794 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
795 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
796 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
797 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
798
799 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
800 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
801 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
802
803 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
804 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
805 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
806
807 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
808 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
809 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
810
811 curve = params->arr_curve_points;
812 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
813 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
814 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
815 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
816 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
817
818 curve += 2;
819 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
820 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
821 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
822 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
823 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
824
825 curve += 2;
826 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
827 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
828 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
829 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
830 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
831
832 curve += 2;
833 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
834 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
835 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
836 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
837 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
838
839 curve += 2;
840 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
841 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
842 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
843 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
844 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
845
846 curve += 2;
847 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
848 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
849 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
850 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
851 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
852
853 curve += 2;
854 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
855 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
856 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
857 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
858 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
859
860 curve += 2;
861 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
862 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
863 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
864 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
865 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
866
867 curve += 2;
868 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
869 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
870 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
871 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
872 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
873
874 curve += 2;
875 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
876 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
877 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
878 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
879 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
880
881 curve += 2;
882 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
883 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
884 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
885 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
886 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
887
888 curve += 2;
889 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
890 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
891 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
892 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
893 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
894
895 curve += 2;
896 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
897 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
898 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
899 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
900 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
901
902 curve += 2;
903 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
904 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
905 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
906 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
907 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
908
909 curve += 2;
910 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
911 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
912 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
913 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
914 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
915
916 curve += 2;
917 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
918 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
919 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
920 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
921 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
922
923 curve += 2;
924 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
925 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
926 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
927 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
928 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
929 }
930
931 /*program shaper RAM B*/
dpp3_program_shaper_lutb_settings( struct dpp *dpp_base, const struct pwl_params *params)932 static void dpp3_program_shaper_lutb_settings(
933 struct dpp *dpp_base,
934 const struct pwl_params *params)
935 {
936 const struct gamma_curve *curve;
937 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
938
939 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
940 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
941 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
942 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
943 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
944 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
945 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
946 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
947 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
948
949 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
950 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
951 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
952
953 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
954 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
955 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
956
957 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
958 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
959 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
960
961 curve = params->arr_curve_points;
962 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
963 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
964 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
965 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
966 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
967
968 curve += 2;
969 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
970 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
971 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
972 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
973 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
974
975 curve += 2;
976 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
977 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
978 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
979 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
980 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
981
982 curve += 2;
983 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
984 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
985 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
986 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
987 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
988
989 curve += 2;
990 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
991 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
992 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
993 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
994 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
995
996 curve += 2;
997 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
998 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
999 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1000 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1001 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1002
1003 curve += 2;
1004 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1005 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1006 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1007 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1008 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1009
1010 curve += 2;
1011 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1012 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1013 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1014 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1015 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1016
1017 curve += 2;
1018 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1019 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1020 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1021 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1022 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1023
1024 curve += 2;
1025 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1026 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1027 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1028 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1029 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1030
1031 curve += 2;
1032 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1033 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1034 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1035 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1036 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1037
1038 curve += 2;
1039 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1040 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1041 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1042 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1043 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1044
1045 curve += 2;
1046 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1047 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1048 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1049 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1050 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1051
1052 curve += 2;
1053 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1054 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1055 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1056 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1057 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1058
1059 curve += 2;
1060 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1061 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1062 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1063 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1064 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1065
1066 curve += 2;
1067 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1068 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1069 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1070 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1071 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1072
1073 curve += 2;
1074 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1075 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1076 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1077 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1078 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1079
1080 }
1081
1082
dpp3_program_shaper( struct dpp *dpp_base, const struct pwl_params *params)1083 bool dpp3_program_shaper(
1084 struct dpp *dpp_base,
1085 const struct pwl_params *params)
1086 {
1087 enum dc_lut_mode current_mode;
1088 enum dc_lut_mode next_mode;
1089
1090 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1091
1092 if (params == NULL) {
1093 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1094 return false;
1095 }
1096 current_mode = dpp3_get_shaper_current(dpp_base);
1097
1098 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1099 next_mode = LUT_RAM_B;
1100 else
1101 next_mode = LUT_RAM_A;
1102
1103 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
1104
1105 if (next_mode == LUT_RAM_A)
1106 dpp3_program_shaper_luta_settings(dpp_base, params);
1107 else
1108 dpp3_program_shaper_lutb_settings(dpp_base, params);
1109
1110 dpp3_program_shaper_lut(
1111 dpp_base, params->rgb_resulted, params->hw_points_num);
1112
1113 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1114
1115 return true;
1116
1117 }
1118
get3dlut_config( struct dpp *dpp_base, bool *is_17x17x17, bool *is_12bits_color_channel)1119 static enum dc_lut_mode get3dlut_config(
1120 struct dpp *dpp_base,
1121 bool *is_17x17x17,
1122 bool *is_12bits_color_channel)
1123 {
1124 uint32_t i_mode, i_enable_10bits, lut_size;
1125 enum dc_lut_mode mode;
1126 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1127
1128 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1129 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1130 REG_GET(CM_3DLUT_MODE,
1131 CM_3DLUT_MODE_CURRENT, &i_mode);
1132
1133 switch (i_mode) {
1134 case 0:
1135 mode = LUT_BYPASS;
1136 break;
1137 case 1:
1138 mode = LUT_RAM_A;
1139 break;
1140 case 2:
1141 mode = LUT_RAM_B;
1142 break;
1143 default:
1144 mode = LUT_BYPASS;
1145 break;
1146 }
1147 if (i_enable_10bits > 0)
1148 *is_12bits_color_channel = false;
1149 else
1150 *is_12bits_color_channel = true;
1151
1152 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1153
1154 if (lut_size == 0)
1155 *is_17x17x17 = true;
1156 else
1157 *is_17x17x17 = false;
1158
1159 return mode;
1160 }
1161 /*
1162 * select ramA or ramB, or bypass
1163 * select color channel size 10 or 12 bits
1164 * select 3dlut size 17x17x17 or 9x9x9
1165 */
dpp3_set_3dlut_mode( struct dpp *dpp_base, enum dc_lut_mode mode, bool is_color_channel_12bits, bool is_lut_size17x17x17)1166 static void dpp3_set_3dlut_mode(
1167 struct dpp *dpp_base,
1168 enum dc_lut_mode mode,
1169 bool is_color_channel_12bits,
1170 bool is_lut_size17x17x17)
1171 {
1172 uint32_t lut_mode;
1173 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1174
1175 if (mode == LUT_BYPASS)
1176 lut_mode = 0;
1177 else if (mode == LUT_RAM_A)
1178 lut_mode = 1;
1179 else
1180 lut_mode = 2;
1181
1182 REG_UPDATE_2(CM_3DLUT_MODE,
1183 CM_3DLUT_MODE, lut_mode,
1184 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1185 }
1186
dpp3_select_3dlut_ram( struct dpp *dpp_base, enum dc_lut_mode mode, bool is_color_channel_12bits)1187 static void dpp3_select_3dlut_ram(
1188 struct dpp *dpp_base,
1189 enum dc_lut_mode mode,
1190 bool is_color_channel_12bits)
1191 {
1192 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1193
1194 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1195 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1196 CM_3DLUT_30BIT_EN,
1197 is_color_channel_12bits == true ? 0:1);
1198 }
1199
1200
1201
dpp3_set3dlut_ram12( struct dpp *dpp_base, const struct dc_rgb *lut, uint32_t entries)1202 static void dpp3_set3dlut_ram12(
1203 struct dpp *dpp_base,
1204 const struct dc_rgb *lut,
1205 uint32_t entries)
1206 {
1207 uint32_t i, red, green, blue, red1, green1, blue1;
1208 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1209
1210 for (i = 0 ; i < entries; i += 2) {
1211 red = lut[i].red<<4;
1212 green = lut[i].green<<4;
1213 blue = lut[i].blue<<4;
1214 red1 = lut[i+1].red<<4;
1215 green1 = lut[i+1].green<<4;
1216 blue1 = lut[i+1].blue<<4;
1217
1218 REG_SET_2(CM_3DLUT_DATA, 0,
1219 CM_3DLUT_DATA0, red,
1220 CM_3DLUT_DATA1, red1);
1221
1222 REG_SET_2(CM_3DLUT_DATA, 0,
1223 CM_3DLUT_DATA0, green,
1224 CM_3DLUT_DATA1, green1);
1225
1226 REG_SET_2(CM_3DLUT_DATA, 0,
1227 CM_3DLUT_DATA0, blue,
1228 CM_3DLUT_DATA1, blue1);
1229
1230 }
1231 }
1232
1233 /*
1234 * load selected lut with 10 bits color channels
1235 */
dpp3_set3dlut_ram10( struct dpp *dpp_base, const struct dc_rgb *lut, uint32_t entries)1236 static void dpp3_set3dlut_ram10(
1237 struct dpp *dpp_base,
1238 const struct dc_rgb *lut,
1239 uint32_t entries)
1240 {
1241 uint32_t i, red, green, blue, value;
1242 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1243
1244 for (i = 0; i < entries; i++) {
1245 red = lut[i].red;
1246 green = lut[i].green;
1247 blue = lut[i].blue;
1248
1249 value = (red<<20) | (green<<10) | blue;
1250
1251 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1252 }
1253
1254 }
1255
1256
dpp3_select_3dlut_ram_mask( struct dpp *dpp_base, uint32_t ram_selection_mask)1257 static void dpp3_select_3dlut_ram_mask(
1258 struct dpp *dpp_base,
1259 uint32_t ram_selection_mask)
1260 {
1261 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1262
1263 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1264 ram_selection_mask);
1265 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1266 }
1267
dpp3_program_3dlut( struct dpp *dpp_base, struct tetrahedral_params *params)1268 bool dpp3_program_3dlut(
1269 struct dpp *dpp_base,
1270 struct tetrahedral_params *params)
1271 {
1272 enum dc_lut_mode mode;
1273 bool is_17x17x17;
1274 bool is_12bits_color_channel;
1275 struct dc_rgb *lut0;
1276 struct dc_rgb *lut1;
1277 struct dc_rgb *lut2;
1278 struct dc_rgb *lut3;
1279 int lut_size0;
1280 int lut_size;
1281
1282 if (params == NULL) {
1283 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1284 return false;
1285 }
1286 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1287
1288 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1289 mode = LUT_RAM_A;
1290 else
1291 mode = LUT_RAM_B;
1292
1293 is_17x17x17 = !params->use_tetrahedral_9;
1294 is_12bits_color_channel = params->use_12bits;
1295 if (is_17x17x17) {
1296 lut0 = params->tetrahedral_17.lut0;
1297 lut1 = params->tetrahedral_17.lut1;
1298 lut2 = params->tetrahedral_17.lut2;
1299 lut3 = params->tetrahedral_17.lut3;
1300 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1301 sizeof(params->tetrahedral_17.lut0[0]);
1302 lut_size = sizeof(params->tetrahedral_17.lut1)/
1303 sizeof(params->tetrahedral_17.lut1[0]);
1304 } else {
1305 lut0 = params->tetrahedral_9.lut0;
1306 lut1 = params->tetrahedral_9.lut1;
1307 lut2 = params->tetrahedral_9.lut2;
1308 lut3 = params->tetrahedral_9.lut3;
1309 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1310 sizeof(params->tetrahedral_9.lut0[0]);
1311 lut_size = sizeof(params->tetrahedral_9.lut1)/
1312 sizeof(params->tetrahedral_9.lut1[0]);
1313 }
1314
1315 dpp3_select_3dlut_ram(dpp_base, mode,
1316 is_12bits_color_channel);
1317 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1318 if (is_12bits_color_channel)
1319 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1320 else
1321 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1322
1323 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1324 if (is_12bits_color_channel)
1325 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1326 else
1327 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1328
1329 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1330 if (is_12bits_color_channel)
1331 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1332 else
1333 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1334
1335 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1336 if (is_12bits_color_channel)
1337 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1338 else
1339 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1340
1341
1342 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1343 is_17x17x17);
1344
1345 return true;
1346 }
1347 static struct dpp_funcs dcn30_dpp_funcs = {
1348 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1349 .dpp_read_state = dpp30_read_state,
1350 .dpp_reset = dpp_reset,
1351 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1352 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1353 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1354 .dpp_set_csc_adjustment = NULL,
1355 .dpp_set_csc_default = NULL,
1356 .dpp_program_regamma_pwl = NULL,
1357 .dpp_set_pre_degam = dpp3_set_pre_degam,
1358 .dpp_program_input_lut = NULL,
1359 .dpp_full_bypass = dpp1_full_bypass,
1360 .dpp_setup = dpp3_cnv_setup,
1361 .dpp_program_degamma_pwl = NULL,
1362 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1363 .dpp_program_cm_bias = dpp3_program_cm_bias,
1364 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1365 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1366 .dpp_program_shaper_lut = dpp3_program_shaper,
1367 .dpp_program_3dlut = dpp3_program_3dlut,
1368 #else
1369 .dpp_program_blnd_lut = NULL,
1370 .dpp_program_shaper_lut = NULL,
1371 .dpp_program_3dlut = NULL,
1372 #endif
1373
1374 .dpp_program_bias_and_scale = NULL,
1375 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1376 .set_cursor_attributes = dpp3_set_cursor_attributes,
1377 .set_cursor_position = dpp1_set_cursor_position,
1378 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1379 .dpp_dppclk_control = dpp1_dppclk_control,
1380 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1381 };
1382
1383
1384 static struct dpp_caps dcn30_dpp_cap = {
1385 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1386 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1387 };
1388
dpp3_construct( struct dcn3_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn3_dpp_registers *tf_regs, const struct dcn3_dpp_shift *tf_shift, const struct dcn3_dpp_mask *tf_mask)1389 bool dpp3_construct(
1390 struct dcn3_dpp *dpp,
1391 struct dc_context *ctx,
1392 uint32_t inst,
1393 const struct dcn3_dpp_registers *tf_regs,
1394 const struct dcn3_dpp_shift *tf_shift,
1395 const struct dcn3_dpp_mask *tf_mask)
1396 {
1397 dpp->base.ctx = ctx;
1398
1399 dpp->base.inst = inst;
1400 dpp->base.funcs = &dcn30_dpp_funcs;
1401 dpp->base.caps = &dcn30_dpp_cap;
1402
1403 dpp->tf_regs = tf_regs;
1404 dpp->tf_shift = tf_shift;
1405 dpp->tf_mask = tf_mask;
1406
1407 dpp->lb_pixel_depth_supported =
1408 LB_PIXEL_DEPTH_18BPP |
1409 LB_PIXEL_DEPTH_24BPP |
1410 LB_PIXEL_DEPTH_30BPP;
1411
1412 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
1413 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
1414
1415 return true;
1416 }
1417
1418