1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/plat-pxa/gpio.c
4 *
5 * Generic PXA GPIO handling
6 *
7 * Author: Nicolas Pitre
8 * Created: Jun 15, 2001
9 * Copyright: MontaVista Software Inc.
10 */
11 #include <linux/module.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/gpio-pxa.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/slab.h>
28
29 /*
30 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
31 * one set of registers. The register offsets are organized below:
32 *
33 * GPLR GPDR GPSR GPCR GRER GFER GEDR
34 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
35 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
36 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
37 *
38 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
39 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
40 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
41 *
42 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
43 *
44 * NOTE:
45 * BANK 3 is only available on PXA27x and later processors.
46 * BANK 4 and 5 are only available on PXA935, PXA1928
47 * BANK 6 is only available on PXA1928
48 */
49
50 #define GPLR_OFFSET 0x00
51 #define GPDR_OFFSET 0x0C
52 #define GPSR_OFFSET 0x18
53 #define GPCR_OFFSET 0x24
54 #define GRER_OFFSET 0x30
55 #define GFER_OFFSET 0x3C
56 #define GEDR_OFFSET 0x48
57 #define GAFR_OFFSET 0x54
58 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
59
60 #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
61
62 int pxa_last_gpio;
63 static int irq_base;
64
65 struct pxa_gpio_bank {
66 void __iomem *regbase;
67 unsigned long irq_mask;
68 unsigned long irq_edge_rise;
69 unsigned long irq_edge_fall;
70
71 #ifdef CONFIG_PM
72 unsigned long saved_gplr;
73 unsigned long saved_gpdr;
74 unsigned long saved_grer;
75 unsigned long saved_gfer;
76 #endif
77 };
78
79 struct pxa_gpio_chip {
80 struct device *dev;
81 struct gpio_chip chip;
82 struct pxa_gpio_bank *banks;
83 struct irq_domain *irqdomain;
84
85 int irq0;
86 int irq1;
87 int (*set_wake)(unsigned int gpio, unsigned int on);
88 };
89
90 enum pxa_gpio_type {
91 PXA25X_GPIO = 0,
92 PXA26X_GPIO,
93 PXA27X_GPIO,
94 PXA3XX_GPIO,
95 PXA93X_GPIO,
96 MMP_GPIO = 0x10,
97 MMP2_GPIO,
98 PXA1928_GPIO,
99 };
100
101 struct pxa_gpio_id {
102 enum pxa_gpio_type type;
103 int gpio_nums;
104 };
105
106 static DEFINE_SPINLOCK(gpio_lock);
107 static struct pxa_gpio_chip *pxa_gpio_chip;
108 static enum pxa_gpio_type gpio_type;
109
110 static struct pxa_gpio_id pxa25x_id = {
111 .type = PXA25X_GPIO,
112 .gpio_nums = 85,
113 };
114
115 static struct pxa_gpio_id pxa26x_id = {
116 .type = PXA26X_GPIO,
117 .gpio_nums = 90,
118 };
119
120 static struct pxa_gpio_id pxa27x_id = {
121 .type = PXA27X_GPIO,
122 .gpio_nums = 121,
123 };
124
125 static struct pxa_gpio_id pxa3xx_id = {
126 .type = PXA3XX_GPIO,
127 .gpio_nums = 128,
128 };
129
130 static struct pxa_gpio_id pxa93x_id = {
131 .type = PXA93X_GPIO,
132 .gpio_nums = 192,
133 };
134
135 static struct pxa_gpio_id mmp_id = {
136 .type = MMP_GPIO,
137 .gpio_nums = 128,
138 };
139
140 static struct pxa_gpio_id mmp2_id = {
141 .type = MMP2_GPIO,
142 .gpio_nums = 192,
143 };
144
145 static struct pxa_gpio_id pxa1928_id = {
146 .type = PXA1928_GPIO,
147 .gpio_nums = 224,
148 };
149
150 #define for_each_gpio_bank(i, b, pc) \
151 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
152
chip_to_pxachip(struct gpio_chip *c)153 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
154 {
155 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
156
157 return pxa_chip;
158 }
159
gpio_bank_base(struct gpio_chip *c, int gpio)160 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
161 {
162 struct pxa_gpio_chip *p = gpiochip_get_data(c);
163 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
164
165 return bank->regbase;
166 }
167
gpio_to_pxabank(struct gpio_chip *c, unsigned gpio)168 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
169 unsigned gpio)
170 {
171 return chip_to_pxachip(c)->banks + gpio / 32;
172 }
173
gpio_is_pxa_type(int type)174 static inline int gpio_is_pxa_type(int type)
175 {
176 return (type & MMP_GPIO) == 0;
177 }
178
gpio_is_mmp_type(int type)179 static inline int gpio_is_mmp_type(int type)
180 {
181 return (type & MMP_GPIO) != 0;
182 }
183
184 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
185 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
186 */
__gpio_is_inverted(int gpio)187 static inline int __gpio_is_inverted(int gpio)
188 {
189 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
190 return 1;
191 return 0;
192 }
193
194 /*
195 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
196 * function of a GPIO, and GPDRx cannot be altered once configured. It
197 * is attributed as "occupied" here (I know this terminology isn't
198 * accurate, you are welcome to propose a better one :-)
199 */
__gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)200 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
201 {
202 void __iomem *base;
203 unsigned long gafr = 0, gpdr = 0;
204 int ret, af = 0, dir = 0;
205
206 base = gpio_bank_base(&pchip->chip, gpio);
207 gpdr = readl_relaxed(base + GPDR_OFFSET);
208
209 switch (gpio_type) {
210 case PXA25X_GPIO:
211 case PXA26X_GPIO:
212 case PXA27X_GPIO:
213 gafr = readl_relaxed(base + GAFR_OFFSET);
214 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
215 dir = gpdr & GPIO_bit(gpio);
216
217 if (__gpio_is_inverted(gpio))
218 ret = (af != 1) || (dir == 0);
219 else
220 ret = (af != 0) || (dir != 0);
221 break;
222 default:
223 ret = gpdr & GPIO_bit(gpio);
224 break;
225 }
226 return ret;
227 }
228
pxa_irq_to_gpio(int irq)229 int pxa_irq_to_gpio(int irq)
230 {
231 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
232 int irq_gpio0;
233
234 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
235 if (irq_gpio0 > 0)
236 return irq - irq_gpio0;
237
238 return irq_gpio0;
239 }
240
pxa_gpio_has_pinctrl(void)241 static bool pxa_gpio_has_pinctrl(void)
242 {
243 switch (gpio_type) {
244 case PXA3XX_GPIO:
245 case MMP2_GPIO:
246 case MMP_GPIO:
247 return false;
248
249 default:
250 return true;
251 }
252 }
253
pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)254 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
255 {
256 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
257
258 return irq_find_mapping(pchip->irqdomain, offset);
259 }
260
pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)261 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
262 {
263 void __iomem *base = gpio_bank_base(chip, offset);
264 uint32_t value, mask = GPIO_bit(offset);
265 unsigned long flags;
266 int ret;
267
268 if (pxa_gpio_has_pinctrl()) {
269 ret = pinctrl_gpio_direction_input(chip->base + offset);
270 if (ret)
271 return ret;
272 }
273
274 spin_lock_irqsave(&gpio_lock, flags);
275
276 value = readl_relaxed(base + GPDR_OFFSET);
277 if (__gpio_is_inverted(chip->base + offset))
278 value |= mask;
279 else
280 value &= ~mask;
281 writel_relaxed(value, base + GPDR_OFFSET);
282
283 spin_unlock_irqrestore(&gpio_lock, flags);
284 return 0;
285 }
286
pxa_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)287 static int pxa_gpio_direction_output(struct gpio_chip *chip,
288 unsigned offset, int value)
289 {
290 void __iomem *base = gpio_bank_base(chip, offset);
291 uint32_t tmp, mask = GPIO_bit(offset);
292 unsigned long flags;
293 int ret;
294
295 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
296
297 if (pxa_gpio_has_pinctrl()) {
298 ret = pinctrl_gpio_direction_output(chip->base + offset);
299 if (ret)
300 return ret;
301 }
302
303 spin_lock_irqsave(&gpio_lock, flags);
304
305 tmp = readl_relaxed(base + GPDR_OFFSET);
306 if (__gpio_is_inverted(chip->base + offset))
307 tmp &= ~mask;
308 else
309 tmp |= mask;
310 writel_relaxed(tmp, base + GPDR_OFFSET);
311
312 spin_unlock_irqrestore(&gpio_lock, flags);
313 return 0;
314 }
315
pxa_gpio_get(struct gpio_chip *chip, unsigned offset)316 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
317 {
318 void __iomem *base = gpio_bank_base(chip, offset);
319 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
320
321 return !!(gplr & GPIO_bit(offset));
322 }
323
pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)324 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
325 {
326 void __iomem *base = gpio_bank_base(chip, offset);
327
328 writel_relaxed(GPIO_bit(offset),
329 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
330 }
331
332 #ifdef CONFIG_OF_GPIO
pxa_gpio_of_xlate(struct gpio_chip *gc, const struct of_phandle_args *gpiospec, u32 *flags)333 static int pxa_gpio_of_xlate(struct gpio_chip *gc,
334 const struct of_phandle_args *gpiospec,
335 u32 *flags)
336 {
337 if (gpiospec->args[0] > pxa_last_gpio)
338 return -EINVAL;
339
340 if (flags)
341 *flags = gpiospec->args[1];
342
343 return gpiospec->args[0];
344 }
345 #endif
346
pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, struct device_node *np, void __iomem *regbase)347 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
348 struct device_node *np, void __iomem *regbase)
349 {
350 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
351 struct pxa_gpio_bank *bank;
352
353 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
354 GFP_KERNEL);
355 if (!pchip->banks)
356 return -ENOMEM;
357
358 pchip->chip.label = "gpio-pxa";
359 pchip->chip.direction_input = pxa_gpio_direction_input;
360 pchip->chip.direction_output = pxa_gpio_direction_output;
361 pchip->chip.get = pxa_gpio_get;
362 pchip->chip.set = pxa_gpio_set;
363 pchip->chip.to_irq = pxa_gpio_to_irq;
364 pchip->chip.ngpio = ngpio;
365 pchip->chip.request = gpiochip_generic_request;
366 pchip->chip.free = gpiochip_generic_free;
367
368 #ifdef CONFIG_OF_GPIO
369 pchip->chip.of_node = np;
370 pchip->chip.of_xlate = pxa_gpio_of_xlate;
371 pchip->chip.of_gpio_n_cells = 2;
372 #endif
373
374 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
375 bank = pchip->banks + i;
376 bank->regbase = regbase + BANK_OFF(i);
377 }
378
379 return gpiochip_add_data(&pchip->chip, pchip);
380 }
381
382 /* Update only those GRERx and GFERx edge detection register bits if those
383 * bits are set in c->irq_mask
384 */
update_edge_detect(struct pxa_gpio_bank *c)385 static inline void update_edge_detect(struct pxa_gpio_bank *c)
386 {
387 uint32_t grer, gfer;
388
389 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
390 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
391 grer |= c->irq_edge_rise & c->irq_mask;
392 gfer |= c->irq_edge_fall & c->irq_mask;
393 writel_relaxed(grer, c->regbase + GRER_OFFSET);
394 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
395 }
396
pxa_gpio_irq_type(struct irq_data *d, unsigned int type)397 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
398 {
399 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
400 unsigned int gpio = irqd_to_hwirq(d);
401 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
402 unsigned long gpdr, mask = GPIO_bit(gpio);
403
404 if (type == IRQ_TYPE_PROBE) {
405 /* Don't mess with enabled GPIOs using preconfigured edges or
406 * GPIOs set to alternate function or to output during probe
407 */
408 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
409 return 0;
410
411 if (__gpio_is_occupied(pchip, gpio))
412 return 0;
413
414 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
415 }
416
417 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
418
419 if (__gpio_is_inverted(gpio))
420 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
421 else
422 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
423
424 if (type & IRQ_TYPE_EDGE_RISING)
425 c->irq_edge_rise |= mask;
426 else
427 c->irq_edge_rise &= ~mask;
428
429 if (type & IRQ_TYPE_EDGE_FALLING)
430 c->irq_edge_fall |= mask;
431 else
432 c->irq_edge_fall &= ~mask;
433
434 update_edge_detect(c);
435
436 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
437 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
438 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
439 return 0;
440 }
441
pxa_gpio_demux_handler(int in_irq, void *d)442 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
443 {
444 int loop, gpio, n, handled = 0;
445 unsigned long gedr;
446 struct pxa_gpio_chip *pchip = d;
447 struct pxa_gpio_bank *c;
448
449 do {
450 loop = 0;
451 for_each_gpio_bank(gpio, c, pchip) {
452 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
453 gedr = gedr & c->irq_mask;
454 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
455
456 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
457 loop = 1;
458
459 generic_handle_irq(
460 irq_find_mapping(pchip->irqdomain,
461 gpio + n));
462 }
463 }
464 handled += loop;
465 } while (loop);
466
467 return handled ? IRQ_HANDLED : IRQ_NONE;
468 }
469
pxa_gpio_direct_handler(int in_irq, void *d)470 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
471 {
472 struct pxa_gpio_chip *pchip = d;
473
474 if (in_irq == pchip->irq0) {
475 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
476 } else if (in_irq == pchip->irq1) {
477 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
478 } else {
479 pr_err("%s() unknown irq %d\n", __func__, in_irq);
480 return IRQ_NONE;
481 }
482 return IRQ_HANDLED;
483 }
484
pxa_ack_muxed_gpio(struct irq_data *d)485 static void pxa_ack_muxed_gpio(struct irq_data *d)
486 {
487 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
488 unsigned int gpio = irqd_to_hwirq(d);
489 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
490
491 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
492 }
493
pxa_mask_muxed_gpio(struct irq_data *d)494 static void pxa_mask_muxed_gpio(struct irq_data *d)
495 {
496 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
497 unsigned int gpio = irqd_to_hwirq(d);
498 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
499 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
500 uint32_t grer, gfer;
501
502 b->irq_mask &= ~GPIO_bit(gpio);
503
504 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
505 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
506 writel_relaxed(grer, base + GRER_OFFSET);
507 writel_relaxed(gfer, base + GFER_OFFSET);
508 }
509
pxa_gpio_set_wake(struct irq_data *d, unsigned int on)510 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
511 {
512 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
513 unsigned int gpio = irqd_to_hwirq(d);
514
515 if (pchip->set_wake)
516 return pchip->set_wake(gpio, on);
517 else
518 return 0;
519 }
520
pxa_unmask_muxed_gpio(struct irq_data *d)521 static void pxa_unmask_muxed_gpio(struct irq_data *d)
522 {
523 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
524 unsigned int gpio = irqd_to_hwirq(d);
525 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
526
527 c->irq_mask |= GPIO_bit(gpio);
528 update_edge_detect(c);
529 }
530
531 static struct irq_chip pxa_muxed_gpio_chip = {
532 .name = "GPIO",
533 .irq_ack = pxa_ack_muxed_gpio,
534 .irq_mask = pxa_mask_muxed_gpio,
535 .irq_unmask = pxa_unmask_muxed_gpio,
536 .irq_set_type = pxa_gpio_irq_type,
537 .irq_set_wake = pxa_gpio_set_wake,
538 };
539
pxa_gpio_nums(struct platform_device *pdev)540 static int pxa_gpio_nums(struct platform_device *pdev)
541 {
542 const struct platform_device_id *id = platform_get_device_id(pdev);
543 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
544 int count = 0;
545
546 switch (pxa_id->type) {
547 case PXA25X_GPIO:
548 case PXA26X_GPIO:
549 case PXA27X_GPIO:
550 case PXA3XX_GPIO:
551 case PXA93X_GPIO:
552 case MMP_GPIO:
553 case MMP2_GPIO:
554 case PXA1928_GPIO:
555 gpio_type = pxa_id->type;
556 count = pxa_id->gpio_nums - 1;
557 break;
558 default:
559 count = -EINVAL;
560 break;
561 }
562 return count;
563 }
564
pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)565 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
566 irq_hw_number_t hw)
567 {
568 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
569 handle_edge_irq);
570 irq_set_chip_data(irq, d->host_data);
571 irq_set_noprobe(irq);
572 return 0;
573 }
574
575 static const struct irq_domain_ops pxa_irq_domain_ops = {
576 .map = pxa_irq_domain_map,
577 .xlate = irq_domain_xlate_twocell,
578 };
579
580 #ifdef CONFIG_OF
581 static const struct of_device_id pxa_gpio_dt_ids[] = {
582 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
583 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
584 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
585 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
586 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
587 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
588 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
589 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
590 {}
591 };
592
pxa_gpio_probe_dt(struct platform_device *pdev, struct pxa_gpio_chip *pchip)593 static int pxa_gpio_probe_dt(struct platform_device *pdev,
594 struct pxa_gpio_chip *pchip)
595 {
596 int nr_gpios;
597 const struct pxa_gpio_id *gpio_id;
598
599 gpio_id = of_device_get_match_data(&pdev->dev);
600 gpio_type = gpio_id->type;
601
602 nr_gpios = gpio_id->gpio_nums;
603 pxa_last_gpio = nr_gpios - 1;
604
605 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
606 if (irq_base < 0) {
607 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
608 return irq_base;
609 }
610 return irq_base;
611 }
612 #else
613 #define pxa_gpio_probe_dt(pdev, pchip) (-1)
614 #endif
615
pxa_gpio_probe(struct platform_device *pdev)616 static int pxa_gpio_probe(struct platform_device *pdev)
617 {
618 struct pxa_gpio_chip *pchip;
619 struct pxa_gpio_bank *c;
620 struct clk *clk;
621 struct pxa_gpio_platform_data *info;
622 void __iomem *gpio_reg_base;
623 int gpio, ret;
624 int irq0 = 0, irq1 = 0, irq_mux;
625
626 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
627 if (!pchip)
628 return -ENOMEM;
629 pchip->dev = &pdev->dev;
630
631 info = dev_get_platdata(&pdev->dev);
632 if (info) {
633 irq_base = info->irq_base;
634 if (irq_base <= 0)
635 return -EINVAL;
636 pxa_last_gpio = pxa_gpio_nums(pdev);
637 pchip->set_wake = info->gpio_set_wake;
638 } else {
639 irq_base = pxa_gpio_probe_dt(pdev, pchip);
640 if (irq_base < 0)
641 return -EINVAL;
642 }
643
644 if (!pxa_last_gpio)
645 return -EINVAL;
646
647 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
648 pxa_last_gpio + 1, irq_base,
649 0, &pxa_irq_domain_ops, pchip);
650 if (!pchip->irqdomain)
651 return -ENOMEM;
652
653 irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
654 irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
655 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
656 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
657 || (irq_mux <= 0))
658 return -EINVAL;
659
660 pchip->irq0 = irq0;
661 pchip->irq1 = irq1;
662
663 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
664 if (IS_ERR(gpio_reg_base))
665 return PTR_ERR(gpio_reg_base);
666
667 clk = clk_get(&pdev->dev, NULL);
668 if (IS_ERR(clk)) {
669 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
670 PTR_ERR(clk));
671 return PTR_ERR(clk);
672 }
673 ret = clk_prepare_enable(clk);
674 if (ret) {
675 clk_put(clk);
676 return ret;
677 }
678
679 /* Initialize GPIO chips */
680 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
681 gpio_reg_base);
682 if (ret) {
683 clk_put(clk);
684 return ret;
685 }
686
687 /* clear all GPIO edge detects */
688 for_each_gpio_bank(gpio, c, pchip) {
689 writel_relaxed(0, c->regbase + GFER_OFFSET);
690 writel_relaxed(0, c->regbase + GRER_OFFSET);
691 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
692 /* unmask GPIO edge detect for AP side */
693 if (gpio_is_mmp_type(gpio_type))
694 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
695 }
696
697 if (irq0 > 0) {
698 ret = devm_request_irq(&pdev->dev,
699 irq0, pxa_gpio_direct_handler, 0,
700 "gpio-0", pchip);
701 if (ret)
702 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
703 ret);
704 }
705 if (irq1 > 0) {
706 ret = devm_request_irq(&pdev->dev,
707 irq1, pxa_gpio_direct_handler, 0,
708 "gpio-1", pchip);
709 if (ret)
710 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
711 ret);
712 }
713 ret = devm_request_irq(&pdev->dev,
714 irq_mux, pxa_gpio_demux_handler, 0,
715 "gpio-mux", pchip);
716 if (ret)
717 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
718 ret);
719
720 pxa_gpio_chip = pchip;
721
722 return 0;
723 }
724
725 static const struct platform_device_id gpio_id_table[] = {
726 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
727 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
728 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
729 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
730 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
731 { "mmp-gpio", (unsigned long)&mmp_id },
732 { "mmp2-gpio", (unsigned long)&mmp2_id },
733 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
734 { },
735 };
736
737 static struct platform_driver pxa_gpio_driver = {
738 .probe = pxa_gpio_probe,
739 .driver = {
740 .name = "pxa-gpio",
741 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
742 },
743 .id_table = gpio_id_table,
744 };
745
pxa_gpio_legacy_init(void)746 static int __init pxa_gpio_legacy_init(void)
747 {
748 if (of_have_populated_dt())
749 return 0;
750
751 return platform_driver_register(&pxa_gpio_driver);
752 }
753 postcore_initcall(pxa_gpio_legacy_init);
754
pxa_gpio_dt_init(void)755 static int __init pxa_gpio_dt_init(void)
756 {
757 if (of_have_populated_dt())
758 return platform_driver_register(&pxa_gpio_driver);
759
760 return 0;
761 }
762 device_initcall(pxa_gpio_dt_init);
763
764 #ifdef CONFIG_PM
pxa_gpio_suspend(void)765 static int pxa_gpio_suspend(void)
766 {
767 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
768 struct pxa_gpio_bank *c;
769 int gpio;
770
771 if (!pchip)
772 return 0;
773
774 for_each_gpio_bank(gpio, c, pchip) {
775 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
776 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
777 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
778 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
779
780 /* Clear GPIO transition detect bits */
781 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
782 }
783 return 0;
784 }
785
pxa_gpio_resume(void)786 static void pxa_gpio_resume(void)
787 {
788 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
789 struct pxa_gpio_bank *c;
790 int gpio;
791
792 if (!pchip)
793 return;
794
795 for_each_gpio_bank(gpio, c, pchip) {
796 /* restore level with set/clear */
797 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
798 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
799
800 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
801 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
802 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
803 }
804 }
805 #else
806 #define pxa_gpio_suspend NULL
807 #define pxa_gpio_resume NULL
808 #endif
809
810 static struct syscore_ops pxa_gpio_syscore_ops = {
811 .suspend = pxa_gpio_suspend,
812 .resume = pxa_gpio_resume,
813 };
814
pxa_gpio_sysinit(void)815 static int __init pxa_gpio_sysinit(void)
816 {
817 register_syscore_ops(&pxa_gpio_syscore_ops);
818 return 0;
819 }
820 postcore_initcall(pxa_gpio_sysinit);
821