1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GHES/EDAC Linux driver
4 *
5 * Copyright (c) 2013 by Mauro Carvalho Chehab
6 *
7 * Red Hat Inc. https://www.redhat.com
8 */
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <acpi/ghes.h>
13 #include <linux/edac.h>
14 #include <linux/dmi.h>
15 #include "edac_module.h"
16 #include <ras/ras_event.h>
17
18 struct ghes_pvt {
19 struct mem_ctl_info *mci;
20
21 /* Buffers for the error handling routine */
22 char other_detail[400];
23 char msg[80];
24 };
25
26 static refcount_t ghes_refcount = REFCOUNT_INIT(0);
27
28 /*
29 * Access to ghes_pvt must be protected by ghes_lock. The spinlock
30 * also provides the necessary (implicit) memory barrier for the SMP
31 * case to make the pointer visible on another CPU.
32 */
33 static struct ghes_pvt *ghes_pvt;
34
35 /*
36 * This driver's representation of the system hardware, as collected
37 * from DMI.
38 */
39 struct ghes_hw_desc {
40 int num_dimms;
41 struct dimm_info *dimms;
42 } ghes_hw;
43
44 /* GHES registration mutex */
45 static DEFINE_MUTEX(ghes_reg_mutex);
46
47 /*
48 * Sync with other, potentially concurrent callers of
49 * ghes_edac_report_mem_error(). We don't know what the
50 * "inventive" firmware would do.
51 */
52 static DEFINE_SPINLOCK(ghes_lock);
53
54 /* "ghes_edac.force_load=1" skips the platform check */
55 static bool __read_mostly force_load;
56 module_param(force_load, bool, 0);
57
58 static bool system_scanned;
59
60 /* Memory Device - Type 17 of SMBIOS spec */
61 struct memdev_dmi_entry {
62 u8 type;
63 u8 length;
64 u16 handle;
65 u16 phys_mem_array_handle;
66 u16 mem_err_info_handle;
67 u16 total_width;
68 u16 data_width;
69 u16 size;
70 u8 form_factor;
71 u8 device_set;
72 u8 device_locator;
73 u8 bank_locator;
74 u8 memory_type;
75 u16 type_detail;
76 u16 speed;
77 u8 manufacturer;
78 u8 serial_number;
79 u8 asset_tag;
80 u8 part_number;
81 u8 attributes;
82 u32 extended_size;
83 u16 conf_mem_clk_speed;
84 } __attribute__((__packed__));
85
find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)86 static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
87 {
88 struct dimm_info *dimm;
89
90 mci_for_each_dimm(mci, dimm) {
91 if (dimm->smbios_handle == handle)
92 return dimm;
93 }
94
95 return NULL;
96 }
97
dimm_setup_label(struct dimm_info *dimm, u16 handle)98 static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
99 {
100 const char *bank = NULL, *device = NULL;
101
102 dmi_memdev_name(handle, &bank, &device);
103
104 /*
105 * Set to a NULL string when both bank and device are zero. In this case,
106 * the label assigned by default will be preserved.
107 */
108 snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
109 (bank && *bank) ? bank : "",
110 (bank && *bank && device && *device) ? " " : "",
111 (device && *device) ? device : "");
112 }
113
assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)114 static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
115 {
116 u16 rdr_mask = BIT(7) | BIT(13);
117
118 if (entry->size == 0xffff) {
119 pr_info("Can't get DIMM%i size\n", dimm->idx);
120 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
121 } else if (entry->size == 0x7fff) {
122 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
123 } else {
124 if (entry->size & BIT(15))
125 dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
126 else
127 dimm->nr_pages = MiB_TO_PAGES(entry->size);
128 }
129
130 switch (entry->memory_type) {
131 case 0x12:
132 if (entry->type_detail & BIT(13))
133 dimm->mtype = MEM_RDDR;
134 else
135 dimm->mtype = MEM_DDR;
136 break;
137 case 0x13:
138 if (entry->type_detail & BIT(13))
139 dimm->mtype = MEM_RDDR2;
140 else
141 dimm->mtype = MEM_DDR2;
142 break;
143 case 0x14:
144 dimm->mtype = MEM_FB_DDR2;
145 break;
146 case 0x18:
147 if (entry->type_detail & BIT(12))
148 dimm->mtype = MEM_NVDIMM;
149 else if (entry->type_detail & BIT(13))
150 dimm->mtype = MEM_RDDR3;
151 else
152 dimm->mtype = MEM_DDR3;
153 break;
154 case 0x1a:
155 if (entry->type_detail & BIT(12))
156 dimm->mtype = MEM_NVDIMM;
157 else if (entry->type_detail & BIT(13))
158 dimm->mtype = MEM_RDDR4;
159 else
160 dimm->mtype = MEM_DDR4;
161 break;
162 default:
163 if (entry->type_detail & BIT(6))
164 dimm->mtype = MEM_RMBS;
165 else if ((entry->type_detail & rdr_mask) == rdr_mask)
166 dimm->mtype = MEM_RDR;
167 else if (entry->type_detail & BIT(7))
168 dimm->mtype = MEM_SDR;
169 else if (entry->type_detail & BIT(9))
170 dimm->mtype = MEM_EDO;
171 else
172 dimm->mtype = MEM_UNKNOWN;
173 }
174
175 /*
176 * Actually, we can only detect if the memory has bits for
177 * checksum or not
178 */
179 if (entry->total_width == entry->data_width)
180 dimm->edac_mode = EDAC_NONE;
181 else
182 dimm->edac_mode = EDAC_SECDED;
183
184 dimm->dtype = DEV_UNKNOWN;
185 dimm->grain = 128; /* Likely, worse case */
186
187 dimm_setup_label(dimm, entry->handle);
188
189 if (dimm->nr_pages) {
190 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
191 dimm->idx, edac_mem_types[dimm->mtype],
192 PAGES_TO_MiB(dimm->nr_pages),
193 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
194 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
195 entry->memory_type, entry->type_detail,
196 entry->total_width, entry->data_width);
197 }
198
199 dimm->smbios_handle = entry->handle;
200 }
201
enumerate_dimms(const struct dmi_header *dh, void *arg)202 static void enumerate_dimms(const struct dmi_header *dh, void *arg)
203 {
204 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
205 struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
206 struct dimm_info *d;
207
208 if (dh->type != DMI_ENTRY_MEM_DEVICE)
209 return;
210
211 /* Enlarge the array with additional 16 */
212 if (!hw->num_dimms || !(hw->num_dimms % 16)) {
213 struct dimm_info *new;
214
215 new = krealloc(hw->dimms, (hw->num_dimms + 16) * sizeof(struct dimm_info),
216 GFP_KERNEL);
217 if (!new) {
218 WARN_ON_ONCE(1);
219 return;
220 }
221
222 hw->dimms = new;
223 }
224
225 d = &hw->dimms[hw->num_dimms];
226 d->idx = hw->num_dimms;
227
228 assign_dmi_dimm_info(d, entry);
229
230 hw->num_dimms++;
231 }
232
ghes_scan_system(void)233 static void ghes_scan_system(void)
234 {
235 if (system_scanned)
236 return;
237
238 dmi_walk(enumerate_dimms, &ghes_hw);
239
240 system_scanned = true;
241 }
242
ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)243 void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
244 {
245 struct edac_raw_error_desc *e;
246 struct mem_ctl_info *mci;
247 struct ghes_pvt *pvt;
248 unsigned long flags;
249 char *p;
250
251 /*
252 * We can do the locking below because GHES defers error processing
253 * from NMI to IRQ context. Whenever that changes, we'd at least
254 * know.
255 */
256 if (WARN_ON_ONCE(in_nmi()))
257 return;
258
259 spin_lock_irqsave(&ghes_lock, flags);
260
261 pvt = ghes_pvt;
262 if (!pvt)
263 goto unlock;
264
265 mci = pvt->mci;
266 e = &mci->error_desc;
267
268 /* Cleans the error report buffer */
269 memset(e, 0, sizeof (*e));
270 e->error_count = 1;
271 e->grain = 1;
272 e->msg = pvt->msg;
273 e->other_detail = pvt->other_detail;
274 e->top_layer = -1;
275 e->mid_layer = -1;
276 e->low_layer = -1;
277 *pvt->other_detail = '\0';
278 *pvt->msg = '\0';
279
280 switch (sev) {
281 case GHES_SEV_CORRECTED:
282 e->type = HW_EVENT_ERR_CORRECTED;
283 break;
284 case GHES_SEV_RECOVERABLE:
285 e->type = HW_EVENT_ERR_UNCORRECTED;
286 break;
287 case GHES_SEV_PANIC:
288 e->type = HW_EVENT_ERR_FATAL;
289 break;
290 default:
291 case GHES_SEV_NO:
292 e->type = HW_EVENT_ERR_INFO;
293 }
294
295 edac_dbg(1, "error validation_bits: 0x%08llx\n",
296 (long long)mem_err->validation_bits);
297
298 /* Error type, mapped on e->msg */
299 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
300 p = pvt->msg;
301 switch (mem_err->error_type) {
302 case 0:
303 p += sprintf(p, "Unknown");
304 break;
305 case 1:
306 p += sprintf(p, "No error");
307 break;
308 case 2:
309 p += sprintf(p, "Single-bit ECC");
310 break;
311 case 3:
312 p += sprintf(p, "Multi-bit ECC");
313 break;
314 case 4:
315 p += sprintf(p, "Single-symbol ChipKill ECC");
316 break;
317 case 5:
318 p += sprintf(p, "Multi-symbol ChipKill ECC");
319 break;
320 case 6:
321 p += sprintf(p, "Master abort");
322 break;
323 case 7:
324 p += sprintf(p, "Target abort");
325 break;
326 case 8:
327 p += sprintf(p, "Parity Error");
328 break;
329 case 9:
330 p += sprintf(p, "Watchdog timeout");
331 break;
332 case 10:
333 p += sprintf(p, "Invalid address");
334 break;
335 case 11:
336 p += sprintf(p, "Mirror Broken");
337 break;
338 case 12:
339 p += sprintf(p, "Memory Sparing");
340 break;
341 case 13:
342 p += sprintf(p, "Scrub corrected error");
343 break;
344 case 14:
345 p += sprintf(p, "Scrub uncorrected error");
346 break;
347 case 15:
348 p += sprintf(p, "Physical Memory Map-out event");
349 break;
350 default:
351 p += sprintf(p, "reserved error (%d)",
352 mem_err->error_type);
353 }
354 } else {
355 strcpy(pvt->msg, "unknown error");
356 }
357
358 /* Error address */
359 if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
360 e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
361 e->offset_in_page = offset_in_page(mem_err->physical_addr);
362 }
363
364 /* Error grain */
365 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
366 e->grain = ~mem_err->physical_addr_mask + 1;
367
368 /* Memory error location, mapped on e->location */
369 p = e->location;
370 if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
371 p += sprintf(p, "node:%d ", mem_err->node);
372 if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
373 p += sprintf(p, "card:%d ", mem_err->card);
374 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
375 p += sprintf(p, "module:%d ", mem_err->module);
376 if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
377 p += sprintf(p, "rank:%d ", mem_err->rank);
378 if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
379 p += sprintf(p, "bank:%d ", mem_err->bank);
380 if (mem_err->validation_bits & CPER_MEM_VALID_BANK_GROUP)
381 p += sprintf(p, "bank_group:%d ",
382 mem_err->bank >> CPER_MEM_BANK_GROUP_SHIFT);
383 if (mem_err->validation_bits & CPER_MEM_VALID_BANK_ADDRESS)
384 p += sprintf(p, "bank_address:%d ",
385 mem_err->bank & CPER_MEM_BANK_ADDRESS_MASK);
386 if (mem_err->validation_bits & (CPER_MEM_VALID_ROW | CPER_MEM_VALID_ROW_EXT)) {
387 u32 row = mem_err->row;
388
389 row |= cper_get_mem_extension(mem_err->validation_bits, mem_err->extended);
390 p += sprintf(p, "row:%d ", row);
391 }
392 if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
393 p += sprintf(p, "col:%d ", mem_err->column);
394 if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
395 p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
396 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
397 const char *bank = NULL, *device = NULL;
398 struct dimm_info *dimm;
399
400 dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
401 if (bank != NULL && device != NULL)
402 p += sprintf(p, "DIMM location:%s %s ", bank, device);
403 else
404 p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
405 mem_err->mem_dev_handle);
406
407 dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
408 if (dimm) {
409 e->top_layer = dimm->idx;
410 strcpy(e->label, dimm->label);
411 }
412 }
413 if (mem_err->validation_bits & CPER_MEM_VALID_CHIP_ID)
414 p += sprintf(p, "chipID: %d ",
415 mem_err->extended >> CPER_MEM_CHIP_ID_SHIFT);
416 if (p > e->location)
417 *(p - 1) = '\0';
418
419 if (!*e->label)
420 strcpy(e->label, "unknown memory");
421
422 /* All other fields are mapped on e->other_detail */
423 p = pvt->other_detail;
424 p += snprintf(p, sizeof(pvt->other_detail),
425 "APEI location: %s ", e->location);
426 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
427 u64 status = mem_err->error_status;
428
429 p += sprintf(p, "status(0x%016llx): ", (long long)status);
430 switch ((status >> 8) & 0xff) {
431 case 1:
432 p += sprintf(p, "Error detected internal to the component ");
433 break;
434 case 16:
435 p += sprintf(p, "Error detected in the bus ");
436 break;
437 case 4:
438 p += sprintf(p, "Storage error in DRAM memory ");
439 break;
440 case 5:
441 p += sprintf(p, "Storage error in TLB ");
442 break;
443 case 6:
444 p += sprintf(p, "Storage error in cache ");
445 break;
446 case 7:
447 p += sprintf(p, "Error in one or more functional units ");
448 break;
449 case 8:
450 p += sprintf(p, "component failed self test ");
451 break;
452 case 9:
453 p += sprintf(p, "Overflow or undervalue of internal queue ");
454 break;
455 case 17:
456 p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
457 break;
458 case 18:
459 p += sprintf(p, "Improper access error ");
460 break;
461 case 19:
462 p += sprintf(p, "Access to a memory address which is not mapped to any component ");
463 break;
464 case 20:
465 p += sprintf(p, "Loss of Lockstep ");
466 break;
467 case 21:
468 p += sprintf(p, "Response not associated with a request ");
469 break;
470 case 22:
471 p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
472 break;
473 case 23:
474 p += sprintf(p, "Detection of a PATH_ERROR ");
475 break;
476 case 25:
477 p += sprintf(p, "Bus operation timeout ");
478 break;
479 case 26:
480 p += sprintf(p, "A read was issued to data that has been poisoned ");
481 break;
482 default:
483 p += sprintf(p, "reserved ");
484 break;
485 }
486 }
487 if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
488 p += sprintf(p, "requestorID: 0x%016llx ",
489 (long long)mem_err->requestor_id);
490 if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
491 p += sprintf(p, "responderID: 0x%016llx ",
492 (long long)mem_err->responder_id);
493 if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
494 p += sprintf(p, "targetID: 0x%016llx ",
495 (long long)mem_err->responder_id);
496 if (p > pvt->other_detail)
497 *(p - 1) = '\0';
498
499 edac_raw_mc_handle_error(e);
500
501 unlock:
502 spin_unlock_irqrestore(&ghes_lock, flags);
503 }
504
505 /*
506 * Known systems that are safe to enable this module.
507 */
508 static struct acpi_platform_list plat_list[] = {
509 {"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
510 { } /* End */
511 };
512
ghes_edac_register(struct ghes *ghes, struct device *dev)513 int ghes_edac_register(struct ghes *ghes, struct device *dev)
514 {
515 bool fake = false;
516 struct mem_ctl_info *mci;
517 struct ghes_pvt *pvt;
518 struct edac_mc_layer layers[1];
519 unsigned long flags;
520 int idx = -1;
521 int rc = 0;
522
523 if (IS_ENABLED(CONFIG_X86)) {
524 /* Check if safe to enable on this system */
525 idx = acpi_match_platform_list(plat_list);
526 if (!force_load && idx < 0)
527 return -ENODEV;
528 } else {
529 force_load = true;
530 idx = 0;
531 }
532
533 /* finish another registration/unregistration instance first */
534 mutex_lock(&ghes_reg_mutex);
535
536 /*
537 * We have only one logical memory controller to which all DIMMs belong.
538 */
539 if (refcount_inc_not_zero(&ghes_refcount))
540 goto unlock;
541
542 ghes_scan_system();
543
544 /* Check if we've got a bogus BIOS */
545 if (!ghes_hw.num_dimms) {
546 fake = true;
547 ghes_hw.num_dimms = 1;
548 }
549
550 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
551 layers[0].size = ghes_hw.num_dimms;
552 layers[0].is_virt_csrow = true;
553
554 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
555 if (!mci) {
556 pr_info("Can't allocate memory for EDAC data\n");
557 rc = -ENOMEM;
558 goto unlock;
559 }
560
561 pvt = mci->pvt_info;
562 pvt->mci = mci;
563
564 mci->pdev = dev;
565 mci->mtype_cap = MEM_FLAG_EMPTY;
566 mci->edac_ctl_cap = EDAC_FLAG_NONE;
567 mci->edac_cap = EDAC_FLAG_NONE;
568 mci->mod_name = "ghes_edac.c";
569 mci->ctl_name = "ghes_edac";
570 mci->dev_name = "ghes";
571
572 if (fake) {
573 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
574 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
575 pr_info("work on such system. Use this driver with caution\n");
576 } else if (idx < 0) {
577 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
578 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
579 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
580 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
581 pr_info("to correct its BIOS.\n");
582 pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
583 }
584
585 if (!fake) {
586 struct dimm_info *src, *dst;
587 int i = 0;
588
589 mci_for_each_dimm(mci, dst) {
590 src = &ghes_hw.dimms[i];
591
592 dst->idx = src->idx;
593 dst->smbios_handle = src->smbios_handle;
594 dst->nr_pages = src->nr_pages;
595 dst->mtype = src->mtype;
596 dst->edac_mode = src->edac_mode;
597 dst->dtype = src->dtype;
598 dst->grain = src->grain;
599
600 /*
601 * If no src->label, preserve default label assigned
602 * from EDAC core.
603 */
604 if (strlen(src->label))
605 memcpy(dst->label, src->label, sizeof(src->label));
606
607 i++;
608 }
609
610 } else {
611 struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
612
613 dimm->nr_pages = 1;
614 dimm->grain = 128;
615 dimm->mtype = MEM_UNKNOWN;
616 dimm->dtype = DEV_UNKNOWN;
617 dimm->edac_mode = EDAC_SECDED;
618 }
619
620 rc = edac_mc_add_mc(mci);
621 if (rc < 0) {
622 pr_info("Can't register with the EDAC core\n");
623 edac_mc_free(mci);
624 rc = -ENODEV;
625 goto unlock;
626 }
627
628 spin_lock_irqsave(&ghes_lock, flags);
629 ghes_pvt = pvt;
630 spin_unlock_irqrestore(&ghes_lock, flags);
631
632 /* only set on success */
633 refcount_set(&ghes_refcount, 1);
634
635 unlock:
636
637 /* Not needed anymore */
638 kfree(ghes_hw.dimms);
639 ghes_hw.dimms = NULL;
640
641 mutex_unlock(&ghes_reg_mutex);
642
643 return rc;
644 }
645
ghes_edac_unregister(struct ghes *ghes)646 void ghes_edac_unregister(struct ghes *ghes)
647 {
648 struct mem_ctl_info *mci;
649 unsigned long flags;
650
651 if (!force_load)
652 return;
653
654 mutex_lock(&ghes_reg_mutex);
655
656 system_scanned = false;
657 memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
658
659 if (!refcount_dec_and_test(&ghes_refcount))
660 goto unlock;
661
662 /*
663 * Wait for the irq handler being finished.
664 */
665 spin_lock_irqsave(&ghes_lock, flags);
666 mci = ghes_pvt ? ghes_pvt->mci : NULL;
667 ghes_pvt = NULL;
668 spin_unlock_irqrestore(&ghes_lock, flags);
669
670 if (!mci)
671 goto unlock;
672
673 mci = edac_mc_del_mc(mci->pdev);
674 if (mci)
675 edac_mc_free(mci);
676
677 unlock:
678 mutex_unlock(&ghes_reg_mutex);
679 }
680