1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #ifndef __HISI_SEC_V2_CRYPTO_H 5 #define __HISI_SEC_V2_CRYPTO_H 6 7 #define SEC_IV_SIZE 24 8 #define SEC_MAX_KEY_SIZE 64 9 #define SEC_MAX_AKEY_SIZE 128 10 #define SEC_COMM_SCENE 0 11 12 enum sec_calg { 13 SEC_CALG_3DES = 0x1, 14 SEC_CALG_AES = 0x2, 15 SEC_CALG_SM4 = 0x3, 16 }; 17 18 enum sec_hash_alg { 19 SEC_A_HMAC_SHA1 = 0x10, 20 SEC_A_HMAC_SHA256 = 0x11, 21 SEC_A_HMAC_SHA512 = 0x15, 22 }; 23 24 enum sec_mac_len { 25 SEC_HMAC_SHA1_MAC = 20, 26 SEC_HMAC_SHA256_MAC = 32, 27 SEC_HMAC_SHA512_MAC = 64, 28 }; 29 30 enum sec_cmode { 31 SEC_CMODE_ECB = 0x0, 32 SEC_CMODE_CBC = 0x1, 33 SEC_CMODE_CTR = 0x4, 34 SEC_CMODE_XTS = 0x7, 35 }; 36 37 enum sec_ckey_type { 38 SEC_CKEY_128BIT = 0x0, 39 SEC_CKEY_192BIT = 0x1, 40 SEC_CKEY_256BIT = 0x2, 41 SEC_CKEY_3DES_3KEY = 0x1, 42 SEC_CKEY_3DES_2KEY = 0x3, 43 }; 44 45 enum sec_bd_type { 46 SEC_BD_TYPE1 = 0x1, 47 SEC_BD_TYPE2 = 0x2, 48 }; 49 50 enum sec_auth { 51 SEC_NO_AUTH = 0x0, 52 SEC_AUTH_TYPE1 = 0x1, 53 SEC_AUTH_TYPE2 = 0x2, 54 }; 55 56 enum sec_cipher_dir { 57 SEC_CIPHER_ENC = 0x1, 58 SEC_CIPHER_DEC = 0x2, 59 }; 60 61 enum sec_addr_type { 62 SEC_PBUF = 0x0, 63 SEC_SGL = 0x1, 64 SEC_PRP = 0x2, 65 }; 66 67 struct sec_sqe_type2 { 68 /* 69 * mac_len: 0~4 bits 70 * a_key_len: 5~10 bits 71 * a_alg: 11~16 bits 72 */ 73 __le32 mac_key_alg; 74 75 /* 76 * c_icv_len: 0~5 bits 77 * c_width: 6~8 bits 78 * c_key_len: 9~11 bits 79 * c_mode: 12~15 bits 80 */ 81 __le16 icvw_kmode; 82 83 /* c_alg: 0~3 bits */ 84 __u8 c_alg; 85 __u8 rsvd4; 86 87 /* 88 * a_len: 0~23 bits 89 * iv_offset_l: 24~31 bits 90 */ 91 __le32 alen_ivllen; 92 93 /* 94 * c_len: 0~23 bits 95 * iv_offset_h: 24~31 bits 96 */ 97 __le32 clen_ivhlen; 98 99 __le16 auth_src_offset; 100 __le16 cipher_src_offset; 101 __le16 cs_ip_header_offset; 102 __le16 cs_udp_header_offset; 103 __le16 pass_word_len; 104 __le16 dk_len; 105 __u8 salt3; 106 __u8 salt2; 107 __u8 salt1; 108 __u8 salt0; 109 110 __le16 tag; 111 __le16 rsvd5; 112 113 /* 114 * c_pad_type: 0~3 bits 115 * c_pad_len: 4~11 bits 116 * c_pad_data_type: 12~15 bits 117 */ 118 __le16 cph_pad; 119 120 /* c_pad_len_field: 0~1 bits */ 121 __le16 c_pad_len_field; 122 123 __le64 long_a_data_len; 124 __le64 a_ivin_addr; 125 __le64 a_key_addr; 126 __le64 mac_addr; 127 __le64 c_ivin_addr; 128 __le64 c_key_addr; 129 130 __le64 data_src_addr; 131 __le64 data_dst_addr; 132 133 /* 134 * done: 0 bit 135 * icv: 1~3 bits 136 * csc: 4~6 bits 137 * flag: 7-10 bits 138 * dif_check: 11~13 bits 139 */ 140 __le16 done_flag; 141 142 __u8 error_type; 143 __u8 warning_type; 144 __u8 mac_i3; 145 __u8 mac_i2; 146 __u8 mac_i1; 147 __u8 mac_i0; 148 __le16 check_sum_i; 149 __u8 tls_pad_len_i; 150 __u8 rsvd12; 151 __le32 counter; 152 }; 153 154 struct sec_sqe { 155 /* 156 * type: 0~3 bits 157 * cipher: 4~5 bits 158 * auth: 6~7 bit s 159 */ 160 __u8 type_cipher_auth; 161 162 /* 163 * seq: 0 bit 164 * de: 1~2 bits 165 * scene: 3~6 bits 166 * src_addr_type: ~7 bit, with sdm_addr_type 0-1 bits 167 */ 168 __u8 sds_sa_type; 169 170 /* 171 * src_addr_type: 0~1 bits, not used now, 172 * if support PRP, set this field, or set zero. 173 * dst_addr_type: 2~4 bits 174 * mac_addr_type: 5~7 bits 175 */ 176 __u8 sdm_addr_type; 177 __u8 rsvd0; 178 179 /* 180 * nonce_len(type2): 0~3 bits 181 * huk(type2): 4 bit 182 * key_s(type2): 5 bit 183 * ci_gen: 6~7 bits 184 */ 185 __u8 huk_key_ci; 186 187 /* 188 * ai_gen: 0~1 bits 189 * a_pad(type2): 2~3 bits 190 * c_s(type2): 4~5 bits 191 */ 192 __u8 ai_apd_cs; 193 194 /* 195 * rhf(type2): 0 bit 196 * c_key_type: 1~2 bits 197 * a_key_type: 3~4 bits 198 * write_frame_len(type2): 5~7 bits 199 */ 200 __u8 rca_key_frm; 201 202 /* 203 * cal_iv_addr_en(type2): 0 bit 204 * tls_up(type2): 1 bit 205 * inveld: 7 bit 206 */ 207 __u8 iv_tls_ld; 208 209 /* Just using type2 BD now */ 210 struct sec_sqe_type2 type2; 211 }; 212 213 int sec_register_to_crypto(void); 214 void sec_unregister_from_crypto(void); 215 #endif 216