1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Zynq UltraScale+ MPSoC PLL driver
4 *
5 * Copyright (C) 2016-2018 Xilinx
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/slab.h>
11 #include "clk-zynqmp.h"
12
13 /**
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
17 * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF
18 */
19 struct zynqmp_pll {
20 struct clk_hw hw;
21 u32 clk_id;
22 bool set_pll_mode;
23 };
24
25 #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
26
27 #define PLL_FBDIV_MIN 25
28 #define PLL_FBDIV_MAX 125
29
30 #define PS_PLL_VCO_MIN 1500000000
31 #define PS_PLL_VCO_MAX 3000000000UL
32
33 enum pll_mode {
34 PLL_MODE_INT,
35 PLL_MODE_FRAC,
36 };
37
38 #define FRAC_OFFSET 0x8
39 #define PLLFCFG_FRAC_EN BIT(31)
40 #define FRAC_DIV BIT(16) /* 2^16 */
41
42 /**
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
45 *
46 * Return: Mode of PLL
47 */
zynqmp_pll_get_mode(struct clk_hw *hw)48 static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
49 {
50 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
51 u32 clk_id = clk->clk_id;
52 const char *clk_name = clk_hw_get_name(hw);
53 u32 ret_payload[PAYLOAD_ARG_CNT];
54 int ret;
55
56 ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload);
57 if (ret)
58 pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
59 __func__, clk_name, ret);
60
61 return ret_payload[1];
62 }
63
64 /**
65 * zynqmp_pll_set_mode() - Set the PLL mode
66 * @hw: Handle between common and hardware-specific interfaces
67 * @on: Flag to determine the mode
68 */
zynqmp_pll_set_mode(struct clk_hw *hw, bool on)69 static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
70 {
71 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
72 u32 clk_id = clk->clk_id;
73 const char *clk_name = clk_hw_get_name(hw);
74 int ret;
75 u32 mode;
76
77 if (on)
78 mode = PLL_MODE_FRAC;
79 else
80 mode = PLL_MODE_INT;
81
82 ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);
83 if (ret)
84 pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
85 __func__, clk_name, ret);
86 else
87 clk->set_pll_mode = true;
88 }
89
90 /**
91 * zynqmp_pll_round_rate() - Round a clock frequency
92 * @hw: Handle between common and hardware-specific interfaces
93 * @rate: Desired clock frequency
94 * @prate: Clock frequency of parent clock
95 *
96 * Return: Frequency closest to @rate the hardware can generate
97 */
zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)98 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
99 unsigned long *prate)
100 {
101 u32 fbdiv;
102 u32 mult, div;
103
104 /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
105 if (rate > PS_PLL_VCO_MAX) {
106 div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
107 rate = rate / div;
108 }
109 if (rate < PS_PLL_VCO_MIN) {
110 mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
111 rate = rate * mult;
112 }
113
114 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
115 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
116 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
117 rate = *prate * fbdiv;
118 }
119
120 return rate;
121 }
122
123 /**
124 * zynqmp_pll_recalc_rate() - Recalculate clock frequency
125 * @hw: Handle between common and hardware-specific interfaces
126 * @parent_rate: Clock frequency of parent clock
127 *
128 * Return: Current clock frequency
129 */
zynqmp_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)130 static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
131 unsigned long parent_rate)
132 {
133 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
134 u32 clk_id = clk->clk_id;
135 const char *clk_name = clk_hw_get_name(hw);
136 u32 fbdiv, data;
137 unsigned long rate, frac;
138 u32 ret_payload[PAYLOAD_ARG_CNT];
139 int ret;
140
141 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
142 if (ret)
143 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
144 __func__, clk_name, ret);
145
146 rate = parent_rate * fbdiv;
147 if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
148 zynqmp_pm_get_pll_frac_data(clk_id, ret_payload);
149 data = ret_payload[1];
150 frac = (parent_rate * data) / FRAC_DIV;
151 rate = rate + frac;
152 }
153
154 return rate;
155 }
156
157 /**
158 * zynqmp_pll_set_rate() - Set rate of PLL
159 * @hw: Handle between common and hardware-specific interfaces
160 * @rate: Frequency of clock to be set
161 * @parent_rate: Clock frequency of parent clock
162 *
163 * Set PLL divider to set desired rate.
164 *
165 * Returns: rate which is set on success else error code
166 */
zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)167 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
168 unsigned long parent_rate)
169 {
170 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
171 u32 clk_id = clk->clk_id;
172 const char *clk_name = clk_hw_get_name(hw);
173 u32 fbdiv;
174 long rate_div, frac, m, f;
175 int ret;
176
177 rate_div = (rate * FRAC_DIV) / parent_rate;
178 f = rate_div % FRAC_DIV;
179 zynqmp_pll_set_mode(hw, !!f);
180
181 if (f) {
182 m = rate_div / FRAC_DIV;
183 m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
184 rate = parent_rate * m;
185 frac = (parent_rate * f) / FRAC_DIV;
186
187 ret = zynqmp_pm_clock_setdivider(clk_id, m);
188 if (ret == -EUSERS)
189 WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
190 clk_name);
191 else if (ret)
192 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
193 __func__, clk_name, ret);
194 zynqmp_pm_set_pll_frac_data(clk_id, f);
195
196 return rate + frac;
197 }
198
199 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
200 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
201 ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
202 if (ret)
203 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
204 __func__, clk_name, ret);
205
206 return parent_rate * fbdiv;
207 }
208
209 /**
210 * zynqmp_pll_is_enabled() - Check if a clock is enabled
211 * @hw: Handle between common and hardware-specific interfaces
212 *
213 * Return: 1 if the clock is enabled, 0 otherwise
214 */
zynqmp_pll_is_enabled(struct clk_hw *hw)215 static int zynqmp_pll_is_enabled(struct clk_hw *hw)
216 {
217 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
218 const char *clk_name = clk_hw_get_name(hw);
219 u32 clk_id = clk->clk_id;
220 unsigned int state;
221 int ret;
222
223 ret = zynqmp_pm_clock_getstate(clk_id, &state);
224 if (ret) {
225 pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
226 __func__, clk_name, ret);
227 return -EIO;
228 }
229
230 return state ? 1 : 0;
231 }
232
233 /**
234 * zynqmp_pll_enable() - Enable clock
235 * @hw: Handle between common and hardware-specific interfaces
236 *
237 * Return: 0 on success else error code
238 */
zynqmp_pll_enable(struct clk_hw *hw)239 static int zynqmp_pll_enable(struct clk_hw *hw)
240 {
241 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
242 const char *clk_name = clk_hw_get_name(hw);
243 u32 clk_id = clk->clk_id;
244 int ret;
245
246 /*
247 * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request
248 * that has been sent to ATF.
249 */
250 if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))
251 return 0;
252
253 clk->set_pll_mode = false;
254
255 ret = zynqmp_pm_clock_enable(clk_id);
256 if (ret)
257 pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
258 __func__, clk_name, ret);
259
260 return ret;
261 }
262
263 /**
264 * zynqmp_pll_disable() - Disable clock
265 * @hw: Handle between common and hardware-specific interfaces
266 */
zynqmp_pll_disable(struct clk_hw *hw)267 static void zynqmp_pll_disable(struct clk_hw *hw)
268 {
269 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
270 const char *clk_name = clk_hw_get_name(hw);
271 u32 clk_id = clk->clk_id;
272 int ret;
273
274 if (!zynqmp_pll_is_enabled(hw))
275 return;
276
277 ret = zynqmp_pm_clock_disable(clk_id);
278 if (ret)
279 pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
280 __func__, clk_name, ret);
281 }
282
283 static const struct clk_ops zynqmp_pll_ops = {
284 .enable = zynqmp_pll_enable,
285 .disable = zynqmp_pll_disable,
286 .is_enabled = zynqmp_pll_is_enabled,
287 .round_rate = zynqmp_pll_round_rate,
288 .recalc_rate = zynqmp_pll_recalc_rate,
289 .set_rate = zynqmp_pll_set_rate,
290 };
291
292 /**
293 * zynqmp_clk_register_pll() - Register PLL with the clock framework
294 * @name: PLL name
295 * @clk_id: Clock ID
296 * @parents: Name of this clock's parents
297 * @num_parents: Number of parents
298 * @nodes: Clock topology node
299 *
300 * Return: clock hardware to the registered clock
301 */
zynqmp_clk_register_pll(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, const struct clock_topology *nodes)302 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
303 const char * const *parents,
304 u8 num_parents,
305 const struct clock_topology *nodes)
306 {
307 struct zynqmp_pll *pll;
308 struct clk_hw *hw;
309 struct clk_init_data init;
310 int ret;
311
312 init.name = name;
313 init.ops = &zynqmp_pll_ops;
314 init.flags = nodes->flag;
315 init.parent_names = parents;
316 init.num_parents = 1;
317
318 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
319 if (!pll)
320 return ERR_PTR(-ENOMEM);
321
322 pll->hw.init = &init;
323 pll->clk_id = clk_id;
324
325 hw = &pll->hw;
326 ret = clk_hw_register(NULL, hw);
327 if (ret) {
328 kfree(pll);
329 return ERR_PTR(ret);
330 }
331
332 clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
333 if (ret < 0)
334 pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);
335
336 return hw;
337 }
338