1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12
13 #include "common.h"
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-pll.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap.h"
19 #include "gdsc.h"
20
21 #define CX_GMU_CBCR_SLEEP_MASK 0xf
22 #define CX_GMU_CBCR_SLEEP_SHIFT 4
23 #define CX_GMU_CBCR_WAKE_MASK 0xf
24 #define CX_GMU_CBCR_WAKE_SHIFT 8
25
26 enum {
27 P_BI_TCXO,
28 P_CORE_BI_PLL_TEST_SE,
29 P_GPLL0_OUT_MAIN,
30 P_GPLL0_OUT_MAIN_DIV,
31 P_GPU_CC_PLL1_OUT_EVEN,
32 P_GPU_CC_PLL1_OUT_MAIN,
33 P_GPU_CC_PLL1_OUT_ODD,
34 };
35
36 static const struct parent_map gpu_cc_parent_map_0[] = {
37 { P_BI_TCXO, 0 },
38 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
39 { P_GPLL0_OUT_MAIN, 5 },
40 { P_GPLL0_OUT_MAIN_DIV, 6 },
41 { P_CORE_BI_PLL_TEST_SE, 7 },
42 };
43
44 static const char * const gpu_cc_parent_names_0[] = {
45 "bi_tcxo",
46 "gpu_cc_pll1",
47 "gcc_gpu_gpll0_clk_src",
48 "gcc_gpu_gpll0_div_clk_src",
49 "core_bi_pll_test_se",
50 };
51
52 static const struct alpha_pll_config gpu_cc_pll1_config = {
53 .l = 0x1a,
54 .alpha = 0xaab,
55 };
56
57 static struct clk_alpha_pll gpu_cc_pll1 = {
58 .offset = 0x100,
59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
60 .clkr = {
61 .hw.init = &(struct clk_init_data){
62 .name = "gpu_cc_pll1",
63 .parent_names = (const char *[]){ "bi_tcxo" },
64 .num_parents = 1,
65 .ops = &clk_alpha_pll_fabia_ops,
66 },
67 },
68 };
69
70 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
71 F(19200000, P_BI_TCXO, 1, 0, 0),
72 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
73 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
74 { }
75 };
76
77 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
78 .cmd_rcgr = 0x1120,
79 .mnd_width = 0,
80 .hid_width = 5,
81 .parent_map = gpu_cc_parent_map_0,
82 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
83 .clkr.hw.init = &(struct clk_init_data){
84 .name = "gpu_cc_gmu_clk_src",
85 .parent_names = gpu_cc_parent_names_0,
86 .num_parents = 5,
87 .ops = &clk_rcg2_shared_ops,
88 },
89 };
90
91 static struct clk_branch gpu_cc_cx_gmu_clk = {
92 .halt_reg = 0x1098,
93 .halt_check = BRANCH_HALT,
94 .clkr = {
95 .enable_reg = 0x1098,
96 .enable_mask = BIT(0),
97 .hw.init = &(struct clk_init_data){
98 .name = "gpu_cc_cx_gmu_clk",
99 .parent_names = (const char *[]){
100 "gpu_cc_gmu_clk_src",
101 },
102 .num_parents = 1,
103 .flags = CLK_SET_RATE_PARENT,
104 .ops = &clk_branch2_ops,
105 },
106 },
107 };
108
109 static struct clk_branch gpu_cc_cxo_clk = {
110 .halt_reg = 0x109c,
111 .halt_check = BRANCH_HALT,
112 .clkr = {
113 .enable_reg = 0x109c,
114 .enable_mask = BIT(0),
115 .hw.init = &(struct clk_init_data){
116 .name = "gpu_cc_cxo_clk",
117 .ops = &clk_branch2_ops,
118 },
119 },
120 };
121
122 static struct gdsc gpu_cx_gdsc = {
123 .gdscr = 0x106c,
124 .gds_hw_ctrl = 0x1540,
125 .clk_dis_wait_val = 0x8,
126 .pd = {
127 .name = "gpu_cx_gdsc",
128 },
129 .pwrsts = PWRSTS_OFF_ON,
130 .flags = VOTABLE,
131 };
132
133 static struct gdsc gpu_gx_gdsc = {
134 .gdscr = 0x100c,
135 .clamp_io_ctrl = 0x1508,
136 .pd = {
137 .name = "gpu_gx_gdsc",
138 .power_on = gdsc_gx_do_nothing_enable,
139 },
140 .pwrsts = PWRSTS_OFF_ON,
141 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
142 };
143
144 static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
145 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
146 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
147 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
148 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
149 };
150
151 static struct gdsc *gpu_cc_sdm845_gdscs[] = {
152 [GPU_CX_GDSC] = &gpu_cx_gdsc,
153 [GPU_GX_GDSC] = &gpu_gx_gdsc,
154 };
155
156 static const struct regmap_config gpu_cc_sdm845_regmap_config = {
157 .reg_bits = 32,
158 .reg_stride = 4,
159 .val_bits = 32,
160 .max_register = 0x8008,
161 .fast_io = true,
162 };
163
164 static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
165 .config = &gpu_cc_sdm845_regmap_config,
166 .clks = gpu_cc_sdm845_clocks,
167 .num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
168 .gdscs = gpu_cc_sdm845_gdscs,
169 .num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
170 };
171
172 static const struct of_device_id gpu_cc_sdm845_match_table[] = {
173 { .compatible = "qcom,sdm845-gpucc" },
174 { }
175 };
176 MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
177
gpu_cc_sdm845_probe(struct platform_device *pdev)178 static int gpu_cc_sdm845_probe(struct platform_device *pdev)
179 {
180 struct regmap *regmap;
181 unsigned int value, mask;
182
183 regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
184 if (IS_ERR(regmap))
185 return PTR_ERR(regmap);
186
187 clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
188
189 /*
190 * Configure gpu_cc_cx_gmu_clk with recommended
191 * wakeup/sleep settings
192 */
193 mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
194 mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
195 value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
196 regmap_update_bits(regmap, 0x1098, mask, value);
197
198 return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
199 }
200
201 static struct platform_driver gpu_cc_sdm845_driver = {
202 .probe = gpu_cc_sdm845_probe,
203 .driver = {
204 .name = "sdm845-gpucc",
205 .of_match_table = gpu_cc_sdm845_match_table,
206 },
207 };
208
gpu_cc_sdm845_init(void)209 static int __init gpu_cc_sdm845_init(void)
210 {
211 return platform_driver_register(&gpu_cc_sdm845_driver);
212 }
213 subsys_initcall(gpu_cc_sdm845_init);
214
gpu_cc_sdm845_exit(void)215 static void __exit gpu_cc_sdm845_exit(void)
216 {
217 platform_driver_unregister(&gpu_cc_sdm845_driver);
218 }
219 module_exit(gpu_cc_sdm845_exit);
220
221 MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
222 MODULE_LICENSE("GPL v2");
223