1 /*******************************************************************
2 *
3 * Copyright (c) 2000 ATecoM GmbH
4 *
5 * The author may be reached at ecd@atecom.com.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *******************************************************************/
28
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/poison.h>
32 #include <linux/skbuff.h>
33 #include <linux/kernel.h>
34 #include <linux/vmalloc.h>
35 #include <linux/netdevice.h>
36 #include <linux/atmdev.h>
37 #include <linux/atm.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/interrupt.h>
41 #include <linux/bitops.h>
42 #include <linux/wait.h>
43 #include <linux/jiffies.h>
44 #include <linux/mutex.h>
45 #include <linux/slab.h>
46
47 #include <asm/io.h>
48 #include <linux/uaccess.h>
49 #include <linux/atomic.h>
50 #include <asm/byteorder.h>
51
52 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
53 #include "suni.h"
54 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
55
56
57 #include "idt77252.h"
58 #include "idt77252_tables.h"
59
60 static unsigned int vpibits = 1;
61
62
63 #define ATM_IDT77252_SEND_IDLE 1
64
65
66 /*
67 * Debug HACKs.
68 */
69 #define DEBUG_MODULE 1
70 #undef HAVE_EEPROM /* does not work, yet. */
71
72 #ifdef CONFIG_ATM_IDT77252_DEBUG
73 static unsigned long debug = DBG_GENERAL;
74 #endif
75
76
77 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
78
79
80 /*
81 * SCQ Handling.
82 */
83 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
84 static void free_scq(struct idt77252_dev *, struct scq_info *);
85 static int queue_skb(struct idt77252_dev *, struct vc_map *,
86 struct sk_buff *, int oam);
87 static void drain_scq(struct idt77252_dev *, struct vc_map *);
88 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
89 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
90
91 /*
92 * FBQ Handling.
93 */
94 static int push_rx_skb(struct idt77252_dev *,
95 struct sk_buff *, int queue);
96 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
97 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
98 static void recycle_rx_pool_skb(struct idt77252_dev *,
99 struct rx_pool *);
100 static void add_rx_skb(struct idt77252_dev *, int queue,
101 unsigned int size, unsigned int count);
102
103 /*
104 * RSQ Handling.
105 */
106 static int init_rsq(struct idt77252_dev *);
107 static void deinit_rsq(struct idt77252_dev *);
108 static void idt77252_rx(struct idt77252_dev *);
109
110 /*
111 * TSQ handling.
112 */
113 static int init_tsq(struct idt77252_dev *);
114 static void deinit_tsq(struct idt77252_dev *);
115 static void idt77252_tx(struct idt77252_dev *);
116
117
118 /*
119 * ATM Interface.
120 */
121 static void idt77252_dev_close(struct atm_dev *dev);
122 static int idt77252_open(struct atm_vcc *vcc);
123 static void idt77252_close(struct atm_vcc *vcc);
124 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
125 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
126 int flags);
127 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
128 unsigned long addr);
129 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
130 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
131 int flags);
132 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
133 char *page);
134 static void idt77252_softint(struct work_struct *work);
135
136
137 static const struct atmdev_ops idt77252_ops =
138 {
139 .dev_close = idt77252_dev_close,
140 .open = idt77252_open,
141 .close = idt77252_close,
142 .send = idt77252_send,
143 .send_oam = idt77252_send_oam,
144 .phy_put = idt77252_phy_put,
145 .phy_get = idt77252_phy_get,
146 .change_qos = idt77252_change_qos,
147 .proc_read = idt77252_proc_read,
148 .owner = THIS_MODULE
149 };
150
151 static struct idt77252_dev *idt77252_chain = NULL;
152 static unsigned int idt77252_sram_write_errors = 0;
153
154 /*****************************************************************************/
155 /* */
156 /* I/O and Utility Bus */
157 /* */
158 /*****************************************************************************/
159
160 static void
waitfor_idle(struct idt77252_dev *card)161 waitfor_idle(struct idt77252_dev *card)
162 {
163 u32 stat;
164
165 stat = readl(SAR_REG_STAT);
166 while (stat & SAR_STAT_CMDBZ)
167 stat = readl(SAR_REG_STAT);
168 }
169
170 static u32
read_sram(struct idt77252_dev *card, unsigned long addr)171 read_sram(struct idt77252_dev *card, unsigned long addr)
172 {
173 unsigned long flags;
174 u32 value;
175
176 spin_lock_irqsave(&card->cmd_lock, flags);
177 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
178 waitfor_idle(card);
179 value = readl(SAR_REG_DR0);
180 spin_unlock_irqrestore(&card->cmd_lock, flags);
181 return value;
182 }
183
184 static void
write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)185 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
186 {
187 unsigned long flags;
188
189 if ((idt77252_sram_write_errors == 0) &&
190 (((addr > card->tst[0] + card->tst_size - 2) &&
191 (addr < card->tst[0] + card->tst_size)) ||
192 ((addr > card->tst[1] + card->tst_size - 2) &&
193 (addr < card->tst[1] + card->tst_size)))) {
194 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
195 card->name, addr, value);
196 }
197
198 spin_lock_irqsave(&card->cmd_lock, flags);
199 writel(value, SAR_REG_DR0);
200 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
201 waitfor_idle(card);
202 spin_unlock_irqrestore(&card->cmd_lock, flags);
203 }
204
205 static u8
read_utility(void *dev, unsigned long ubus_addr)206 read_utility(void *dev, unsigned long ubus_addr)
207 {
208 struct idt77252_dev *card = dev;
209 unsigned long flags;
210 u8 value;
211
212 if (!card) {
213 printk("Error: No such device.\n");
214 return -1;
215 }
216
217 spin_lock_irqsave(&card->cmd_lock, flags);
218 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
219 waitfor_idle(card);
220 value = readl(SAR_REG_DR0);
221 spin_unlock_irqrestore(&card->cmd_lock, flags);
222 return value;
223 }
224
225 static void
write_utility(void *dev, unsigned long ubus_addr, u8 value)226 write_utility(void *dev, unsigned long ubus_addr, u8 value)
227 {
228 struct idt77252_dev *card = dev;
229 unsigned long flags;
230
231 if (!card) {
232 printk("Error: No such device.\n");
233 return;
234 }
235
236 spin_lock_irqsave(&card->cmd_lock, flags);
237 writel((u32) value, SAR_REG_DR0);
238 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
239 waitfor_idle(card);
240 spin_unlock_irqrestore(&card->cmd_lock, flags);
241 }
242
243 #ifdef HAVE_EEPROM
244 static u32 rdsrtab[] =
245 {
246 SAR_GP_EECS | SAR_GP_EESCLK,
247 0,
248 SAR_GP_EESCLK, /* 0 */
249 0,
250 SAR_GP_EESCLK, /* 0 */
251 0,
252 SAR_GP_EESCLK, /* 0 */
253 0,
254 SAR_GP_EESCLK, /* 0 */
255 0,
256 SAR_GP_EESCLK, /* 0 */
257 SAR_GP_EEDO,
258 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
259 0,
260 SAR_GP_EESCLK, /* 0 */
261 SAR_GP_EEDO,
262 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
263 };
264
265 static u32 wrentab[] =
266 {
267 SAR_GP_EECS | SAR_GP_EESCLK,
268 0,
269 SAR_GP_EESCLK, /* 0 */
270 0,
271 SAR_GP_EESCLK, /* 0 */
272 0,
273 SAR_GP_EESCLK, /* 0 */
274 0,
275 SAR_GP_EESCLK, /* 0 */
276 SAR_GP_EEDO,
277 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
278 SAR_GP_EEDO,
279 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
280 0,
281 SAR_GP_EESCLK, /* 0 */
282 0,
283 SAR_GP_EESCLK /* 0 */
284 };
285
286 static u32 rdtab[] =
287 {
288 SAR_GP_EECS | SAR_GP_EESCLK,
289 0,
290 SAR_GP_EESCLK, /* 0 */
291 0,
292 SAR_GP_EESCLK, /* 0 */
293 0,
294 SAR_GP_EESCLK, /* 0 */
295 0,
296 SAR_GP_EESCLK, /* 0 */
297 0,
298 SAR_GP_EESCLK, /* 0 */
299 0,
300 SAR_GP_EESCLK, /* 0 */
301 SAR_GP_EEDO,
302 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
303 SAR_GP_EEDO,
304 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
305 };
306
307 static u32 wrtab[] =
308 {
309 SAR_GP_EECS | SAR_GP_EESCLK,
310 0,
311 SAR_GP_EESCLK, /* 0 */
312 0,
313 SAR_GP_EESCLK, /* 0 */
314 0,
315 SAR_GP_EESCLK, /* 0 */
316 0,
317 SAR_GP_EESCLK, /* 0 */
318 0,
319 SAR_GP_EESCLK, /* 0 */
320 0,
321 SAR_GP_EESCLK, /* 0 */
322 SAR_GP_EEDO,
323 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
324 0,
325 SAR_GP_EESCLK /* 0 */
326 };
327
328 static u32 clktab[] =
329 {
330 0,
331 SAR_GP_EESCLK,
332 0,
333 SAR_GP_EESCLK,
334 0,
335 SAR_GP_EESCLK,
336 0,
337 SAR_GP_EESCLK,
338 0,
339 SAR_GP_EESCLK,
340 0,
341 SAR_GP_EESCLK,
342 0,
343 SAR_GP_EESCLK,
344 0,
345 SAR_GP_EESCLK,
346 0
347 };
348
349 static u32
idt77252_read_gp(struct idt77252_dev *card)350 idt77252_read_gp(struct idt77252_dev *card)
351 {
352 u32 gp;
353
354 gp = readl(SAR_REG_GP);
355 #if 0
356 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
357 #endif
358 return gp;
359 }
360
361 static void
idt77252_write_gp(struct idt77252_dev *card, u32 value)362 idt77252_write_gp(struct idt77252_dev *card, u32 value)
363 {
364 unsigned long flags;
365
366 #if 0
367 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
368 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
369 value & SAR_GP_EEDO ? "1" : "0");
370 #endif
371
372 spin_lock_irqsave(&card->cmd_lock, flags);
373 waitfor_idle(card);
374 writel(value, SAR_REG_GP);
375 spin_unlock_irqrestore(&card->cmd_lock, flags);
376 }
377
378 static u8
idt77252_eeprom_read_status(struct idt77252_dev *card)379 idt77252_eeprom_read_status(struct idt77252_dev *card)
380 {
381 u8 byte;
382 u32 gp;
383 int i, j;
384
385 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
386
387 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
388 idt77252_write_gp(card, gp | rdsrtab[i]);
389 udelay(5);
390 }
391 idt77252_write_gp(card, gp | SAR_GP_EECS);
392 udelay(5);
393
394 byte = 0;
395 for (i = 0, j = 0; i < 8; i++) {
396 byte <<= 1;
397
398 idt77252_write_gp(card, gp | clktab[j++]);
399 udelay(5);
400
401 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
402
403 idt77252_write_gp(card, gp | clktab[j++]);
404 udelay(5);
405 }
406 idt77252_write_gp(card, gp | SAR_GP_EECS);
407 udelay(5);
408
409 return byte;
410 }
411
412 static u8
idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)413 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
414 {
415 u8 byte;
416 u32 gp;
417 int i, j;
418
419 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
420
421 for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
422 idt77252_write_gp(card, gp | rdtab[i]);
423 udelay(5);
424 }
425 idt77252_write_gp(card, gp | SAR_GP_EECS);
426 udelay(5);
427
428 for (i = 0, j = 0; i < 8; i++) {
429 idt77252_write_gp(card, gp | clktab[j++] |
430 (offset & 1 ? SAR_GP_EEDO : 0));
431 udelay(5);
432
433 idt77252_write_gp(card, gp | clktab[j++] |
434 (offset & 1 ? SAR_GP_EEDO : 0));
435 udelay(5);
436
437 offset >>= 1;
438 }
439 idt77252_write_gp(card, gp | SAR_GP_EECS);
440 udelay(5);
441
442 byte = 0;
443 for (i = 0, j = 0; i < 8; i++) {
444 byte <<= 1;
445
446 idt77252_write_gp(card, gp | clktab[j++]);
447 udelay(5);
448
449 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
450
451 idt77252_write_gp(card, gp | clktab[j++]);
452 udelay(5);
453 }
454 idt77252_write_gp(card, gp | SAR_GP_EECS);
455 udelay(5);
456
457 return byte;
458 }
459
460 static void
idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)461 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
462 {
463 u32 gp;
464 int i, j;
465
466 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
467
468 for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
469 idt77252_write_gp(card, gp | wrentab[i]);
470 udelay(5);
471 }
472 idt77252_write_gp(card, gp | SAR_GP_EECS);
473 udelay(5);
474
475 for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
476 idt77252_write_gp(card, gp | wrtab[i]);
477 udelay(5);
478 }
479 idt77252_write_gp(card, gp | SAR_GP_EECS);
480 udelay(5);
481
482 for (i = 0, j = 0; i < 8; i++) {
483 idt77252_write_gp(card, gp | clktab[j++] |
484 (offset & 1 ? SAR_GP_EEDO : 0));
485 udelay(5);
486
487 idt77252_write_gp(card, gp | clktab[j++] |
488 (offset & 1 ? SAR_GP_EEDO : 0));
489 udelay(5);
490
491 offset >>= 1;
492 }
493 idt77252_write_gp(card, gp | SAR_GP_EECS);
494 udelay(5);
495
496 for (i = 0, j = 0; i < 8; i++) {
497 idt77252_write_gp(card, gp | clktab[j++] |
498 (data & 1 ? SAR_GP_EEDO : 0));
499 udelay(5);
500
501 idt77252_write_gp(card, gp | clktab[j++] |
502 (data & 1 ? SAR_GP_EEDO : 0));
503 udelay(5);
504
505 data >>= 1;
506 }
507 idt77252_write_gp(card, gp | SAR_GP_EECS);
508 udelay(5);
509 }
510
511 static void
idt77252_eeprom_init(struct idt77252_dev *card)512 idt77252_eeprom_init(struct idt77252_dev *card)
513 {
514 u32 gp;
515
516 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
517
518 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
519 udelay(5);
520 idt77252_write_gp(card, gp | SAR_GP_EECS);
521 udelay(5);
522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523 udelay(5);
524 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 udelay(5);
526 }
527 #endif /* HAVE_EEPROM */
528
529
530 #ifdef CONFIG_ATM_IDT77252_DEBUG
531 static void
dump_tct(struct idt77252_dev *card, int index)532 dump_tct(struct idt77252_dev *card, int index)
533 {
534 unsigned long tct;
535 int i;
536
537 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
538
539 printk("%s: TCT %x:", card->name, index);
540 for (i = 0; i < 8; i++) {
541 printk(" %08x", read_sram(card, tct + i));
542 }
543 printk("\n");
544 }
545
546 static void
idt77252_tx_dump(struct idt77252_dev *card)547 idt77252_tx_dump(struct idt77252_dev *card)
548 {
549 struct atm_vcc *vcc;
550 struct vc_map *vc;
551 int i;
552
553 printk("%s\n", __func__);
554 for (i = 0; i < card->tct_size; i++) {
555 vc = card->vcs[i];
556 if (!vc)
557 continue;
558
559 vcc = NULL;
560 if (vc->rx_vcc)
561 vcc = vc->rx_vcc;
562 else if (vc->tx_vcc)
563 vcc = vc->tx_vcc;
564
565 if (!vcc)
566 continue;
567
568 printk("%s: Connection %d:\n", card->name, vc->index);
569 dump_tct(card, vc->index);
570 }
571 }
572 #endif
573
574
575 /*****************************************************************************/
576 /* */
577 /* SCQ Handling */
578 /* */
579 /*****************************************************************************/
580
581 static int
sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)582 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
583 {
584 struct sb_pool *pool = &card->sbpool[queue];
585 int index;
586
587 index = pool->index;
588 while (pool->skb[index]) {
589 index = (index + 1) & FBQ_MASK;
590 if (index == pool->index)
591 return -ENOBUFS;
592 }
593
594 pool->skb[index] = skb;
595 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
596
597 pool->index = (index + 1) & FBQ_MASK;
598 return 0;
599 }
600
601 static void
sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)602 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
603 {
604 unsigned int queue, index;
605 u32 handle;
606
607 handle = IDT77252_PRV_POOL(skb);
608
609 queue = POOL_QUEUE(handle);
610 if (queue > 3)
611 return;
612
613 index = POOL_INDEX(handle);
614 if (index > FBQ_SIZE - 1)
615 return;
616
617 card->sbpool[queue].skb[index] = NULL;
618 }
619
620 static struct sk_buff *
sb_pool_skb(struct idt77252_dev *card, u32 handle)621 sb_pool_skb(struct idt77252_dev *card, u32 handle)
622 {
623 unsigned int queue, index;
624
625 queue = POOL_QUEUE(handle);
626 if (queue > 3)
627 return NULL;
628
629 index = POOL_INDEX(handle);
630 if (index > FBQ_SIZE - 1)
631 return NULL;
632
633 return card->sbpool[queue].skb[index];
634 }
635
636 static struct scq_info *
alloc_scq(struct idt77252_dev *card, int class)637 alloc_scq(struct idt77252_dev *card, int class)
638 {
639 struct scq_info *scq;
640
641 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
642 if (!scq)
643 return NULL;
644 scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE,
645 &scq->paddr, GFP_KERNEL);
646 if (scq->base == NULL) {
647 kfree(scq);
648 return NULL;
649 }
650
651 scq->next = scq->base;
652 scq->last = scq->base + (SCQ_ENTRIES - 1);
653 atomic_set(&scq->used, 0);
654
655 spin_lock_init(&scq->lock);
656 spin_lock_init(&scq->skblock);
657
658 skb_queue_head_init(&scq->transmit);
659 skb_queue_head_init(&scq->pending);
660
661 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
662 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
663
664 return scq;
665 }
666
667 static void
free_scq(struct idt77252_dev *card, struct scq_info *scq)668 free_scq(struct idt77252_dev *card, struct scq_info *scq)
669 {
670 struct sk_buff *skb;
671 struct atm_vcc *vcc;
672
673 dma_free_coherent(&card->pcidev->dev, SCQ_SIZE,
674 scq->base, scq->paddr);
675
676 while ((skb = skb_dequeue(&scq->transmit))) {
677 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
678 skb->len, DMA_TO_DEVICE);
679
680 vcc = ATM_SKB(skb)->vcc;
681 if (vcc->pop)
682 vcc->pop(vcc, skb);
683 else
684 dev_kfree_skb(skb);
685 }
686
687 while ((skb = skb_dequeue(&scq->pending))) {
688 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
689 skb->len, DMA_TO_DEVICE);
690
691 vcc = ATM_SKB(skb)->vcc;
692 if (vcc->pop)
693 vcc->pop(vcc, skb);
694 else
695 dev_kfree_skb(skb);
696 }
697
698 kfree(scq);
699 }
700
701
702 static int
push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)703 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
704 {
705 struct scq_info *scq = vc->scq;
706 unsigned long flags;
707 struct scqe *tbd;
708 int entries;
709
710 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
711
712 atomic_inc(&scq->used);
713 entries = atomic_read(&scq->used);
714 if (entries > (SCQ_ENTRIES - 1)) {
715 atomic_dec(&scq->used);
716 goto out;
717 }
718
719 skb_queue_tail(&scq->transmit, skb);
720
721 spin_lock_irqsave(&vc->lock, flags);
722 if (vc->estimator) {
723 struct atm_vcc *vcc = vc->tx_vcc;
724 struct sock *sk = sk_atm(vcc);
725
726 vc->estimator->cells += (skb->len + 47) / 48;
727 if (refcount_read(&sk->sk_wmem_alloc) >
728 (sk->sk_sndbuf >> 1)) {
729 u32 cps = vc->estimator->maxcps;
730
731 vc->estimator->cps = cps;
732 vc->estimator->avcps = cps << 5;
733 if (vc->lacr < vc->init_er) {
734 vc->lacr = vc->init_er;
735 writel(TCMDQ_LACR | (vc->lacr << 16) |
736 vc->index, SAR_REG_TCMDQ);
737 }
738 }
739 }
740 spin_unlock_irqrestore(&vc->lock, flags);
741
742 tbd = &IDT77252_PRV_TBD(skb);
743
744 spin_lock_irqsave(&scq->lock, flags);
745 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
746 SAR_TBD_TSIF | SAR_TBD_GTSI);
747 scq->next->word_2 = cpu_to_le32(tbd->word_2);
748 scq->next->word_3 = cpu_to_le32(tbd->word_3);
749 scq->next->word_4 = cpu_to_le32(tbd->word_4);
750
751 if (scq->next == scq->last)
752 scq->next = scq->base;
753 else
754 scq->next++;
755
756 write_sram(card, scq->scd,
757 scq->paddr +
758 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
759 spin_unlock_irqrestore(&scq->lock, flags);
760
761 scq->trans_start = jiffies;
762
763 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
764 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
765 SAR_REG_TCMDQ);
766 }
767
768 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
769
770 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
771 card->name, atomic_read(&scq->used),
772 read_sram(card, scq->scd + 1), scq->next);
773
774 return 0;
775
776 out:
777 if (time_after(jiffies, scq->trans_start + HZ)) {
778 printk("%s: Error pushing TBD for %d.%d\n",
779 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
780 #ifdef CONFIG_ATM_IDT77252_DEBUG
781 idt77252_tx_dump(card);
782 #endif
783 scq->trans_start = jiffies;
784 }
785
786 return -ENOBUFS;
787 }
788
789
790 static void
drain_scq(struct idt77252_dev *card, struct vc_map *vc)791 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
792 {
793 struct scq_info *scq = vc->scq;
794 struct sk_buff *skb;
795 struct atm_vcc *vcc;
796
797 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
798 card->name, atomic_read(&scq->used), scq->next);
799
800 skb = skb_dequeue(&scq->transmit);
801 if (skb) {
802 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
803
804 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
805 skb->len, DMA_TO_DEVICE);
806
807 vcc = ATM_SKB(skb)->vcc;
808
809 if (vcc->pop)
810 vcc->pop(vcc, skb);
811 else
812 dev_kfree_skb(skb);
813
814 atomic_inc(&vcc->stats->tx);
815 }
816
817 atomic_dec(&scq->used);
818
819 spin_lock(&scq->skblock);
820 while ((skb = skb_dequeue(&scq->pending))) {
821 if (push_on_scq(card, vc, skb)) {
822 skb_queue_head(&vc->scq->pending, skb);
823 break;
824 }
825 }
826 spin_unlock(&scq->skblock);
827 }
828
829 static int
queue_skb(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb, int oam)830 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
831 struct sk_buff *skb, int oam)
832 {
833 struct atm_vcc *vcc;
834 struct scqe *tbd;
835 unsigned long flags;
836 int error;
837 int aal;
838 u32 word4;
839
840 if (skb->len == 0) {
841 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
842 return -EINVAL;
843 }
844
845 TXPRINTK("%s: Sending %d bytes of data.\n",
846 card->name, skb->len);
847
848 tbd = &IDT77252_PRV_TBD(skb);
849 vcc = ATM_SKB(skb)->vcc;
850 word4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
851 (skb->data[2] << 8) | (skb->data[3] << 0);
852
853 IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,
854 skb->len, DMA_TO_DEVICE);
855
856 error = -EINVAL;
857
858 if (oam) {
859 if (skb->len != 52)
860 goto errout;
861
862 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
863 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
864 tbd->word_3 = 0x00000000;
865 tbd->word_4 = word4;
866
867 if (test_bit(VCF_RSV, &vc->flags))
868 vc = card->vcs[0];
869
870 goto done;
871 }
872
873 if (test_bit(VCF_RSV, &vc->flags)) {
874 printk("%s: Trying to transmit on reserved VC\n", card->name);
875 goto errout;
876 }
877
878 aal = vcc->qos.aal;
879
880 switch (aal) {
881 case ATM_AAL0:
882 case ATM_AAL34:
883 if (skb->len > 52)
884 goto errout;
885
886 if (aal == ATM_AAL0)
887 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
888 ATM_CELL_PAYLOAD;
889 else
890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
891 ATM_CELL_PAYLOAD;
892
893 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
894 tbd->word_3 = 0x00000000;
895 tbd->word_4 = word4;
896 break;
897
898 case ATM_AAL5:
899 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
900 tbd->word_2 = IDT77252_PRV_PADDR(skb);
901 tbd->word_3 = skb->len;
902 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
903 (vcc->vci << SAR_TBD_VCI_SHIFT);
904 break;
905
906 case ATM_AAL1:
907 case ATM_AAL2:
908 default:
909 printk("%s: Traffic type not supported.\n", card->name);
910 error = -EPROTONOSUPPORT;
911 goto errout;
912 }
913
914 done:
915 spin_lock_irqsave(&vc->scq->skblock, flags);
916 skb_queue_tail(&vc->scq->pending, skb);
917
918 while ((skb = skb_dequeue(&vc->scq->pending))) {
919 if (push_on_scq(card, vc, skb)) {
920 skb_queue_head(&vc->scq->pending, skb);
921 break;
922 }
923 }
924 spin_unlock_irqrestore(&vc->scq->skblock, flags);
925
926 return 0;
927
928 errout:
929 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
930 skb->len, DMA_TO_DEVICE);
931 return error;
932 }
933
934 static unsigned long
get_free_scd(struct idt77252_dev *card, struct vc_map *vc)935 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
936 {
937 int i;
938
939 for (i = 0; i < card->scd_size; i++) {
940 if (!card->scd2vc[i]) {
941 card->scd2vc[i] = vc;
942 vc->scd_index = i;
943 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
944 }
945 }
946 return 0;
947 }
948
949 static void
fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)950 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
951 {
952 write_sram(card, scq->scd, scq->paddr);
953 write_sram(card, scq->scd + 1, 0x00000000);
954 write_sram(card, scq->scd + 2, 0xffffffff);
955 write_sram(card, scq->scd + 3, 0x00000000);
956 }
957
958 static void
clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)959 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
960 {
961 return;
962 }
963
964 /*****************************************************************************/
965 /* */
966 /* RSQ Handling */
967 /* */
968 /*****************************************************************************/
969
970 static int
init_rsq(struct idt77252_dev *card)971 init_rsq(struct idt77252_dev *card)
972 {
973 struct rsq_entry *rsqe;
974
975 card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
976 &card->rsq.paddr, GFP_KERNEL);
977 if (card->rsq.base == NULL) {
978 printk("%s: can't allocate RSQ.\n", card->name);
979 return -1;
980 }
981
982 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
983 card->rsq.next = card->rsq.last;
984 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
985 rsqe->word_4 = 0;
986
987 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
988 SAR_REG_RSQH);
989 writel(card->rsq.paddr, SAR_REG_RSQB);
990
991 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
992 (unsigned long) card->rsq.base,
993 readl(SAR_REG_RSQB));
994 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
995 card->name,
996 readl(SAR_REG_RSQH),
997 readl(SAR_REG_RSQB),
998 readl(SAR_REG_RSQT));
999
1000 return 0;
1001 }
1002
1003 static void
deinit_rsq(struct idt77252_dev *card)1004 deinit_rsq(struct idt77252_dev *card)
1005 {
1006 dma_free_coherent(&card->pcidev->dev, RSQSIZE,
1007 card->rsq.base, card->rsq.paddr);
1008 }
1009
1010 static void
dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)1011 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1012 {
1013 struct atm_vcc *vcc;
1014 struct sk_buff *skb;
1015 struct rx_pool *rpp;
1016 struct vc_map *vc;
1017 u32 header, vpi, vci;
1018 u32 stat;
1019 int i;
1020
1021 stat = le32_to_cpu(rsqe->word_4);
1022
1023 if (stat & SAR_RSQE_IDLE) {
1024 RXPRINTK("%s: message about inactive connection.\n",
1025 card->name);
1026 return;
1027 }
1028
1029 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1030 if (skb == NULL) {
1031 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1032 card->name, __func__,
1033 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1034 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1035 return;
1036 }
1037
1038 header = le32_to_cpu(rsqe->word_1);
1039 vpi = (header >> 16) & 0x00ff;
1040 vci = (header >> 0) & 0xffff;
1041
1042 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1043 card->name, vpi, vci, skb, skb->data);
1044
1045 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1046 printk("%s: SDU received for out-of-range vc %u.%u\n",
1047 card->name, vpi, vci);
1048 recycle_rx_skb(card, skb);
1049 return;
1050 }
1051
1052 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1053 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1054 printk("%s: SDU received on non RX vc %u.%u\n",
1055 card->name, vpi, vci);
1056 recycle_rx_skb(card, skb);
1057 return;
1058 }
1059
1060 vcc = vc->rx_vcc;
1061
1062 dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1063 skb_end_pointer(skb) - skb->data,
1064 DMA_FROM_DEVICE);
1065
1066 if ((vcc->qos.aal == ATM_AAL0) ||
1067 (vcc->qos.aal == ATM_AAL34)) {
1068 struct sk_buff *sb;
1069 unsigned char *cell;
1070 u32 aal0;
1071
1072 cell = skb->data;
1073 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1074 if ((sb = dev_alloc_skb(64)) == NULL) {
1075 printk("%s: Can't allocate buffers for aal0.\n",
1076 card->name);
1077 atomic_add(i, &vcc->stats->rx_drop);
1078 break;
1079 }
1080 if (!atm_charge(vcc, sb->truesize)) {
1081 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1082 card->name);
1083 atomic_add(i - 1, &vcc->stats->rx_drop);
1084 dev_kfree_skb(sb);
1085 break;
1086 }
1087 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1088 (vci << ATM_HDR_VCI_SHIFT);
1089 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1090 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1091
1092 *((u32 *) sb->data) = aal0;
1093 skb_put(sb, sizeof(u32));
1094 skb_put_data(sb, cell, ATM_CELL_PAYLOAD);
1095
1096 ATM_SKB(sb)->vcc = vcc;
1097 __net_timestamp(sb);
1098 vcc->push(vcc, sb);
1099 atomic_inc(&vcc->stats->rx);
1100
1101 cell += ATM_CELL_PAYLOAD;
1102 }
1103
1104 recycle_rx_skb(card, skb);
1105 return;
1106 }
1107 if (vcc->qos.aal != ATM_AAL5) {
1108 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1109 card->name, vcc->qos.aal);
1110 recycle_rx_skb(card, skb);
1111 return;
1112 }
1113 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1114
1115 rpp = &vc->rcv.rx_pool;
1116
1117 __skb_queue_tail(&rpp->queue, skb);
1118 rpp->len += skb->len;
1119
1120 if (stat & SAR_RSQE_EPDU) {
1121 unsigned int len, truesize;
1122 unsigned char *l1l2;
1123
1124 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1125
1126 len = (l1l2[0] << 8) | l1l2[1];
1127 len = len ? len : 0x10000;
1128
1129 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1130
1131 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1132 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1133 "(CDC: %08x)\n",
1134 card->name, len, rpp->len, readl(SAR_REG_CDC));
1135 recycle_rx_pool_skb(card, rpp);
1136 atomic_inc(&vcc->stats->rx_err);
1137 return;
1138 }
1139 if (stat & SAR_RSQE_CRC) {
1140 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1141 recycle_rx_pool_skb(card, rpp);
1142 atomic_inc(&vcc->stats->rx_err);
1143 return;
1144 }
1145 if (skb_queue_len(&rpp->queue) > 1) {
1146 struct sk_buff *sb;
1147
1148 skb = dev_alloc_skb(rpp->len);
1149 if (!skb) {
1150 RXPRINTK("%s: Can't alloc RX skb.\n",
1151 card->name);
1152 recycle_rx_pool_skb(card, rpp);
1153 atomic_inc(&vcc->stats->rx_err);
1154 return;
1155 }
1156 if (!atm_charge(vcc, skb->truesize)) {
1157 recycle_rx_pool_skb(card, rpp);
1158 dev_kfree_skb(skb);
1159 return;
1160 }
1161 skb_queue_walk(&rpp->queue, sb)
1162 skb_put_data(skb, sb->data, sb->len);
1163
1164 recycle_rx_pool_skb(card, rpp);
1165
1166 skb_trim(skb, len);
1167 ATM_SKB(skb)->vcc = vcc;
1168 __net_timestamp(skb);
1169
1170 vcc->push(vcc, skb);
1171 atomic_inc(&vcc->stats->rx);
1172
1173 return;
1174 }
1175
1176 flush_rx_pool(card, rpp);
1177
1178 if (!atm_charge(vcc, skb->truesize)) {
1179 recycle_rx_skb(card, skb);
1180 return;
1181 }
1182
1183 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1184 skb_end_pointer(skb) - skb->data,
1185 DMA_FROM_DEVICE);
1186 sb_pool_remove(card, skb);
1187
1188 skb_trim(skb, len);
1189 ATM_SKB(skb)->vcc = vcc;
1190 __net_timestamp(skb);
1191
1192 truesize = skb->truesize;
1193 vcc->push(vcc, skb);
1194 atomic_inc(&vcc->stats->rx);
1195
1196 if (truesize > SAR_FB_SIZE_3)
1197 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1198 else if (truesize > SAR_FB_SIZE_2)
1199 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1200 else if (truesize > SAR_FB_SIZE_1)
1201 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1202 else
1203 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1204 return;
1205 }
1206 }
1207
1208 static void
idt77252_rx(struct idt77252_dev *card)1209 idt77252_rx(struct idt77252_dev *card)
1210 {
1211 struct rsq_entry *rsqe;
1212
1213 if (card->rsq.next == card->rsq.last)
1214 rsqe = card->rsq.base;
1215 else
1216 rsqe = card->rsq.next + 1;
1217
1218 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1219 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1220 return;
1221 }
1222
1223 do {
1224 dequeue_rx(card, rsqe);
1225 rsqe->word_4 = 0;
1226 card->rsq.next = rsqe;
1227 if (card->rsq.next == card->rsq.last)
1228 rsqe = card->rsq.base;
1229 else
1230 rsqe = card->rsq.next + 1;
1231 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1232
1233 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1234 SAR_REG_RSQH);
1235 }
1236
1237 static void
idt77252_rx_raw(struct idt77252_dev *card)1238 idt77252_rx_raw(struct idt77252_dev *card)
1239 {
1240 struct sk_buff *queue;
1241 u32 head, tail;
1242 struct atm_vcc *vcc;
1243 struct vc_map *vc;
1244 struct sk_buff *sb;
1245
1246 if (card->raw_cell_head == NULL) {
1247 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1248 card->raw_cell_head = sb_pool_skb(card, handle);
1249 }
1250
1251 queue = card->raw_cell_head;
1252 if (!queue)
1253 return;
1254
1255 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1256 tail = readl(SAR_REG_RAWCT);
1257
1258 dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue),
1259 skb_end_offset(queue) - 16,
1260 DMA_FROM_DEVICE);
1261
1262 while (head != tail) {
1263 unsigned int vpi, vci;
1264 u32 header;
1265
1266 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1267
1268 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1269 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1270
1271 #ifdef CONFIG_ATM_IDT77252_DEBUG
1272 if (debug & DBG_RAW_CELL) {
1273 int i;
1274
1275 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1276 card->name, (header >> 28) & 0x000f,
1277 (header >> 20) & 0x00ff,
1278 (header >> 4) & 0xffff,
1279 (header >> 1) & 0x0007,
1280 (header >> 0) & 0x0001);
1281 for (i = 16; i < 64; i++)
1282 printk(" %02x", queue->data[i]);
1283 printk("\n");
1284 }
1285 #endif
1286
1287 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1288 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1289 card->name, vpi, vci);
1290 goto drop;
1291 }
1292
1293 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1294 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1295 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1296 card->name, vpi, vci);
1297 goto drop;
1298 }
1299
1300 vcc = vc->rx_vcc;
1301
1302 if (vcc->qos.aal != ATM_AAL0) {
1303 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1304 card->name, vpi, vci);
1305 atomic_inc(&vcc->stats->rx_drop);
1306 goto drop;
1307 }
1308
1309 if ((sb = dev_alloc_skb(64)) == NULL) {
1310 printk("%s: Can't allocate buffers for AAL0.\n",
1311 card->name);
1312 atomic_inc(&vcc->stats->rx_err);
1313 goto drop;
1314 }
1315
1316 if (!atm_charge(vcc, sb->truesize)) {
1317 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1318 card->name);
1319 dev_kfree_skb(sb);
1320 goto drop;
1321 }
1322
1323 *((u32 *) sb->data) = header;
1324 skb_put(sb, sizeof(u32));
1325 skb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD);
1326
1327 ATM_SKB(sb)->vcc = vcc;
1328 __net_timestamp(sb);
1329 vcc->push(vcc, sb);
1330 atomic_inc(&vcc->stats->rx);
1331
1332 drop:
1333 skb_pull(queue, 64);
1334
1335 head = IDT77252_PRV_PADDR(queue)
1336 + (queue->data - queue->head - 16);
1337
1338 if (queue->len < 128) {
1339 struct sk_buff *next;
1340 u32 handle;
1341
1342 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1343 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1344
1345 next = sb_pool_skb(card, handle);
1346 recycle_rx_skb(card, queue);
1347
1348 if (next) {
1349 card->raw_cell_head = next;
1350 queue = card->raw_cell_head;
1351 dma_sync_single_for_cpu(&card->pcidev->dev,
1352 IDT77252_PRV_PADDR(queue),
1353 (skb_end_pointer(queue) -
1354 queue->data),
1355 DMA_FROM_DEVICE);
1356 } else {
1357 card->raw_cell_head = NULL;
1358 printk("%s: raw cell queue overrun\n",
1359 card->name);
1360 break;
1361 }
1362 }
1363 }
1364 }
1365
1366
1367 /*****************************************************************************/
1368 /* */
1369 /* TSQ Handling */
1370 /* */
1371 /*****************************************************************************/
1372
1373 static int
init_tsq(struct idt77252_dev *card)1374 init_tsq(struct idt77252_dev *card)
1375 {
1376 struct tsq_entry *tsqe;
1377
1378 card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
1379 &card->tsq.paddr, GFP_KERNEL);
1380 if (card->tsq.base == NULL) {
1381 printk("%s: can't allocate TSQ.\n", card->name);
1382 return -1;
1383 }
1384
1385 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1386 card->tsq.next = card->tsq.last;
1387 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1388 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1389
1390 writel(card->tsq.paddr, SAR_REG_TSQB);
1391 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1392 SAR_REG_TSQH);
1393
1394 return 0;
1395 }
1396
1397 static void
deinit_tsq(struct idt77252_dev *card)1398 deinit_tsq(struct idt77252_dev *card)
1399 {
1400 dma_free_coherent(&card->pcidev->dev, TSQSIZE,
1401 card->tsq.base, card->tsq.paddr);
1402 }
1403
1404 static void
idt77252_tx(struct idt77252_dev *card)1405 idt77252_tx(struct idt77252_dev *card)
1406 {
1407 struct tsq_entry *tsqe;
1408 unsigned int vpi, vci;
1409 struct vc_map *vc;
1410 u32 conn, stat;
1411
1412 if (card->tsq.next == card->tsq.last)
1413 tsqe = card->tsq.base;
1414 else
1415 tsqe = card->tsq.next + 1;
1416
1417 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1418 card->tsq.base, card->tsq.next, card->tsq.last);
1419 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1420 readl(SAR_REG_TSQB),
1421 readl(SAR_REG_TSQT),
1422 readl(SAR_REG_TSQH));
1423
1424 stat = le32_to_cpu(tsqe->word_2);
1425
1426 if (stat & SAR_TSQE_INVALID)
1427 return;
1428
1429 do {
1430 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1431 le32_to_cpu(tsqe->word_1),
1432 le32_to_cpu(tsqe->word_2));
1433
1434 switch (stat & SAR_TSQE_TYPE) {
1435 case SAR_TSQE_TYPE_TIMER:
1436 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1437 break;
1438
1439 case SAR_TSQE_TYPE_IDLE:
1440
1441 conn = le32_to_cpu(tsqe->word_1);
1442
1443 if (SAR_TSQE_TAG(stat) == 0x10) {
1444 #ifdef NOTDEF
1445 printk("%s: Connection %d halted.\n",
1446 card->name,
1447 le32_to_cpu(tsqe->word_1) & 0x1fff);
1448 #endif
1449 break;
1450 }
1451
1452 vc = card->vcs[conn & 0x1fff];
1453 if (!vc) {
1454 printk("%s: could not find VC from conn %d\n",
1455 card->name, conn & 0x1fff);
1456 break;
1457 }
1458
1459 printk("%s: Connection %d IDLE.\n",
1460 card->name, vc->index);
1461
1462 set_bit(VCF_IDLE, &vc->flags);
1463 break;
1464
1465 case SAR_TSQE_TYPE_TSR:
1466
1467 conn = le32_to_cpu(tsqe->word_1);
1468
1469 vc = card->vcs[conn & 0x1fff];
1470 if (!vc) {
1471 printk("%s: no VC at index %d\n",
1472 card->name,
1473 le32_to_cpu(tsqe->word_1) & 0x1fff);
1474 break;
1475 }
1476
1477 drain_scq(card, vc);
1478 break;
1479
1480 case SAR_TSQE_TYPE_TBD_COMP:
1481
1482 conn = le32_to_cpu(tsqe->word_1);
1483
1484 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1485 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1486
1487 if (vpi >= (1 << card->vpibits) ||
1488 vci >= (1 << card->vcibits)) {
1489 printk("%s: TBD complete: "
1490 "out of range VPI.VCI %u.%u\n",
1491 card->name, vpi, vci);
1492 break;
1493 }
1494
1495 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1496 if (!vc) {
1497 printk("%s: TBD complete: "
1498 "no VC at VPI.VCI %u.%u\n",
1499 card->name, vpi, vci);
1500 break;
1501 }
1502
1503 drain_scq(card, vc);
1504 break;
1505 }
1506
1507 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1508
1509 card->tsq.next = tsqe;
1510 if (card->tsq.next == card->tsq.last)
1511 tsqe = card->tsq.base;
1512 else
1513 tsqe = card->tsq.next + 1;
1514
1515 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1516 card->tsq.base, card->tsq.next, card->tsq.last);
1517
1518 stat = le32_to_cpu(tsqe->word_2);
1519
1520 } while (!(stat & SAR_TSQE_INVALID));
1521
1522 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1523 SAR_REG_TSQH);
1524
1525 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1526 card->index, readl(SAR_REG_TSQH),
1527 readl(SAR_REG_TSQT), card->tsq.next);
1528 }
1529
1530
1531 static void
tst_timer(struct timer_list *t)1532 tst_timer(struct timer_list *t)
1533 {
1534 struct idt77252_dev *card = from_timer(card, t, tst_timer);
1535 unsigned long base, idle, jump;
1536 unsigned long flags;
1537 u32 pc;
1538 int e;
1539
1540 spin_lock_irqsave(&card->tst_lock, flags);
1541
1542 base = card->tst[card->tst_index];
1543 idle = card->tst[card->tst_index ^ 1];
1544
1545 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1546 jump = base + card->tst_size - 2;
1547
1548 pc = readl(SAR_REG_NOW) >> 2;
1549 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1550 mod_timer(&card->tst_timer, jiffies + 1);
1551 goto out;
1552 }
1553
1554 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1555
1556 card->tst_index ^= 1;
1557 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1558
1559 base = card->tst[card->tst_index];
1560 idle = card->tst[card->tst_index ^ 1];
1561
1562 for (e = 0; e < card->tst_size - 2; e++) {
1563 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1564 write_sram(card, idle + e,
1565 card->soft_tst[e].tste & TSTE_MASK);
1566 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1567 }
1568 }
1569 }
1570
1571 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1572
1573 for (e = 0; e < card->tst_size - 2; e++) {
1574 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1575 write_sram(card, idle + e,
1576 card->soft_tst[e].tste & TSTE_MASK);
1577 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1578 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1579 }
1580 }
1581
1582 jump = base + card->tst_size - 2;
1583
1584 write_sram(card, jump, TSTE_OPC_NULL);
1585 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1586
1587 mod_timer(&card->tst_timer, jiffies + 1);
1588 }
1589
1590 out:
1591 spin_unlock_irqrestore(&card->tst_lock, flags);
1592 }
1593
1594 static int
__fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)1595 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1596 int n, unsigned int opc)
1597 {
1598 unsigned long cl, avail;
1599 unsigned long idle;
1600 int e, r;
1601 u32 data;
1602
1603 avail = card->tst_size - 2;
1604 for (e = 0; e < avail; e++) {
1605 if (card->soft_tst[e].vc == NULL)
1606 break;
1607 }
1608 if (e >= avail) {
1609 printk("%s: No free TST entries found\n", card->name);
1610 return -1;
1611 }
1612
1613 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1614 card->name, vc ? vc->index : -1, e);
1615
1616 r = n;
1617 cl = avail;
1618 data = opc & TSTE_OPC_MASK;
1619 if (vc && (opc != TSTE_OPC_NULL))
1620 data = opc | vc->index;
1621
1622 idle = card->tst[card->tst_index ^ 1];
1623
1624 /*
1625 * Fill Soft TST.
1626 */
1627 while (r > 0) {
1628 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1629 if (vc)
1630 card->soft_tst[e].vc = vc;
1631 else
1632 card->soft_tst[e].vc = (void *)-1;
1633
1634 card->soft_tst[e].tste = data;
1635 if (timer_pending(&card->tst_timer))
1636 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1637 else {
1638 write_sram(card, idle + e, data);
1639 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1640 }
1641
1642 cl -= card->tst_size;
1643 r--;
1644 }
1645
1646 if (++e == avail)
1647 e = 0;
1648 cl += n;
1649 }
1650
1651 return 0;
1652 }
1653
1654 static int
fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)1655 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1656 {
1657 unsigned long flags;
1658 int res;
1659
1660 spin_lock_irqsave(&card->tst_lock, flags);
1661
1662 res = __fill_tst(card, vc, n, opc);
1663
1664 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1665 if (!timer_pending(&card->tst_timer))
1666 mod_timer(&card->tst_timer, jiffies + 1);
1667
1668 spin_unlock_irqrestore(&card->tst_lock, flags);
1669 return res;
1670 }
1671
1672 static int
__clear_tst(struct idt77252_dev *card, struct vc_map *vc)1673 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1674 {
1675 unsigned long idle;
1676 int e;
1677
1678 idle = card->tst[card->tst_index ^ 1];
1679
1680 for (e = 0; e < card->tst_size - 2; e++) {
1681 if (card->soft_tst[e].vc == vc) {
1682 card->soft_tst[e].vc = NULL;
1683
1684 card->soft_tst[e].tste = TSTE_OPC_VAR;
1685 if (timer_pending(&card->tst_timer))
1686 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1687 else {
1688 write_sram(card, idle + e, TSTE_OPC_VAR);
1689 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1690 }
1691 }
1692 }
1693
1694 return 0;
1695 }
1696
1697 static int
clear_tst(struct idt77252_dev *card, struct vc_map *vc)1698 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1699 {
1700 unsigned long flags;
1701 int res;
1702
1703 spin_lock_irqsave(&card->tst_lock, flags);
1704
1705 res = __clear_tst(card, vc);
1706
1707 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1708 if (!timer_pending(&card->tst_timer))
1709 mod_timer(&card->tst_timer, jiffies + 1);
1710
1711 spin_unlock_irqrestore(&card->tst_lock, flags);
1712 return res;
1713 }
1714
1715 static int
change_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)1716 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1717 int n, unsigned int opc)
1718 {
1719 unsigned long flags;
1720 int res;
1721
1722 spin_lock_irqsave(&card->tst_lock, flags);
1723
1724 __clear_tst(card, vc);
1725 res = __fill_tst(card, vc, n, opc);
1726
1727 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1728 if (!timer_pending(&card->tst_timer))
1729 mod_timer(&card->tst_timer, jiffies + 1);
1730
1731 spin_unlock_irqrestore(&card->tst_lock, flags);
1732 return res;
1733 }
1734
1735
1736 static int
set_tct(struct idt77252_dev *card, struct vc_map *vc)1737 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1738 {
1739 unsigned long tct;
1740
1741 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1742
1743 switch (vc->class) {
1744 case SCHED_CBR:
1745 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1746 card->name, tct, vc->scq->scd);
1747
1748 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1749 write_sram(card, tct + 1, 0);
1750 write_sram(card, tct + 2, 0);
1751 write_sram(card, tct + 3, 0);
1752 write_sram(card, tct + 4, 0);
1753 write_sram(card, tct + 5, 0);
1754 write_sram(card, tct + 6, 0);
1755 write_sram(card, tct + 7, 0);
1756 break;
1757
1758 case SCHED_UBR:
1759 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1760 card->name, tct, vc->scq->scd);
1761
1762 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1763 write_sram(card, tct + 1, 0);
1764 write_sram(card, tct + 2, TCT_TSIF);
1765 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1766 write_sram(card, tct + 4, 0);
1767 write_sram(card, tct + 5, vc->init_er);
1768 write_sram(card, tct + 6, 0);
1769 write_sram(card, tct + 7, TCT_FLAG_UBR);
1770 break;
1771
1772 case SCHED_VBR:
1773 case SCHED_ABR:
1774 default:
1775 return -ENOSYS;
1776 }
1777
1778 return 0;
1779 }
1780
1781 /*****************************************************************************/
1782 /* */
1783 /* FBQ Handling */
1784 /* */
1785 /*****************************************************************************/
1786
1787 static __inline__ int
idt77252_fbq_level(struct idt77252_dev *card, int queue)1788 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1789 {
1790 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1791 }
1792
1793 static __inline__ int
idt77252_fbq_full(struct idt77252_dev *card, int queue)1794 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1795 {
1796 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1797 }
1798
1799 static int
push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)1800 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1801 {
1802 unsigned long flags;
1803 u32 handle;
1804 u32 addr;
1805
1806 skb->data = skb->head;
1807 skb_reset_tail_pointer(skb);
1808 skb->len = 0;
1809
1810 skb_reserve(skb, 16);
1811
1812 switch (queue) {
1813 case 0:
1814 skb_put(skb, SAR_FB_SIZE_0);
1815 break;
1816 case 1:
1817 skb_put(skb, SAR_FB_SIZE_1);
1818 break;
1819 case 2:
1820 skb_put(skb, SAR_FB_SIZE_2);
1821 break;
1822 case 3:
1823 skb_put(skb, SAR_FB_SIZE_3);
1824 break;
1825 default:
1826 return -1;
1827 }
1828
1829 if (idt77252_fbq_full(card, queue))
1830 return -1;
1831
1832 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1833
1834 handle = IDT77252_PRV_POOL(skb);
1835 addr = IDT77252_PRV_PADDR(skb);
1836
1837 spin_lock_irqsave(&card->cmd_lock, flags);
1838 writel(handle, card->fbq[queue]);
1839 writel(addr, card->fbq[queue]);
1840 spin_unlock_irqrestore(&card->cmd_lock, flags);
1841
1842 return 0;
1843 }
1844
1845 static void
add_rx_skb(struct idt77252_dev *card, int queue, unsigned int size, unsigned int count)1846 add_rx_skb(struct idt77252_dev *card, int queue,
1847 unsigned int size, unsigned int count)
1848 {
1849 struct sk_buff *skb;
1850 dma_addr_t paddr;
1851 u32 handle;
1852
1853 while (count--) {
1854 skb = dev_alloc_skb(size);
1855 if (!skb)
1856 return;
1857
1858 if (sb_pool_add(card, skb, queue)) {
1859 printk("%s: SB POOL full\n", __func__);
1860 goto outfree;
1861 }
1862
1863 paddr = dma_map_single(&card->pcidev->dev, skb->data,
1864 skb_end_pointer(skb) - skb->data,
1865 DMA_FROM_DEVICE);
1866 IDT77252_PRV_PADDR(skb) = paddr;
1867
1868 if (push_rx_skb(card, skb, queue)) {
1869 printk("%s: FB QUEUE full\n", __func__);
1870 goto outunmap;
1871 }
1872 }
1873
1874 return;
1875
1876 outunmap:
1877 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1878 skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
1879
1880 handle = IDT77252_PRV_POOL(skb);
1881 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1882
1883 outfree:
1884 dev_kfree_skb(skb);
1885 }
1886
1887
1888 static void
recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)1889 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1890 {
1891 u32 handle = IDT77252_PRV_POOL(skb);
1892 int err;
1893
1894 dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1895 skb_end_pointer(skb) - skb->data,
1896 DMA_FROM_DEVICE);
1897
1898 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1899 if (err) {
1900 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1901 skb_end_pointer(skb) - skb->data,
1902 DMA_FROM_DEVICE);
1903 sb_pool_remove(card, skb);
1904 dev_kfree_skb(skb);
1905 }
1906 }
1907
1908 static void
flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)1909 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1910 {
1911 skb_queue_head_init(&rpp->queue);
1912 rpp->len = 0;
1913 }
1914
1915 static void
recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)1916 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1917 {
1918 struct sk_buff *skb, *tmp;
1919
1920 skb_queue_walk_safe(&rpp->queue, skb, tmp)
1921 recycle_rx_skb(card, skb);
1922
1923 flush_rx_pool(card, rpp);
1924 }
1925
1926 /*****************************************************************************/
1927 /* */
1928 /* ATM Interface */
1929 /* */
1930 /*****************************************************************************/
1931
1932 static void
idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)1933 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1934 {
1935 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1936 }
1937
1938 static unsigned char
idt77252_phy_get(struct atm_dev *dev, unsigned long addr)1939 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1940 {
1941 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1942 }
1943
1944 static inline int
idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)1945 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1946 {
1947 struct atm_dev *dev = vcc->dev;
1948 struct idt77252_dev *card = dev->dev_data;
1949 struct vc_map *vc = vcc->dev_data;
1950 int err;
1951
1952 if (vc == NULL) {
1953 printk("%s: NULL connection in send().\n", card->name);
1954 atomic_inc(&vcc->stats->tx_err);
1955 dev_kfree_skb(skb);
1956 return -EINVAL;
1957 }
1958 if (!test_bit(VCF_TX, &vc->flags)) {
1959 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1960 atomic_inc(&vcc->stats->tx_err);
1961 dev_kfree_skb(skb);
1962 return -EINVAL;
1963 }
1964
1965 switch (vcc->qos.aal) {
1966 case ATM_AAL0:
1967 case ATM_AAL1:
1968 case ATM_AAL5:
1969 break;
1970 default:
1971 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1972 atomic_inc(&vcc->stats->tx_err);
1973 dev_kfree_skb(skb);
1974 return -EINVAL;
1975 }
1976
1977 if (skb_shinfo(skb)->nr_frags != 0) {
1978 printk("%s: No scatter-gather yet.\n", card->name);
1979 atomic_inc(&vcc->stats->tx_err);
1980 dev_kfree_skb(skb);
1981 return -EINVAL;
1982 }
1983 ATM_SKB(skb)->vcc = vcc;
1984
1985 err = queue_skb(card, vc, skb, oam);
1986 if (err) {
1987 atomic_inc(&vcc->stats->tx_err);
1988 dev_kfree_skb(skb);
1989 return err;
1990 }
1991
1992 return 0;
1993 }
1994
idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)1995 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
1996 {
1997 return idt77252_send_skb(vcc, skb, 0);
1998 }
1999
2000 static int
idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)2001 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2002 {
2003 struct atm_dev *dev = vcc->dev;
2004 struct idt77252_dev *card = dev->dev_data;
2005 struct sk_buff *skb;
2006
2007 skb = dev_alloc_skb(64);
2008 if (!skb) {
2009 printk("%s: Out of memory in send_oam().\n", card->name);
2010 atomic_inc(&vcc->stats->tx_err);
2011 return -ENOMEM;
2012 }
2013 refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2014
2015 skb_put_data(skb, cell, 52);
2016
2017 return idt77252_send_skb(vcc, skb, 1);
2018 }
2019
2020 static __inline__ unsigned int
idt77252_fls(unsigned int x)2021 idt77252_fls(unsigned int x)
2022 {
2023 int r = 1;
2024
2025 if (x == 0)
2026 return 0;
2027 if (x & 0xffff0000) {
2028 x >>= 16;
2029 r += 16;
2030 }
2031 if (x & 0xff00) {
2032 x >>= 8;
2033 r += 8;
2034 }
2035 if (x & 0xf0) {
2036 x >>= 4;
2037 r += 4;
2038 }
2039 if (x & 0xc) {
2040 x >>= 2;
2041 r += 2;
2042 }
2043 if (x & 0x2)
2044 r += 1;
2045 return r;
2046 }
2047
2048 static u16
idt77252_int_to_atmfp(unsigned int rate)2049 idt77252_int_to_atmfp(unsigned int rate)
2050 {
2051 u16 m, e;
2052
2053 if (rate == 0)
2054 return 0;
2055 e = idt77252_fls(rate) - 1;
2056 if (e < 9)
2057 m = (rate - (1 << e)) << (9 - e);
2058 else if (e == 9)
2059 m = (rate - (1 << e));
2060 else /* e > 9 */
2061 m = (rate - (1 << e)) >> (e - 9);
2062 return 0x4000 | (e << 9) | m;
2063 }
2064
2065 static u8
idt77252_rate_logindex(struct idt77252_dev *card, int pcr)2066 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2067 {
2068 u16 afp;
2069
2070 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2071 if (pcr < 0)
2072 return rate_to_log[(afp >> 5) & 0x1ff];
2073 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2074 }
2075
2076 static void
idt77252_est_timer(struct timer_list *t)2077 idt77252_est_timer(struct timer_list *t)
2078 {
2079 struct rate_estimator *est = from_timer(est, t, timer);
2080 struct vc_map *vc = est->vc;
2081 struct idt77252_dev *card = vc->card;
2082 unsigned long flags;
2083 u32 rate, cps;
2084 u64 ncells;
2085 u8 lacr;
2086
2087 spin_lock_irqsave(&vc->lock, flags);
2088 if (!vc->estimator)
2089 goto out;
2090 ncells = est->cells;
2091
2092 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2093 est->last_cells = ncells;
2094 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2095 est->cps = (est->avcps + 0x1f) >> 5;
2096
2097 cps = est->cps;
2098 if (cps < (est->maxcps >> 4))
2099 cps = est->maxcps >> 4;
2100
2101 lacr = idt77252_rate_logindex(card, cps);
2102 if (lacr > vc->max_er)
2103 lacr = vc->max_er;
2104
2105 if (lacr != vc->lacr) {
2106 vc->lacr = lacr;
2107 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2108 }
2109
2110 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2111 add_timer(&est->timer);
2112
2113 out:
2114 spin_unlock_irqrestore(&vc->lock, flags);
2115 }
2116
2117 static struct rate_estimator *
idt77252_init_est(struct vc_map *vc, int pcr)2118 idt77252_init_est(struct vc_map *vc, int pcr)
2119 {
2120 struct rate_estimator *est;
2121
2122 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2123 if (!est)
2124 return NULL;
2125 est->maxcps = pcr < 0 ? -pcr : pcr;
2126 est->cps = est->maxcps;
2127 est->avcps = est->cps << 5;
2128 est->vc = vc;
2129
2130 est->interval = 2; /* XXX: make this configurable */
2131 est->ewma_log = 2; /* XXX: make this configurable */
2132 timer_setup(&est->timer, idt77252_est_timer, 0);
2133 mod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval));
2134
2135 return est;
2136 }
2137
2138 static int
idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, struct atm_vcc *vcc, struct atm_qos *qos)2139 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2140 struct atm_vcc *vcc, struct atm_qos *qos)
2141 {
2142 int tst_free, tst_used, tst_entries;
2143 unsigned long tmpl, modl;
2144 int tcr, tcra;
2145
2146 if ((qos->txtp.max_pcr == 0) &&
2147 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2148 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2149 card->name);
2150 return -EINVAL;
2151 }
2152
2153 tst_used = 0;
2154 tst_free = card->tst_free;
2155 if (test_bit(VCF_TX, &vc->flags))
2156 tst_used = vc->ntste;
2157 tst_free += tst_used;
2158
2159 tcr = atm_pcr_goal(&qos->txtp);
2160 tcra = tcr >= 0 ? tcr : -tcr;
2161
2162 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2163
2164 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2165 modl = tmpl % (unsigned long)card->utopia_pcr;
2166
2167 tst_entries = (int) (tmpl / card->utopia_pcr);
2168 if (tcr > 0) {
2169 if (modl > 0)
2170 tst_entries++;
2171 } else if (tcr == 0) {
2172 tst_entries = tst_free - SAR_TST_RESERVED;
2173 if (tst_entries <= 0) {
2174 printk("%s: no CBR bandwidth free.\n", card->name);
2175 return -ENOSR;
2176 }
2177 }
2178
2179 if (tst_entries == 0) {
2180 printk("%s: selected CBR bandwidth < granularity.\n",
2181 card->name);
2182 return -EINVAL;
2183 }
2184
2185 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2186 printk("%s: not enough CBR bandwidth free.\n", card->name);
2187 return -ENOSR;
2188 }
2189
2190 vc->ntste = tst_entries;
2191
2192 card->tst_free = tst_free - tst_entries;
2193 if (test_bit(VCF_TX, &vc->flags)) {
2194 if (tst_used == tst_entries)
2195 return 0;
2196
2197 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2198 card->name, tst_used, tst_entries);
2199 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2200 return 0;
2201 }
2202
2203 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2204 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2205 return 0;
2206 }
2207
2208 static int
idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, struct atm_vcc *vcc, struct atm_qos *qos)2209 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2210 struct atm_vcc *vcc, struct atm_qos *qos)
2211 {
2212 struct rate_estimator *est = NULL;
2213 unsigned long flags;
2214 int tcr;
2215
2216 spin_lock_irqsave(&vc->lock, flags);
2217 if (vc->estimator) {
2218 est = vc->estimator;
2219 vc->estimator = NULL;
2220 }
2221 spin_unlock_irqrestore(&vc->lock, flags);
2222 if (est) {
2223 del_timer_sync(&est->timer);
2224 kfree(est);
2225 }
2226
2227 tcr = atm_pcr_goal(&qos->txtp);
2228 if (tcr == 0)
2229 tcr = card->link_pcr;
2230
2231 vc->estimator = idt77252_init_est(vc, tcr);
2232
2233 vc->class = SCHED_UBR;
2234 vc->init_er = idt77252_rate_logindex(card, tcr);
2235 vc->lacr = vc->init_er;
2236 if (tcr < 0)
2237 vc->max_er = vc->init_er;
2238 else
2239 vc->max_er = 0xff;
2240
2241 return 0;
2242 }
2243
2244 static int
idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, struct atm_vcc *vcc, struct atm_qos *qos)2245 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2246 struct atm_vcc *vcc, struct atm_qos *qos)
2247 {
2248 int error;
2249
2250 if (test_bit(VCF_TX, &vc->flags))
2251 return -EBUSY;
2252
2253 switch (qos->txtp.traffic_class) {
2254 case ATM_CBR:
2255 vc->class = SCHED_CBR;
2256 break;
2257
2258 case ATM_UBR:
2259 vc->class = SCHED_UBR;
2260 break;
2261
2262 case ATM_VBR:
2263 case ATM_ABR:
2264 default:
2265 return -EPROTONOSUPPORT;
2266 }
2267
2268 vc->scq = alloc_scq(card, vc->class);
2269 if (!vc->scq) {
2270 printk("%s: can't get SCQ.\n", card->name);
2271 return -ENOMEM;
2272 }
2273
2274 vc->scq->scd = get_free_scd(card, vc);
2275 if (vc->scq->scd == 0) {
2276 printk("%s: no SCD available.\n", card->name);
2277 free_scq(card, vc->scq);
2278 return -ENOMEM;
2279 }
2280
2281 fill_scd(card, vc->scq, vc->class);
2282
2283 if (set_tct(card, vc)) {
2284 printk("%s: class %d not supported.\n",
2285 card->name, qos->txtp.traffic_class);
2286
2287 card->scd2vc[vc->scd_index] = NULL;
2288 free_scq(card, vc->scq);
2289 return -EPROTONOSUPPORT;
2290 }
2291
2292 switch (vc->class) {
2293 case SCHED_CBR:
2294 error = idt77252_init_cbr(card, vc, vcc, qos);
2295 if (error) {
2296 card->scd2vc[vc->scd_index] = NULL;
2297 free_scq(card, vc->scq);
2298 return error;
2299 }
2300
2301 clear_bit(VCF_IDLE, &vc->flags);
2302 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2303 break;
2304
2305 case SCHED_UBR:
2306 error = idt77252_init_ubr(card, vc, vcc, qos);
2307 if (error) {
2308 card->scd2vc[vc->scd_index] = NULL;
2309 free_scq(card, vc->scq);
2310 return error;
2311 }
2312
2313 set_bit(VCF_IDLE, &vc->flags);
2314 break;
2315 }
2316
2317 vc->tx_vcc = vcc;
2318 set_bit(VCF_TX, &vc->flags);
2319 return 0;
2320 }
2321
2322 static int
idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, struct atm_vcc *vcc, struct atm_qos *qos)2323 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2324 struct atm_vcc *vcc, struct atm_qos *qos)
2325 {
2326 unsigned long flags;
2327 unsigned long addr;
2328 u32 rcte = 0;
2329
2330 if (test_bit(VCF_RX, &vc->flags))
2331 return -EBUSY;
2332
2333 vc->rx_vcc = vcc;
2334 set_bit(VCF_RX, &vc->flags);
2335
2336 if ((vcc->vci == 3) || (vcc->vci == 4))
2337 return 0;
2338
2339 flush_rx_pool(card, &vc->rcv.rx_pool);
2340
2341 rcte |= SAR_RCTE_CONNECTOPEN;
2342 rcte |= SAR_RCTE_RAWCELLINTEN;
2343
2344 switch (qos->aal) {
2345 case ATM_AAL0:
2346 rcte |= SAR_RCTE_RCQ;
2347 break;
2348 case ATM_AAL1:
2349 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2350 break;
2351 case ATM_AAL34:
2352 rcte |= SAR_RCTE_AAL34;
2353 break;
2354 case ATM_AAL5:
2355 rcte |= SAR_RCTE_AAL5;
2356 break;
2357 default:
2358 rcte |= SAR_RCTE_RCQ;
2359 break;
2360 }
2361
2362 if (qos->aal != ATM_AAL5)
2363 rcte |= SAR_RCTE_FBP_1;
2364 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2365 rcte |= SAR_RCTE_FBP_3;
2366 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2367 rcte |= SAR_RCTE_FBP_2;
2368 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2369 rcte |= SAR_RCTE_FBP_1;
2370 else
2371 rcte |= SAR_RCTE_FBP_01;
2372
2373 addr = card->rct_base + (vc->index << 2);
2374
2375 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2376 write_sram(card, addr, rcte);
2377
2378 spin_lock_irqsave(&card->cmd_lock, flags);
2379 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2380 waitfor_idle(card);
2381 spin_unlock_irqrestore(&card->cmd_lock, flags);
2382
2383 return 0;
2384 }
2385
2386 static int
idt77252_open(struct atm_vcc *vcc)2387 idt77252_open(struct atm_vcc *vcc)
2388 {
2389 struct atm_dev *dev = vcc->dev;
2390 struct idt77252_dev *card = dev->dev_data;
2391 struct vc_map *vc;
2392 unsigned int index;
2393 unsigned int inuse;
2394 int error;
2395 int vci = vcc->vci;
2396 short vpi = vcc->vpi;
2397
2398 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2399 return 0;
2400
2401 if (vpi >= (1 << card->vpibits)) {
2402 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2403 return -EINVAL;
2404 }
2405
2406 if (vci >= (1 << card->vcibits)) {
2407 printk("%s: unsupported VCI: %d\n", card->name, vci);
2408 return -EINVAL;
2409 }
2410
2411 set_bit(ATM_VF_ADDR, &vcc->flags);
2412
2413 mutex_lock(&card->mutex);
2414
2415 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2416
2417 switch (vcc->qos.aal) {
2418 case ATM_AAL0:
2419 case ATM_AAL1:
2420 case ATM_AAL5:
2421 break;
2422 default:
2423 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2424 mutex_unlock(&card->mutex);
2425 return -EPROTONOSUPPORT;
2426 }
2427
2428 index = VPCI2VC(card, vpi, vci);
2429 if (!card->vcs[index]) {
2430 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2431 if (!card->vcs[index]) {
2432 printk("%s: can't alloc vc in open()\n", card->name);
2433 mutex_unlock(&card->mutex);
2434 return -ENOMEM;
2435 }
2436 card->vcs[index]->card = card;
2437 card->vcs[index]->index = index;
2438
2439 spin_lock_init(&card->vcs[index]->lock);
2440 }
2441 vc = card->vcs[index];
2442
2443 vcc->dev_data = vc;
2444
2445 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2446 card->name, vc->index, vcc->vpi, vcc->vci,
2447 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2448 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2449 vcc->qos.rxtp.max_sdu);
2450
2451 inuse = 0;
2452 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2453 test_bit(VCF_TX, &vc->flags))
2454 inuse = 1;
2455 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2456 test_bit(VCF_RX, &vc->flags))
2457 inuse += 2;
2458
2459 if (inuse) {
2460 printk("%s: %s vci already in use.\n", card->name,
2461 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2462 mutex_unlock(&card->mutex);
2463 return -EADDRINUSE;
2464 }
2465
2466 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2467 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2468 if (error) {
2469 mutex_unlock(&card->mutex);
2470 return error;
2471 }
2472 }
2473
2474 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2475 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2476 if (error) {
2477 mutex_unlock(&card->mutex);
2478 return error;
2479 }
2480 }
2481
2482 set_bit(ATM_VF_READY, &vcc->flags);
2483
2484 mutex_unlock(&card->mutex);
2485 return 0;
2486 }
2487
2488 static void
idt77252_close(struct atm_vcc *vcc)2489 idt77252_close(struct atm_vcc *vcc)
2490 {
2491 struct atm_dev *dev = vcc->dev;
2492 struct idt77252_dev *card = dev->dev_data;
2493 struct vc_map *vc = vcc->dev_data;
2494 unsigned long flags;
2495 unsigned long addr;
2496 unsigned long timeout;
2497
2498 mutex_lock(&card->mutex);
2499
2500 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2501 card->name, vc->index, vcc->vpi, vcc->vci);
2502
2503 clear_bit(ATM_VF_READY, &vcc->flags);
2504
2505 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2506
2507 spin_lock_irqsave(&vc->lock, flags);
2508 clear_bit(VCF_RX, &vc->flags);
2509 vc->rx_vcc = NULL;
2510 spin_unlock_irqrestore(&vc->lock, flags);
2511
2512 if ((vcc->vci == 3) || (vcc->vci == 4))
2513 goto done;
2514
2515 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2516
2517 spin_lock_irqsave(&card->cmd_lock, flags);
2518 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2519 waitfor_idle(card);
2520 spin_unlock_irqrestore(&card->cmd_lock, flags);
2521
2522 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2523 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2524 card->name);
2525
2526 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2527 }
2528 }
2529
2530 done:
2531 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2532
2533 spin_lock_irqsave(&vc->lock, flags);
2534 clear_bit(VCF_TX, &vc->flags);
2535 clear_bit(VCF_IDLE, &vc->flags);
2536 clear_bit(VCF_RSV, &vc->flags);
2537 vc->tx_vcc = NULL;
2538
2539 if (vc->estimator) {
2540 del_timer(&vc->estimator->timer);
2541 kfree(vc->estimator);
2542 vc->estimator = NULL;
2543 }
2544 spin_unlock_irqrestore(&vc->lock, flags);
2545
2546 timeout = 5 * 1000;
2547 while (atomic_read(&vc->scq->used) > 0) {
2548 timeout = msleep_interruptible(timeout);
2549 if (!timeout) {
2550 pr_warn("%s: SCQ drain timeout: %u used\n",
2551 card->name, atomic_read(&vc->scq->used));
2552 break;
2553 }
2554 }
2555
2556 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2557 clear_scd(card, vc->scq, vc->class);
2558
2559 if (vc->class == SCHED_CBR) {
2560 clear_tst(card, vc);
2561 card->tst_free += vc->ntste;
2562 vc->ntste = 0;
2563 }
2564
2565 card->scd2vc[vc->scd_index] = NULL;
2566 free_scq(card, vc->scq);
2567 }
2568
2569 mutex_unlock(&card->mutex);
2570 }
2571
2572 static int
idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)2573 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2574 {
2575 struct atm_dev *dev = vcc->dev;
2576 struct idt77252_dev *card = dev->dev_data;
2577 struct vc_map *vc = vcc->dev_data;
2578 int error = 0;
2579
2580 mutex_lock(&card->mutex);
2581
2582 if (qos->txtp.traffic_class != ATM_NONE) {
2583 if (!test_bit(VCF_TX, &vc->flags)) {
2584 error = idt77252_init_tx(card, vc, vcc, qos);
2585 if (error)
2586 goto out;
2587 } else {
2588 switch (qos->txtp.traffic_class) {
2589 case ATM_CBR:
2590 error = idt77252_init_cbr(card, vc, vcc, qos);
2591 if (error)
2592 goto out;
2593 break;
2594
2595 case ATM_UBR:
2596 error = idt77252_init_ubr(card, vc, vcc, qos);
2597 if (error)
2598 goto out;
2599
2600 if (!test_bit(VCF_IDLE, &vc->flags)) {
2601 writel(TCMDQ_LACR | (vc->lacr << 16) |
2602 vc->index, SAR_REG_TCMDQ);
2603 }
2604 break;
2605
2606 case ATM_VBR:
2607 case ATM_ABR:
2608 error = -EOPNOTSUPP;
2609 goto out;
2610 }
2611 }
2612 }
2613
2614 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2615 !test_bit(VCF_RX, &vc->flags)) {
2616 error = idt77252_init_rx(card, vc, vcc, qos);
2617 if (error)
2618 goto out;
2619 }
2620
2621 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2622
2623 set_bit(ATM_VF_HASQOS, &vcc->flags);
2624
2625 out:
2626 mutex_unlock(&card->mutex);
2627 return error;
2628 }
2629
2630 static int
idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)2631 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2632 {
2633 struct idt77252_dev *card = dev->dev_data;
2634 int i, left;
2635
2636 left = (int) *pos;
2637 if (!left--)
2638 return sprintf(page, "IDT77252 Interrupts:\n");
2639 if (!left--)
2640 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2641 if (!left--)
2642 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2643 if (!left--)
2644 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2645 if (!left--)
2646 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2647 if (!left--)
2648 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2649 if (!left--)
2650 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2651 if (!left--)
2652 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2653 if (!left--)
2654 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2655 if (!left--)
2656 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2657 if (!left--)
2658 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2659 if (!left--)
2660 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2661 if (!left--)
2662 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2663 if (!left--)
2664 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2665 if (!left--)
2666 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2667
2668 for (i = 0; i < card->tct_size; i++) {
2669 unsigned long tct;
2670 struct atm_vcc *vcc;
2671 struct vc_map *vc;
2672 char *p;
2673
2674 vc = card->vcs[i];
2675 if (!vc)
2676 continue;
2677
2678 vcc = NULL;
2679 if (vc->tx_vcc)
2680 vcc = vc->tx_vcc;
2681 if (!vcc)
2682 continue;
2683 if (left--)
2684 continue;
2685
2686 p = page;
2687 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2688 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2689
2690 for (i = 0; i < 8; i++)
2691 p += sprintf(p, " %08x", read_sram(card, tct + i));
2692 p += sprintf(p, "\n");
2693 return p - page;
2694 }
2695 return 0;
2696 }
2697
2698 /*****************************************************************************/
2699 /* */
2700 /* Interrupt handler */
2701 /* */
2702 /*****************************************************************************/
2703
2704 static void
idt77252_collect_stat(struct idt77252_dev *card)2705 idt77252_collect_stat(struct idt77252_dev *card)
2706 {
2707 (void) readl(SAR_REG_CDC);
2708 (void) readl(SAR_REG_VPEC);
2709 (void) readl(SAR_REG_ICC);
2710
2711 }
2712
2713 static irqreturn_t
idt77252_interrupt(int irq, void *dev_id)2714 idt77252_interrupt(int irq, void *dev_id)
2715 {
2716 struct idt77252_dev *card = dev_id;
2717 u32 stat;
2718
2719 stat = readl(SAR_REG_STAT) & 0xffff;
2720 if (!stat) /* no interrupt for us */
2721 return IRQ_NONE;
2722
2723 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2724 printk("%s: Re-entering irq_handler()\n", card->name);
2725 goto out;
2726 }
2727
2728 writel(stat, SAR_REG_STAT); /* reset interrupt */
2729
2730 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2731 INTPRINTK("%s: TSIF\n", card->name);
2732 card->irqstat[15]++;
2733 idt77252_tx(card);
2734 }
2735 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2736 INTPRINTK("%s: TXICP\n", card->name);
2737 card->irqstat[14]++;
2738 #ifdef CONFIG_ATM_IDT77252_DEBUG
2739 idt77252_tx_dump(card);
2740 #endif
2741 }
2742 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2743 INTPRINTK("%s: TSQF\n", card->name);
2744 card->irqstat[12]++;
2745 idt77252_tx(card);
2746 }
2747 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2748 INTPRINTK("%s: TMROF\n", card->name);
2749 card->irqstat[11]++;
2750 idt77252_collect_stat(card);
2751 }
2752
2753 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2754 INTPRINTK("%s: EPDU\n", card->name);
2755 card->irqstat[5]++;
2756 idt77252_rx(card);
2757 }
2758 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2759 INTPRINTK("%s: RSQAF\n", card->name);
2760 card->irqstat[1]++;
2761 idt77252_rx(card);
2762 }
2763 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2764 INTPRINTK("%s: RSQF\n", card->name);
2765 card->irqstat[6]++;
2766 idt77252_rx(card);
2767 }
2768 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2769 INTPRINTK("%s: RAWCF\n", card->name);
2770 card->irqstat[4]++;
2771 idt77252_rx_raw(card);
2772 }
2773
2774 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2775 INTPRINTK("%s: PHYI", card->name);
2776 card->irqstat[10]++;
2777 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2778 card->atmdev->phy->interrupt(card->atmdev);
2779 }
2780
2781 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2782 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2783
2784 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2785
2786 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2787
2788 if (stat & SAR_STAT_FBQ0A)
2789 card->irqstat[2]++;
2790 if (stat & SAR_STAT_FBQ1A)
2791 card->irqstat[3]++;
2792 if (stat & SAR_STAT_FBQ2A)
2793 card->irqstat[7]++;
2794 if (stat & SAR_STAT_FBQ3A)
2795 card->irqstat[8]++;
2796
2797 schedule_work(&card->tqueue);
2798 }
2799
2800 out:
2801 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2802 return IRQ_HANDLED;
2803 }
2804
2805 static void
idt77252_softint(struct work_struct *work)2806 idt77252_softint(struct work_struct *work)
2807 {
2808 struct idt77252_dev *card =
2809 container_of(work, struct idt77252_dev, tqueue);
2810 u32 stat;
2811 int done;
2812
2813 for (done = 1; ; done = 1) {
2814 stat = readl(SAR_REG_STAT) >> 16;
2815
2816 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2817 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2818 done = 0;
2819 }
2820
2821 stat >>= 4;
2822 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2823 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2824 done = 0;
2825 }
2826
2827 stat >>= 4;
2828 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2829 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2830 done = 0;
2831 }
2832
2833 stat >>= 4;
2834 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2835 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2836 done = 0;
2837 }
2838
2839 if (done)
2840 break;
2841 }
2842
2843 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2844 }
2845
2846
2847 static int
open_card_oam(struct idt77252_dev *card)2848 open_card_oam(struct idt77252_dev *card)
2849 {
2850 unsigned long flags;
2851 unsigned long addr;
2852 struct vc_map *vc;
2853 int vpi, vci;
2854 int index;
2855 u32 rcte;
2856
2857 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2858 for (vci = 3; vci < 5; vci++) {
2859 index = VPCI2VC(card, vpi, vci);
2860
2861 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2862 if (!vc) {
2863 printk("%s: can't alloc vc\n", card->name);
2864 return -ENOMEM;
2865 }
2866 vc->index = index;
2867 card->vcs[index] = vc;
2868
2869 flush_rx_pool(card, &vc->rcv.rx_pool);
2870
2871 rcte = SAR_RCTE_CONNECTOPEN |
2872 SAR_RCTE_RAWCELLINTEN |
2873 SAR_RCTE_RCQ |
2874 SAR_RCTE_FBP_1;
2875
2876 addr = card->rct_base + (vc->index << 2);
2877 write_sram(card, addr, rcte);
2878
2879 spin_lock_irqsave(&card->cmd_lock, flags);
2880 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2881 SAR_REG_CMD);
2882 waitfor_idle(card);
2883 spin_unlock_irqrestore(&card->cmd_lock, flags);
2884 }
2885 }
2886
2887 return 0;
2888 }
2889
2890 static void
close_card_oam(struct idt77252_dev *card)2891 close_card_oam(struct idt77252_dev *card)
2892 {
2893 unsigned long flags;
2894 unsigned long addr;
2895 struct vc_map *vc;
2896 int vpi, vci;
2897 int index;
2898
2899 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2900 for (vci = 3; vci < 5; vci++) {
2901 index = VPCI2VC(card, vpi, vci);
2902 vc = card->vcs[index];
2903
2904 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2905
2906 spin_lock_irqsave(&card->cmd_lock, flags);
2907 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2908 SAR_REG_CMD);
2909 waitfor_idle(card);
2910 spin_unlock_irqrestore(&card->cmd_lock, flags);
2911
2912 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2913 DPRINTK("%s: closing a VC "
2914 "with pending rx buffers.\n",
2915 card->name);
2916
2917 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2918 }
2919 kfree(vc);
2920 }
2921 }
2922 }
2923
2924 static int
open_card_ubr0(struct idt77252_dev *card)2925 open_card_ubr0(struct idt77252_dev *card)
2926 {
2927 struct vc_map *vc;
2928
2929 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2930 if (!vc) {
2931 printk("%s: can't alloc vc\n", card->name);
2932 return -ENOMEM;
2933 }
2934 card->vcs[0] = vc;
2935 vc->class = SCHED_UBR0;
2936
2937 vc->scq = alloc_scq(card, vc->class);
2938 if (!vc->scq) {
2939 printk("%s: can't get SCQ.\n", card->name);
2940 kfree(card->vcs[0]);
2941 card->vcs[0] = NULL;
2942 return -ENOMEM;
2943 }
2944
2945 card->scd2vc[0] = vc;
2946 vc->scd_index = 0;
2947 vc->scq->scd = card->scd_base;
2948
2949 fill_scd(card, vc->scq, vc->class);
2950
2951 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
2952 write_sram(card, card->tct_base + 1, 0);
2953 write_sram(card, card->tct_base + 2, 0);
2954 write_sram(card, card->tct_base + 3, 0);
2955 write_sram(card, card->tct_base + 4, 0);
2956 write_sram(card, card->tct_base + 5, 0);
2957 write_sram(card, card->tct_base + 6, 0);
2958 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
2959
2960 clear_bit(VCF_IDLE, &vc->flags);
2961 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
2962 return 0;
2963 }
2964
2965 static void
close_card_ubr0(struct idt77252_dev *card)2966 close_card_ubr0(struct idt77252_dev *card)
2967 {
2968 struct vc_map *vc = card->vcs[0];
2969
2970 free_scq(card, vc->scq);
2971 kfree(vc);
2972 }
2973
2974 static int
idt77252_dev_open(struct idt77252_dev *card)2975 idt77252_dev_open(struct idt77252_dev *card)
2976 {
2977 u32 conf;
2978
2979 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
2980 printk("%s: SAR not yet initialized.\n", card->name);
2981 return -1;
2982 }
2983
2984 conf = SAR_CFG_RXPTH| /* enable receive path */
2985 SAR_RX_DELAY | /* interrupt on complete PDU */
2986 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
2987 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
2988 SAR_CFG_TMOIE | /* interrupt on timer overflow */
2989 SAR_CFG_FBIE | /* interrupt on low free buffers */
2990 SAR_CFG_TXEN | /* transmit operation enable */
2991 SAR_CFG_TXINT | /* interrupt on transmit status */
2992 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
2993 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
2994 SAR_CFG_PHYIE /* enable PHY interrupts */
2995 ;
2996
2997 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
2998 /* Test RAW cell receive. */
2999 conf |= SAR_CFG_VPECA;
3000 #endif
3001
3002 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3003
3004 if (open_card_oam(card)) {
3005 printk("%s: Error initializing OAM.\n", card->name);
3006 return -1;
3007 }
3008
3009 if (open_card_ubr0(card)) {
3010 printk("%s: Error initializing UBR0.\n", card->name);
3011 return -1;
3012 }
3013
3014 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3015 return 0;
3016 }
3017
idt77252_dev_close(struct atm_dev *dev)3018 static void idt77252_dev_close(struct atm_dev *dev)
3019 {
3020 struct idt77252_dev *card = dev->dev_data;
3021 u32 conf;
3022
3023 close_card_ubr0(card);
3024 close_card_oam(card);
3025
3026 conf = SAR_CFG_RXPTH | /* enable receive path */
3027 SAR_RX_DELAY | /* interrupt on complete PDU */
3028 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3029 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3030 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3031 SAR_CFG_FBIE | /* interrupt on low free buffers */
3032 SAR_CFG_TXEN | /* transmit operation enable */
3033 SAR_CFG_TXINT | /* interrupt on transmit status */
3034 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3035 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3036 ;
3037
3038 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3039
3040 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3041 }
3042
3043
3044 /*****************************************************************************/
3045 /* */
3046 /* Initialisation and Deinitialization of IDT77252 */
3047 /* */
3048 /*****************************************************************************/
3049
3050
3051 static void
deinit_card(struct idt77252_dev *card)3052 deinit_card(struct idt77252_dev *card)
3053 {
3054 struct sk_buff *skb;
3055 int i, j;
3056
3057 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3058 printk("%s: SAR not yet initialized.\n", card->name);
3059 return;
3060 }
3061 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3062
3063 writel(0, SAR_REG_CFG);
3064
3065 if (card->atmdev)
3066 atm_dev_deregister(card->atmdev);
3067
3068 for (i = 0; i < 4; i++) {
3069 for (j = 0; j < FBQ_SIZE; j++) {
3070 skb = card->sbpool[i].skb[j];
3071 if (skb) {
3072 dma_unmap_single(&card->pcidev->dev,
3073 IDT77252_PRV_PADDR(skb),
3074 (skb_end_pointer(skb) -
3075 skb->data),
3076 DMA_FROM_DEVICE);
3077 card->sbpool[i].skb[j] = NULL;
3078 dev_kfree_skb(skb);
3079 }
3080 }
3081 }
3082
3083 vfree(card->soft_tst);
3084
3085 vfree(card->scd2vc);
3086
3087 vfree(card->vcs);
3088
3089 if (card->raw_cell_hnd) {
3090 dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32),
3091 card->raw_cell_hnd, card->raw_cell_paddr);
3092 }
3093
3094 if (card->rsq.base) {
3095 DIPRINTK("%s: Release RSQ ...\n", card->name);
3096 deinit_rsq(card);
3097 }
3098
3099 if (card->tsq.base) {
3100 DIPRINTK("%s: Release TSQ ...\n", card->name);
3101 deinit_tsq(card);
3102 }
3103
3104 DIPRINTK("idt77252: Release IRQ.\n");
3105 free_irq(card->pcidev->irq, card);
3106
3107 for (i = 0; i < 4; i++) {
3108 if (card->fbq[i])
3109 iounmap(card->fbq[i]);
3110 }
3111
3112 if (card->membase)
3113 iounmap(card->membase);
3114
3115 clear_bit(IDT77252_BIT_INIT, &card->flags);
3116 DIPRINTK("%s: Card deinitialized.\n", card->name);
3117 }
3118
3119
init_sram(struct idt77252_dev *card)3120 static void init_sram(struct idt77252_dev *card)
3121 {
3122 int i;
3123
3124 for (i = 0; i < card->sramsize; i += 4)
3125 write_sram(card, (i >> 2), 0);
3126
3127 /* set SRAM layout for THIS card */
3128 if (card->sramsize == (512 * 1024)) {
3129 card->tct_base = SAR_SRAM_TCT_128_BASE;
3130 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3131 / SAR_SRAM_TCT_SIZE;
3132 card->rct_base = SAR_SRAM_RCT_128_BASE;
3133 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3134 / SAR_SRAM_RCT_SIZE;
3135 card->rt_base = SAR_SRAM_RT_128_BASE;
3136 card->scd_base = SAR_SRAM_SCD_128_BASE;
3137 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3138 / SAR_SRAM_SCD_SIZE;
3139 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3140 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3141 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3142 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3143 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3144 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3145 card->fifo_size = SAR_RXFD_SIZE_32K;
3146 } else {
3147 card->tct_base = SAR_SRAM_TCT_32_BASE;
3148 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3149 / SAR_SRAM_TCT_SIZE;
3150 card->rct_base = SAR_SRAM_RCT_32_BASE;
3151 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3152 / SAR_SRAM_RCT_SIZE;
3153 card->rt_base = SAR_SRAM_RT_32_BASE;
3154 card->scd_base = SAR_SRAM_SCD_32_BASE;
3155 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3156 / SAR_SRAM_SCD_SIZE;
3157 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3158 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3159 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3160 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3161 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3162 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3163 card->fifo_size = SAR_RXFD_SIZE_4K;
3164 }
3165
3166 /* Initialize TCT */
3167 for (i = 0; i < card->tct_size; i++) {
3168 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3169 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3170 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3171 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3172 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3173 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3174 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3175 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3176 }
3177
3178 /* Initialize RCT */
3179 for (i = 0; i < card->rct_size; i++) {
3180 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3181 (u32) SAR_RCTE_RAWCELLINTEN);
3182 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3183 (u32) 0);
3184 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3185 (u32) 0);
3186 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3187 (u32) 0xffffffff);
3188 }
3189
3190 writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3191 writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3192 writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3193 writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3194
3195 /* Initialize rate table */
3196 for (i = 0; i < 256; i++) {
3197 write_sram(card, card->rt_base + i, log_to_rate[i]);
3198 }
3199
3200 for (i = 0; i < 128; i++) {
3201 unsigned int tmp;
3202
3203 tmp = rate_to_log[(i << 2) + 0] << 0;
3204 tmp |= rate_to_log[(i << 2) + 1] << 8;
3205 tmp |= rate_to_log[(i << 2) + 2] << 16;
3206 tmp |= rate_to_log[(i << 2) + 3] << 24;
3207 write_sram(card, card->rt_base + 256 + i, tmp);
3208 }
3209
3210 #if 0 /* Fill RDF and AIR tables. */
3211 for (i = 0; i < 128; i++) {
3212 unsigned int tmp;
3213
3214 tmp = RDF[0][(i << 1) + 0] << 16;
3215 tmp |= RDF[0][(i << 1) + 1] << 0;
3216 write_sram(card, card->rt_base + 512 + i, tmp);
3217 }
3218
3219 for (i = 0; i < 128; i++) {
3220 unsigned int tmp;
3221
3222 tmp = AIR[0][(i << 1) + 0] << 16;
3223 tmp |= AIR[0][(i << 1) + 1] << 0;
3224 write_sram(card, card->rt_base + 640 + i, tmp);
3225 }
3226 #endif
3227
3228 IPRINTK("%s: initialize rate table ...\n", card->name);
3229 writel(card->rt_base << 2, SAR_REG_RTBL);
3230
3231 /* Initialize TSTs */
3232 IPRINTK("%s: initialize TST ...\n", card->name);
3233 card->tst_free = card->tst_size - 2; /* last two are jumps */
3234
3235 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3236 write_sram(card, i, TSTE_OPC_VAR);
3237 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3238 idt77252_sram_write_errors = 1;
3239 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3240 idt77252_sram_write_errors = 0;
3241 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3242 write_sram(card, i, TSTE_OPC_VAR);
3243 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3244 idt77252_sram_write_errors = 1;
3245 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3246 idt77252_sram_write_errors = 0;
3247
3248 card->tst_index = 0;
3249 writel(card->tst[0] << 2, SAR_REG_TSTB);
3250
3251 /* Initialize ABRSTD and Receive FIFO */
3252 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3253 writel(card->abrst_size | (card->abrst_base << 2),
3254 SAR_REG_ABRSTD);
3255
3256 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3257 writel(card->fifo_size | (card->fifo_base << 2),
3258 SAR_REG_RXFD);
3259
3260 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3261 }
3262
init_card(struct atm_dev *dev)3263 static int init_card(struct atm_dev *dev)
3264 {
3265 struct idt77252_dev *card = dev->dev_data;
3266 struct pci_dev *pcidev = card->pcidev;
3267 unsigned long tmpl, modl;
3268 unsigned int linkrate, rsvdcr;
3269 unsigned int tst_entries;
3270 struct net_device *tmp;
3271 char tname[10];
3272
3273 u32 size;
3274 u_char pci_byte;
3275 u32 conf;
3276 int i, k;
3277
3278 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3279 printk("Error: SAR already initialized.\n");
3280 return -1;
3281 }
3282
3283 /*****************************************************************/
3284 /* P C I C O N F I G U R A T I O N */
3285 /*****************************************************************/
3286
3287 /* Set PCI Retry-Timeout and TRDY timeout */
3288 IPRINTK("%s: Checking PCI retries.\n", card->name);
3289 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3290 printk("%s: can't read PCI retry timeout.\n", card->name);
3291 deinit_card(card);
3292 return -1;
3293 }
3294 if (pci_byte != 0) {
3295 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3296 card->name, pci_byte);
3297 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3298 printk("%s: can't set PCI retry timeout.\n",
3299 card->name);
3300 deinit_card(card);
3301 return -1;
3302 }
3303 }
3304 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3305 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3306 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3307 deinit_card(card);
3308 return -1;
3309 }
3310 if (pci_byte != 0) {
3311 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3312 card->name, pci_byte);
3313 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3314 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3315 deinit_card(card);
3316 return -1;
3317 }
3318 }
3319 /* Reset Timer register */
3320 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3321 printk("%s: resetting timer overflow.\n", card->name);
3322 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3323 }
3324 IPRINTK("%s: Request IRQ ... ", card->name);
3325 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,
3326 card->name, card) != 0) {
3327 printk("%s: can't allocate IRQ.\n", card->name);
3328 deinit_card(card);
3329 return -1;
3330 }
3331 IPRINTK("got %d.\n", pcidev->irq);
3332
3333 /*****************************************************************/
3334 /* C H E C K A N D I N I T S R A M */
3335 /*****************************************************************/
3336
3337 IPRINTK("%s: Initializing SRAM\n", card->name);
3338
3339 /* preset size of connecton table, so that init_sram() knows about it */
3340 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3341 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3342 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3343 #ifndef ATM_IDT77252_SEND_IDLE
3344 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3345 #endif
3346 0;
3347
3348 if (card->sramsize == (512 * 1024))
3349 conf |= SAR_CFG_CNTBL_1k;
3350 else
3351 conf |= SAR_CFG_CNTBL_512;
3352
3353 switch (vpibits) {
3354 case 0:
3355 conf |= SAR_CFG_VPVCS_0;
3356 break;
3357 default:
3358 case 1:
3359 conf |= SAR_CFG_VPVCS_1;
3360 break;
3361 case 2:
3362 conf |= SAR_CFG_VPVCS_2;
3363 break;
3364 case 8:
3365 conf |= SAR_CFG_VPVCS_8;
3366 break;
3367 }
3368
3369 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3370
3371 init_sram(card);
3372
3373 /********************************************************************/
3374 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3375 /********************************************************************/
3376 /* Initialize TSQ */
3377 if (0 != init_tsq(card)) {
3378 deinit_card(card);
3379 return -1;
3380 }
3381 /* Initialize RSQ */
3382 if (0 != init_rsq(card)) {
3383 deinit_card(card);
3384 return -1;
3385 }
3386
3387 card->vpibits = vpibits;
3388 if (card->sramsize == (512 * 1024)) {
3389 card->vcibits = 10 - card->vpibits;
3390 } else {
3391 card->vcibits = 9 - card->vpibits;
3392 }
3393
3394 card->vcimask = 0;
3395 for (k = 0, i = 1; k < card->vcibits; k++) {
3396 card->vcimask |= i;
3397 i <<= 1;
3398 }
3399
3400 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3401 writel(0, SAR_REG_VPM);
3402
3403 /* Little Endian Order */
3404 writel(0, SAR_REG_GP);
3405
3406 /* Initialize RAW Cell Handle Register */
3407 card->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev,
3408 2 * sizeof(u32),
3409 &card->raw_cell_paddr,
3410 GFP_KERNEL);
3411 if (!card->raw_cell_hnd) {
3412 printk("%s: memory allocation failure.\n", card->name);
3413 deinit_card(card);
3414 return -1;
3415 }
3416 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3417 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3418 card->raw_cell_hnd);
3419
3420 size = sizeof(struct vc_map *) * card->tct_size;
3421 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3422 card->vcs = vzalloc(size);
3423 if (!card->vcs) {
3424 printk("%s: memory allocation failure.\n", card->name);
3425 deinit_card(card);
3426 return -1;
3427 }
3428
3429 size = sizeof(struct vc_map *) * card->scd_size;
3430 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3431 card->name, size);
3432 card->scd2vc = vzalloc(size);
3433 if (!card->scd2vc) {
3434 printk("%s: memory allocation failure.\n", card->name);
3435 deinit_card(card);
3436 return -1;
3437 }
3438
3439 size = sizeof(struct tst_info) * (card->tst_size - 2);
3440 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3441 card->name, size);
3442 card->soft_tst = vmalloc(size);
3443 if (!card->soft_tst) {
3444 printk("%s: memory allocation failure.\n", card->name);
3445 deinit_card(card);
3446 return -1;
3447 }
3448 for (i = 0; i < card->tst_size - 2; i++) {
3449 card->soft_tst[i].tste = TSTE_OPC_VAR;
3450 card->soft_tst[i].vc = NULL;
3451 }
3452
3453 if (dev->phy == NULL) {
3454 printk("%s: No LT device defined.\n", card->name);
3455 deinit_card(card);
3456 return -1;
3457 }
3458 if (dev->phy->ioctl == NULL) {
3459 printk("%s: LT had no IOCTL function defined.\n", card->name);
3460 deinit_card(card);
3461 return -1;
3462 }
3463
3464 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3465 /*
3466 * this is a jhs hack to get around special functionality in the
3467 * phy driver for the atecom hardware; the functionality doesn't
3468 * exist in the linux atm suni driver
3469 *
3470 * it isn't the right way to do things, but as the guy from NIST
3471 * said, talking about their measurement of the fine structure
3472 * constant, "it's good enough for government work."
3473 */
3474 linkrate = 149760000;
3475 #endif
3476
3477 card->link_pcr = (linkrate / 8 / 53);
3478 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3479 card->name, linkrate, card->link_pcr);
3480
3481 #ifdef ATM_IDT77252_SEND_IDLE
3482 card->utopia_pcr = card->link_pcr;
3483 #else
3484 card->utopia_pcr = (160000000 / 8 / 54);
3485 #endif
3486
3487 rsvdcr = 0;
3488 if (card->utopia_pcr > card->link_pcr)
3489 rsvdcr = card->utopia_pcr - card->link_pcr;
3490
3491 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3492 modl = tmpl % (unsigned long)card->utopia_pcr;
3493 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3494 if (modl)
3495 tst_entries++;
3496 card->tst_free -= tst_entries;
3497 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3498
3499 #ifdef HAVE_EEPROM
3500 idt77252_eeprom_init(card);
3501 printk("%s: EEPROM: %02x:", card->name,
3502 idt77252_eeprom_read_status(card));
3503
3504 for (i = 0; i < 0x80; i++) {
3505 printk(" %02x",
3506 idt77252_eeprom_read_byte(card, i)
3507 );
3508 }
3509 printk("\n");
3510 #endif /* HAVE_EEPROM */
3511
3512 /*
3513 * XXX: <hack>
3514 */
3515 sprintf(tname, "eth%d", card->index);
3516 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */
3517 if (tmp) {
3518 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3519 dev_put(tmp);
3520 printk("%s: ESI %pM\n", card->name, card->atmdev->esi);
3521 }
3522 /*
3523 * XXX: </hack>
3524 */
3525
3526 /* Set Maximum Deficit Count for now. */
3527 writel(0xffff, SAR_REG_MDFCT);
3528
3529 set_bit(IDT77252_BIT_INIT, &card->flags);
3530
3531 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3532 return 0;
3533 }
3534
3535
3536 /*****************************************************************************/
3537 /* */
3538 /* Probing of IDT77252 ABR SAR */
3539 /* */
3540 /*****************************************************************************/
3541
3542
idt77252_preset(struct idt77252_dev *card)3543 static int idt77252_preset(struct idt77252_dev *card)
3544 {
3545 u16 pci_command;
3546
3547 /*****************************************************************/
3548 /* P C I C O N F I G U R A T I O N */
3549 /*****************************************************************/
3550
3551 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3552 card->name);
3553 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3554 printk("%s: can't read PCI_COMMAND.\n", card->name);
3555 deinit_card(card);
3556 return -1;
3557 }
3558 if (!(pci_command & PCI_COMMAND_IO)) {
3559 printk("%s: PCI_COMMAND: %04x (???)\n",
3560 card->name, pci_command);
3561 deinit_card(card);
3562 return (-1);
3563 }
3564 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3565 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3566 printk("%s: can't write PCI_COMMAND.\n", card->name);
3567 deinit_card(card);
3568 return -1;
3569 }
3570 /*****************************************************************/
3571 /* G E N E R I C R E S E T */
3572 /*****************************************************************/
3573
3574 /* Software reset */
3575 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3576 mdelay(1);
3577 writel(0, SAR_REG_CFG);
3578
3579 IPRINTK("%s: Software resetted.\n", card->name);
3580 return 0;
3581 }
3582
3583
probe_sram(struct idt77252_dev *card)3584 static unsigned long probe_sram(struct idt77252_dev *card)
3585 {
3586 u32 data, addr;
3587
3588 writel(0, SAR_REG_DR0);
3589 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3590
3591 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3592 writel(ATM_POISON, SAR_REG_DR0);
3593 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3594
3595 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3596 data = readl(SAR_REG_DR0);
3597
3598 if (data != 0)
3599 break;
3600 }
3601
3602 return addr * sizeof(u32);
3603 }
3604
idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)3605 static int idt77252_init_one(struct pci_dev *pcidev,
3606 const struct pci_device_id *id)
3607 {
3608 static struct idt77252_dev **last = &idt77252_chain;
3609 static int index = 0;
3610
3611 unsigned long membase, srambase;
3612 struct idt77252_dev *card;
3613 struct atm_dev *dev;
3614 int i, err;
3615
3616
3617 if ((err = pci_enable_device(pcidev))) {
3618 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3619 return err;
3620 }
3621
3622 if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
3623 printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
3624 goto err_out_disable_pdev;
3625 }
3626
3627 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3628 if (!card) {
3629 printk("idt77252-%d: can't allocate private data\n", index);
3630 err = -ENOMEM;
3631 goto err_out_disable_pdev;
3632 }
3633 card->revision = pcidev->revision;
3634 card->index = index;
3635 card->pcidev = pcidev;
3636 sprintf(card->name, "idt77252-%d", card->index);
3637
3638 INIT_WORK(&card->tqueue, idt77252_softint);
3639
3640 membase = pci_resource_start(pcidev, 1);
3641 srambase = pci_resource_start(pcidev, 2);
3642
3643 mutex_init(&card->mutex);
3644 spin_lock_init(&card->cmd_lock);
3645 spin_lock_init(&card->tst_lock);
3646
3647 timer_setup(&card->tst_timer, tst_timer, 0);
3648
3649 /* Do the I/O remapping... */
3650 card->membase = ioremap(membase, 1024);
3651 if (!card->membase) {
3652 printk("%s: can't ioremap() membase\n", card->name);
3653 err = -EIO;
3654 goto err_out_free_card;
3655 }
3656
3657 if (idt77252_preset(card)) {
3658 printk("%s: preset failed\n", card->name);
3659 err = -EIO;
3660 goto err_out_iounmap;
3661 }
3662
3663 dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1,
3664 NULL);
3665 if (!dev) {
3666 printk("%s: can't register atm device\n", card->name);
3667 err = -EIO;
3668 goto err_out_iounmap;
3669 }
3670 dev->dev_data = card;
3671 card->atmdev = dev;
3672
3673 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3674 suni_init(dev);
3675 if (!dev->phy) {
3676 printk("%s: can't init SUNI\n", card->name);
3677 err = -EIO;
3678 goto err_out_deinit_card;
3679 }
3680 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3681
3682 card->sramsize = probe_sram(card);
3683
3684 for (i = 0; i < 4; i++) {
3685 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3686 if (!card->fbq[i]) {
3687 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3688 err = -EIO;
3689 goto err_out_deinit_card;
3690 }
3691 }
3692
3693 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3694 card->name, ((card->revision > 1) && (card->revision < 25)) ?
3695 'A' + card->revision - 1 : '?', membase, srambase,
3696 card->sramsize / 1024);
3697
3698 if (init_card(dev)) {
3699 printk("%s: init_card failed\n", card->name);
3700 err = -EIO;
3701 goto err_out_deinit_card;
3702 }
3703
3704 dev->ci_range.vpi_bits = card->vpibits;
3705 dev->ci_range.vci_bits = card->vcibits;
3706 dev->link_rate = card->link_pcr;
3707
3708 if (dev->phy->start)
3709 dev->phy->start(dev);
3710
3711 if (idt77252_dev_open(card)) {
3712 printk("%s: dev_open failed\n", card->name);
3713 err = -EIO;
3714 goto err_out_stop;
3715 }
3716
3717 *last = card;
3718 last = &card->next;
3719 index++;
3720
3721 return 0;
3722
3723 err_out_stop:
3724 if (dev->phy->stop)
3725 dev->phy->stop(dev);
3726
3727 err_out_deinit_card:
3728 deinit_card(card);
3729
3730 err_out_iounmap:
3731 iounmap(card->membase);
3732
3733 err_out_free_card:
3734 kfree(card);
3735
3736 err_out_disable_pdev:
3737 pci_disable_device(pcidev);
3738 return err;
3739 }
3740
3741 static const struct pci_device_id idt77252_pci_tbl[] =
3742 {
3743 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },
3744 { 0, }
3745 };
3746
3747 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3748
3749 static struct pci_driver idt77252_driver = {
3750 .name = "idt77252",
3751 .id_table = idt77252_pci_tbl,
3752 .probe = idt77252_init_one,
3753 };
3754
idt77252_init(void)3755 static int __init idt77252_init(void)
3756 {
3757 struct sk_buff *skb;
3758
3759 printk("%s: at %p\n", __func__, idt77252_init);
3760
3761 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3762 sizeof(struct idt77252_skb_prv)) {
3763 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3764 __func__, (unsigned long) sizeof(skb->cb),
3765 (unsigned long) sizeof(struct atm_skb_data) +
3766 sizeof(struct idt77252_skb_prv));
3767 return -EIO;
3768 }
3769
3770 return pci_register_driver(&idt77252_driver);
3771 }
3772
idt77252_exit(void)3773 static void __exit idt77252_exit(void)
3774 {
3775 struct idt77252_dev *card;
3776 struct atm_dev *dev;
3777
3778 pci_unregister_driver(&idt77252_driver);
3779
3780 while (idt77252_chain) {
3781 card = idt77252_chain;
3782 dev = card->atmdev;
3783 idt77252_chain = card->next;
3784 del_timer_sync(&card->tst_timer);
3785
3786 if (dev->phy->stop)
3787 dev->phy->stop(dev);
3788 deinit_card(card);
3789 pci_disable_device(card->pcidev);
3790 kfree(card);
3791 }
3792
3793 DIPRINTK("idt77252: finished cleanup-module().\n");
3794 }
3795
3796 module_init(idt77252_init);
3797 module_exit(idt77252_exit);
3798
3799 MODULE_LICENSE("GPL");
3800
3801 module_param(vpibits, uint, 0);
3802 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3803 #ifdef CONFIG_ATM_IDT77252_DEBUG
3804 module_param(debug, ulong, 0644);
3805 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3806 #endif
3807
3808 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3809 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
3810