1 ######################################################################## 2 # Implement fast SHA-512 with AVX instructions. (x86_64) 3 # 4 # Copyright (C) 2013 Intel Corporation. 5 # 6 # Authors: 7 # James Guilford <james.guilford@intel.com> 8 # Kirk Yap <kirk.s.yap@intel.com> 9 # David Cote <david.m.cote@intel.com> 10 # Tim Chen <tim.c.chen@linux.intel.com> 11 # 12 # This software is available to you under a choice of one of two 13 # licenses. You may choose to be licensed under the terms of the GNU 14 # General Public License (GPL) Version 2, available from the file 15 # COPYING in the main directory of this source tree, or the 16 # OpenIB.org BSD license below: 17 # 18 # Redistribution and use in source and binary forms, with or 19 # without modification, are permitted provided that the following 20 # conditions are met: 21 # 22 # - Redistributions of source code must retain the above 23 # copyright notice, this list of conditions and the following 24 # disclaimer. 25 # 26 # - Redistributions in binary form must reproduce the above 27 # copyright notice, this list of conditions and the following 28 # disclaimer in the documentation and/or other materials 29 # provided with the distribution. 30 # 31 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 32 # EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 34 # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 35 # BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 36 # ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 37 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 38 # SOFTWARE. 39 # 40 ######################################################################## 41 # 42 # This code is described in an Intel White-Paper: 43 # "Fast SHA-512 Implementations on Intel Architecture Processors" 44 # 45 # To find it, surf to http://www.intel.com/p/en_US/embedded 46 # and search for that title. 47 # 48 ######################################################################## 49 50 #include <linux/linkage.h> 51 52 .text 53 54 # Virtual Registers 55 # ARG1 56 digest = %rdi 57 # ARG2 58 msg = %rsi 59 # ARG3 60 msglen = %rdx 61 T1 = %rcx 62 T2 = %r8 63 a_64 = %r9 64 b_64 = %r10 65 c_64 = %r11 66 d_64 = %r12 67 e_64 = %r13 68 f_64 = %r14 69 g_64 = %r15 70 h_64 = %rbx 71 tmp0 = %rax 72 73 # Local variables (stack frame) 74 75 # Message Schedule 76 W_SIZE = 80*8 77 # W[t] + K[t] | W[t+1] + K[t+1] 78 WK_SIZE = 2*8 79 RSPSAVE_SIZE = 1*8 80 GPRSAVE_SIZE = 5*8 81 82 frame_W = 0 83 frame_WK = frame_W + W_SIZE 84 frame_RSPSAVE = frame_WK + WK_SIZE 85 frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE 86 frame_size = frame_GPRSAVE + GPRSAVE_SIZE 87 88 # Useful QWORD "arrays" for simpler memory references 89 # MSG, DIGEST, K_t, W_t are arrays 90 # WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even 91 92 # Input message (arg1) 93 #define MSG(i) 8*i(msg) 94 95 # Output Digest (arg2) 96 #define DIGEST(i) 8*i(digest) 97 98 # SHA Constants (static mem) 99 #define K_t(i) 8*i+K512(%rip) 100 101 # Message Schedule (stack frame) 102 #define W_t(i) 8*i+frame_W(%rsp) 103 104 # W[t]+K[t] (stack frame) 105 #define WK_2(i) 8*((i%2))+frame_WK(%rsp) 106 107 .macro RotateState 108 # Rotate symbols a..h right 109 TMP = h_64 110 h_64 = g_64 111 g_64 = f_64 112 f_64 = e_64 113 e_64 = d_64 114 d_64 = c_64 115 c_64 = b_64 116 b_64 = a_64 117 a_64 = TMP 118 .endm 119 120 .macro RORQ p1 p2 121 # shld is faster than ror on Sandybridge 122 shld $(64-\p2), \p1, \p1 123 .endm 124 125 .macro SHA512_Round rnd 126 # Compute Round %%t 127 mov f_64, T1 # T1 = f 128 mov e_64, tmp0 # tmp = e 129 xor g_64, T1 # T1 = f ^ g 130 RORQ tmp0, 23 # 41 # tmp = e ror 23 131 and e_64, T1 # T1 = (f ^ g) & e 132 xor e_64, tmp0 # tmp = (e ror 23) ^ e 133 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g) 134 idx = \rnd 135 add WK_2(idx), T1 # W[t] + K[t] from message scheduler 136 RORQ tmp0, 4 # 18 # tmp = ((e ror 23) ^ e) ror 4 137 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e 138 mov a_64, T2 # T2 = a 139 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h 140 RORQ tmp0, 14 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e) 141 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e) 142 mov a_64, tmp0 # tmp = a 143 xor c_64, T2 # T2 = a ^ c 144 and c_64, tmp0 # tmp = a & c 145 and b_64, T2 # T2 = (a ^ c) & b 146 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c) 147 mov a_64, tmp0 # tmp = a 148 RORQ tmp0, 5 # 39 # tmp = a ror 5 149 xor a_64, tmp0 # tmp = (a ror 5) ^ a 150 add T1, d_64 # e(next_state) = d + T1 151 RORQ tmp0, 6 # 34 # tmp = ((a ror 5) ^ a) ror 6 152 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a 153 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c) 154 RORQ tmp0, 28 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a) 155 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a) 156 RotateState 157 .endm 158 159 .macro SHA512_2Sched_2Round_avx rnd 160 # Compute rounds t-2 and t-1 161 # Compute message schedule QWORDS t and t+1 162 163 # Two rounds are computed based on the values for K[t-2]+W[t-2] and 164 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message 165 # scheduler. 166 # The two new schedule QWORDS are stored at [W_t(t)] and [W_t(t+1)]. 167 # They are then added to their respective SHA512 constants at 168 # [K_t(t)] and [K_t(t+1)] and stored at dqword [WK_2(t)] 169 # For brievity, the comments following vectored instructions only refer to 170 # the first of a pair of QWORDS. 171 # Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]} 172 # The computation of the message schedule and the rounds are tightly 173 # stitched to take advantage of instruction-level parallelism. 174 175 idx = \rnd - 2 176 vmovdqa W_t(idx), %xmm4 # XMM4 = W[t-2] 177 idx = \rnd - 15 178 vmovdqu W_t(idx), %xmm5 # XMM5 = W[t-15] 179 mov f_64, T1 180 vpsrlq $61, %xmm4, %xmm0 # XMM0 = W[t-2]>>61 181 mov e_64, tmp0 182 vpsrlq $1, %xmm5, %xmm6 # XMM6 = W[t-15]>>1 183 xor g_64, T1 184 RORQ tmp0, 23 # 41 185 vpsrlq $19, %xmm4, %xmm1 # XMM1 = W[t-2]>>19 186 and e_64, T1 187 xor e_64, tmp0 188 vpxor %xmm1, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 189 xor g_64, T1 190 idx = \rnd 191 add WK_2(idx), T1# 192 vpsrlq $8, %xmm5, %xmm7 # XMM7 = W[t-15]>>8 193 RORQ tmp0, 4 # 18 194 vpsrlq $6, %xmm4, %xmm2 # XMM2 = W[t-2]>>6 195 xor e_64, tmp0 196 mov a_64, T2 197 add h_64, T1 198 vpxor %xmm7, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 199 RORQ tmp0, 14 # 14 200 add tmp0, T1 201 vpsrlq $7, %xmm5, %xmm8 # XMM8 = W[t-15]>>7 202 mov a_64, tmp0 203 xor c_64, T2 204 vpsllq $(64-61), %xmm4, %xmm3 # XMM3 = W[t-2]<<3 205 and c_64, tmp0 206 and b_64, T2 207 vpxor %xmm3, %xmm2, %xmm2 # XMM2 = W[t-2]>>6 ^ W[t-2]<<3 208 xor tmp0, T2 209 mov a_64, tmp0 210 vpsllq $(64-1), %xmm5, %xmm9 # XMM9 = W[t-15]<<63 211 RORQ tmp0, 5 # 39 212 vpxor %xmm9, %xmm8, %xmm8 # XMM8 = W[t-15]>>7 ^ W[t-15]<<63 213 xor a_64, tmp0 214 add T1, d_64 215 RORQ tmp0, 6 # 34 216 xor a_64, tmp0 217 vpxor %xmm8, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^ 218 # W[t-15]>>7 ^ W[t-15]<<63 219 lea (T1, T2), h_64 220 RORQ tmp0, 28 # 28 221 vpsllq $(64-19), %xmm4, %xmm4 # XMM4 = W[t-2]<<25 222 add tmp0, h_64 223 RotateState 224 vpxor %xmm4, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^ 225 # W[t-2]<<25 226 mov f_64, T1 227 vpxor %xmm2, %xmm0, %xmm0 # XMM0 = s1(W[t-2]) 228 mov e_64, tmp0 229 xor g_64, T1 230 idx = \rnd - 16 231 vpaddq W_t(idx), %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16] 232 idx = \rnd - 7 233 vmovdqu W_t(idx), %xmm1 # XMM1 = W[t-7] 234 RORQ tmp0, 23 # 41 235 and e_64, T1 236 xor e_64, tmp0 237 xor g_64, T1 238 vpsllq $(64-8), %xmm5, %xmm5 # XMM5 = W[t-15]<<56 239 idx = \rnd + 1 240 add WK_2(idx), T1 241 vpxor %xmm5, %xmm6, %xmm6 # XMM6 = s0(W[t-15]) 242 RORQ tmp0, 4 # 18 243 vpaddq %xmm6, %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15]) 244 xor e_64, tmp0 245 vpaddq %xmm1, %xmm0, %xmm0 # XMM0 = W[t] = s1(W[t-2]) + W[t-7] + 246 # s0(W[t-15]) + W[t-16] 247 mov a_64, T2 248 add h_64, T1 249 RORQ tmp0, 14 # 14 250 add tmp0, T1 251 idx = \rnd 252 vmovdqa %xmm0, W_t(idx) # Store W[t] 253 vpaddq K_t(idx), %xmm0, %xmm0 # Compute W[t]+K[t] 254 vmovdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds 255 mov a_64, tmp0 256 xor c_64, T2 257 and c_64, tmp0 258 and b_64, T2 259 xor tmp0, T2 260 mov a_64, tmp0 261 RORQ tmp0, 5 # 39 262 xor a_64, tmp0 263 add T1, d_64 264 RORQ tmp0, 6 # 34 265 xor a_64, tmp0 266 lea (T1, T2), h_64 267 RORQ tmp0, 28 # 28 268 add tmp0, h_64 269 RotateState 270 .endm 271 272 ######################################################################## 273 # void sha512_transform_avx(sha512_state *state, const u8 *data, int blocks) 274 # Purpose: Updates the SHA512 digest stored at "state" with the message 275 # stored in "data". 276 # The size of the message pointed to by "data" must be an integer multiple 277 # of SHA512 message blocks. 278 # "blocks" is the message length in SHA512 blocks 279 ######################################################################## 280 SYM_FUNC_START(sha512_transform_avx) 281 cmp $0, msglen 282 je nowork 283 284 # Allocate Stack Space 285 mov %rsp, %rax 286 sub $frame_size, %rsp 287 and $~(0x20 - 1), %rsp 288 mov %rax, frame_RSPSAVE(%rsp) 289 290 # Save GPRs 291 mov %rbx, frame_GPRSAVE(%rsp) 292 mov %r12, frame_GPRSAVE +8*1(%rsp) 293 mov %r13, frame_GPRSAVE +8*2(%rsp) 294 mov %r14, frame_GPRSAVE +8*3(%rsp) 295 mov %r15, frame_GPRSAVE +8*4(%rsp) 296 297 updateblock: 298 299 # Load state variables 300 mov DIGEST(0), a_64 301 mov DIGEST(1), b_64 302 mov DIGEST(2), c_64 303 mov DIGEST(3), d_64 304 mov DIGEST(4), e_64 305 mov DIGEST(5), f_64 306 mov DIGEST(6), g_64 307 mov DIGEST(7), h_64 308 309 t = 0 310 .rept 80/2 + 1 311 # (80 rounds) / (2 rounds/iteration) + (1 iteration) 312 # +1 iteration because the scheduler leads hashing by 1 iteration 313 .if t < 2 314 # BSWAP 2 QWORDS 315 vmovdqa XMM_QWORD_BSWAP(%rip), %xmm1 316 vmovdqu MSG(t), %xmm0 317 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP 318 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair 319 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t] 320 vmovdqa %xmm0, WK_2(t) # Store into WK for rounds 321 .elseif t < 16 322 # BSWAP 2 QWORDS# Compute 2 Rounds 323 vmovdqu MSG(t), %xmm0 324 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP 325 SHA512_Round t-2 # Round t-2 326 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair 327 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t] 328 SHA512_Round t-1 # Round t-1 329 vmovdqa %xmm0, WK_2(t)# Store W[t]+K[t] into WK 330 .elseif t < 79 331 # Schedule 2 QWORDS# Compute 2 Rounds 332 SHA512_2Sched_2Round_avx t 333 .else 334 # Compute 2 Rounds 335 SHA512_Round t-2 336 SHA512_Round t-1 337 .endif 338 t = t+2 339 .endr 340 341 # Update digest 342 add a_64, DIGEST(0) 343 add b_64, DIGEST(1) 344 add c_64, DIGEST(2) 345 add d_64, DIGEST(3) 346 add e_64, DIGEST(4) 347 add f_64, DIGEST(5) 348 add g_64, DIGEST(6) 349 add h_64, DIGEST(7) 350 351 # Advance to next message block 352 add $16*8, msg 353 dec msglen 354 jnz updateblock 355 356 # Restore GPRs 357 mov frame_GPRSAVE(%rsp), %rbx 358 mov frame_GPRSAVE +8*1(%rsp), %r12 359 mov frame_GPRSAVE +8*2(%rsp), %r13 360 mov frame_GPRSAVE +8*3(%rsp), %r14 361 mov frame_GPRSAVE +8*4(%rsp), %r15 362 363 # Restore Stack Pointer 364 mov frame_RSPSAVE(%rsp), %rsp 365 366 nowork: 367 RET 368 SYM_FUNC_END(sha512_transform_avx) 369 370 ######################################################################## 371 ### Binary Data 372 373 .section .rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16 374 .align 16 375 # Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb. 376 XMM_QWORD_BSWAP: 377 .octa 0x08090a0b0c0d0e0f0001020304050607 378 379 # Mergeable 640-byte rodata section. This allows linker to merge the table 380 # with other, exactly the same 640-byte fragment of another rodata section 381 # (if such section exists). 382 .section .rodata.cst640.K512, "aM", @progbits, 640 383 .align 64 384 # K[t] used in SHA512 hashing 385 K512: 386 .quad 0x428a2f98d728ae22,0x7137449123ef65cd 387 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc 388 .quad 0x3956c25bf348b538,0x59f111f1b605d019 389 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118 390 .quad 0xd807aa98a3030242,0x12835b0145706fbe 391 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2 392 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1 393 .quad 0x9bdc06a725c71235,0xc19bf174cf692694 394 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3 395 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65 396 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483 397 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5 398 .quad 0x983e5152ee66dfab,0xa831c66d2db43210 399 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4 400 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725 401 .quad 0x06ca6351e003826f,0x142929670a0e6e70 402 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926 403 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df 404 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8 405 .quad 0x81c2c92e47edaee6,0x92722c851482353b 406 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001 407 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30 408 .quad 0xd192e819d6ef5218,0xd69906245565a910 409 .quad 0xf40e35855771202a,0x106aa07032bbd1b8 410 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53 411 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8 412 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb 413 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3 414 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60 415 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec 416 .quad 0x90befffa23631e28,0xa4506cebde82bde9 417 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b 418 .quad 0xca273eceea26619c,0xd186b8c721c0c207 419 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178 420 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6 421 .quad 0x113f9804bef90dae,0x1b710b35131c471b 422 .quad 0x28db77f523047d84,0x32caab7b40c72493 423 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c 424 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a 425 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817 426