1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Format of an instruction in memory.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 2020 Loongson Technology Co., Ltd.
10 */
11 #ifndef _ASM_INST_H
12 #define _ASM_INST_H
13 #include <linux/types.h>
14
15 #include <asm/asm.h>
16 #include <asm/errno.h>
17 #include <asm/ptrace.h>
18
19 #include <uapi/asm/inst.h>
20
21 /* HACHACHAHCAHC ... */
22
23 /* In case some other massaging is needed, keep LOONGARCHInst as wrapper */
24
25 #define LOONGARCHInst(x) x
26
27 #define I_OPCODE_SFT 26
28 #define LOONGARCHInst_OPCODE(x) (LOONGARCHInst(x) >> I_OPCODE_SFT)
29
30 #define I_JTARGET_SFT 0
31 #define LOONGARCHInst_JTARGET(x) (LOONGARCHInst(x) & 0x03ffffff)
32
33 #define I_RS_SFT 21
34 #define LOONGARCHInst_RS(x) ((LOONGARCHInst(x) & 0x03e00000) >> I_RS_SFT)
35
36 #define I_RT_SFT 16
37 #define LOONGARCHInst_RT(x) ((LOONGARCHInst(x) & 0x001f0000) >> I_RT_SFT)
38
39 #define I_IMM_SFT 0
40 #define LOONGARCHInst_SIMM(x) ((int)((short)(LOONGARCHInst(x) & 0xffff)))
41 #define LOONGARCHInst_UIMM(x) (LOONGARCHInst(x) & 0xffff)
42
43 #define I_CACHEOP_SFT 18
44 #define LOONGARCHInst_CACHEOP(x) ((LOONGARCHInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
45
46 #define I_CACHESEL_SFT 16
47 #define LOONGARCHInst_CACHESEL(x) ((LOONGARCHInst(x) & 0x00030000) >> I_CACHESEL_SFT)
48
49 #define I_RD_SFT 11
50 #define LOONGARCHInst_RD(x) ((LOONGARCHInst(x) & 0x0000f800) >> I_RD_SFT)
51
52 #define I_RE_SFT 6
53 #define LOONGARCHInst_RE(x) ((LOONGARCHInst(x) & 0x000007c0) >> I_RE_SFT)
54
55 #define I_FUNC_SFT 0
56 #define LOONGARCHInst_FUNC(x) (LOONGARCHInst(x) & 0x0000003f)
57
58 #define I_FFMT_SFT 21
59 #define LOONGARCHInst_FFMT(x) ((LOONGARCHInst(x) & 0x01e00000) >> I_FFMT_SFT)
60
61 #define I_FT_SFT 16
62 #define LOONGARCHInst_FT(x) ((LOONGARCHInst(x) & 0x001f0000) >> I_FT_SFT)
63
64 #define I_FS_SFT 11
65 #define LOONGARCHInst_FS(x) ((LOONGARCHInst(x) & 0x0000f800) >> I_FS_SFT)
66
67 #define I_FD_SFT 6
68 #define LOONGARCHInst_FD(x) ((LOONGARCHInst(x) & 0x000007c0) >> I_FD_SFT)
69
70 #define I_FR_SFT 21
71 #define LOONGARCHInst_FR(x) ((LOONGARCHInst(x) & 0x03e00000) >> I_FR_SFT)
72
73 #define I_FMA_FUNC_SFT 2
74 #define LOONGARCHInst_FMA_FUNC(x) ((LOONGARCHInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
75
76 #define I_FMA_FFMT_SFT 0
77 #define LOONGARCHInst_FMA_FFMT(x) (LOONGARCHInst(x) & 0x00000003)
78
79 struct pt_regs;
80 typedef unsigned int loongarch_instruction;
81
82 /* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */
83 extern const int reg16to32[];
84
85 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
86
87 enum loongarch_gpr {
88 LOONGARCH_GPR_ZERO = 0,
89 LOONGARCH_GPR_RA = 1,
90 LOONGARCH_GPR_TP = 2,
91 LOONGARCH_GPR_SP = 3,
92 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
93 LOONGARCH_GPR_A1, /* Reused as V1 for return value */
94 LOONGARCH_GPR_A2,
95 LOONGARCH_GPR_A3,
96 LOONGARCH_GPR_A4,
97 LOONGARCH_GPR_A5,
98 LOONGARCH_GPR_A6,
99 LOONGARCH_GPR_A7,
100 LOONGARCH_GPR_T0 = 12,
101 LOONGARCH_GPR_T1,
102 LOONGARCH_GPR_T2,
103 LOONGARCH_GPR_T3,
104 LOONGARCH_GPR_T4,
105 LOONGARCH_GPR_T5,
106 LOONGARCH_GPR_T6,
107 LOONGARCH_GPR_T7,
108 LOONGARCH_GPR_T8,
109 LOONGARCH_GPR_FP = 22,
110 LOONGARCH_GPR_S0 = 23,
111 LOONGARCH_GPR_S1,
112 LOONGARCH_GPR_S2,
113 LOONGARCH_GPR_S3,
114 LOONGARCH_GPR_S4,
115 LOONGARCH_GPR_S5,
116 LOONGARCH_GPR_S6,
117 LOONGARCH_GPR_S7,
118 LOONGARCH_GPR_S8,
119 LOONGARCH_GPR_MAX
120 };
121
122 #define INSN_NOP 0x03400000
123 #define INSN_BREAK 0x002a0000
124
125 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
126 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
127 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
128
129 #define ADDR_IMMSHIFT_ADDU16ID 16
130 #define ADDR_IMMSHIFT_LU32ID 32
131 #define ADDR_IMMSHIFT_LU52ID 52
132
133 #define ADDR_IMM(addr, INSN) ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN)
134
135 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc);
136 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign);
137 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n);
138
cond_beqz(struct pt_regs *regs, int rj)139 static inline bool cond_beqz(struct pt_regs *regs, int rj)
140 {
141 return regs->regs[rj] == 0;
142 }
143
cond_bnez(struct pt_regs *regs, int rj)144 static inline bool cond_bnez(struct pt_regs *regs, int rj)
145 {
146 return regs->regs[rj] != 0;
147 }
148
cond_beq(struct pt_regs *regs, int rj, int rd)149 static inline bool cond_beq(struct pt_regs *regs, int rj, int rd)
150 {
151 return regs->regs[rj] == regs->regs[rd];
152 }
153
cond_bne(struct pt_regs *regs, int rj, int rd)154 static inline bool cond_bne(struct pt_regs *regs, int rj, int rd)
155 {
156 return regs->regs[rj] != regs->regs[rd];
157 }
158
cond_blt(struct pt_regs *regs, int rj, int rd)159 static inline bool cond_blt(struct pt_regs *regs, int rj, int rd)
160 {
161 return (long)regs->regs[rj] < (long)regs->regs[rd];
162 }
163
cond_bge(struct pt_regs *regs, int rj, int rd)164 static inline bool cond_bge(struct pt_regs *regs, int rj, int rd)
165 {
166 return (long)regs->regs[rj] >= (long)regs->regs[rd];
167 }
168
cond_bltu(struct pt_regs *regs, int rj, int rd)169 static inline bool cond_bltu(struct pt_regs *regs, int rj, int rd)
170 {
171 return regs->regs[rj] < regs->regs[rd];
172 }
173
cond_bgeu(struct pt_regs *regs, int rj, int rd)174 static inline bool cond_bgeu(struct pt_regs *regs, int rj, int rd)
175 {
176 return regs->regs[rj] >= regs->regs[rd];
177 }
178
is_branch_insn(union loongarch_instruction insn)179 static inline bool is_branch_insn(union loongarch_instruction insn)
180 {
181 return insn.reg1i21_format.opcode >= beqz_op &&
182 insn.reg1i21_format.opcode <= bgeu_op;
183 }
184
is_pc_insn(union loongarch_instruction insn)185 static inline bool is_pc_insn(union loongarch_instruction insn)
186 {
187 return insn.reg1i20_format.opcode >= pcaddi_op &&
188 insn.reg1i20_format.opcode <= pcaddu18i_op;
189 }
190
191 unsigned long bs_dest_16(unsigned long now, unsigned int si);
192 unsigned long bs_dest_21(unsigned long now, unsigned int h, unsigned int l);
193 unsigned long bs_dest_26(unsigned long now, unsigned int h, unsigned int l);
194
195 int simu_branch(struct pt_regs *regs, union loongarch_instruction insn);
196 int simu_pc(struct pt_regs *regs, union loongarch_instruction insn);
197
198 int larch_insn_read(void *addr, u32 *insnp);
199 int larch_insn_write(void *addr, u32 insn);
200 int larch_insn_patch_text(void *addr, u32 insn);
201
202 u32 larch_insn_gen_nop(void);
203 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
204 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest);
205
206 u32 larch_insn_gen_addu16id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
207 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
208 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
209
210 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj,
211 unsigned long pc, unsigned long dest);
212
213 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj,
214 enum loongarch_gpr rk);
215 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
216
217 #endif /* _ASM_INST_H */
218