1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Based on arch/arm/mm/proc.S
4  *
5  * Copyright (C) 2001 Deep Blue Solutions Ltd.
6  * Copyright (C) 2012 ARM Ltd.
7  * Author: Catalin Marinas <catalin.marinas@arm.com>
8  */
9 
10 #include <linux/init.h>
11 #include <linux/linkage.h>
12 #include <linux/pgtable.h>
13 #include <asm/assembler.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/asm_pointer_auth.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/cpufeature.h>
19 #include <asm/alternative.h>
20 #include <asm/smp.h>
21 #include <asm/sysreg.h>
22 
23 #ifdef CONFIG_ARM64_64K_PAGES
24 #define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
25 #elif defined(CONFIG_ARM64_16K_PAGES)
26 #define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
27 #else /* CONFIG_ARM64_4K_PAGES */
28 #define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
29 #endif
30 
31 #ifdef CONFIG_RANDOMIZE_BASE
32 #define TCR_KASLR_FLAGS	TCR_NFD1
33 #else
34 #define TCR_KASLR_FLAGS	0
35 #endif
36 
37 #define TCR_SMP_FLAGS	TCR_SHARED
38 
39 /* PTWs cacheable, inner/outer WBWA */
40 #define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
41 
42 #ifdef CONFIG_KASAN_SW_TAGS
43 #define TCR_KASAN_FLAGS TCR_TBI1
44 #else
45 #define TCR_KASAN_FLAGS 0
46 #endif
47 
48 /*
49  * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
50  * changed during __cpu_setup to Normal Tagged if the system supports MTE.
51  */
52 #define MAIR_EL1_SET							\
53 	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
54 	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
55 	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |		\
56 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
57 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
58 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |		\
59 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
60 
61 #ifdef CONFIG_CPU_PM
62 /**
63  * cpu_do_suspend - save CPU registers context
64  *
65  * x0: virtual address of context pointer
66  *
67  * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
68  */
69 SYM_FUNC_START(cpu_do_suspend)
70 	mrs	x2, tpidr_el0
71 	mrs	x3, tpidrro_el0
72 	mrs	x4, contextidr_el1
73 	mrs	x5, osdlr_el1
74 	mrs	x6, cpacr_el1
75 	mrs	x7, tcr_el1
76 	mrs	x8, vbar_el1
77 	mrs	x9, mdscr_el1
78 	mrs	x10, oslsr_el1
79 	mrs	x11, sctlr_el1
80 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
81 	mrs	x12, tpidr_el1
82 alternative_else
83 	mrs	x12, tpidr_el2
84 alternative_endif
85 	mrs	x13, sp_el0
86 	stp	x2, x3, [x0]
87 	stp	x4, x5, [x0, #16]
88 	stp	x6, x7, [x0, #32]
89 	stp	x8, x9, [x0, #48]
90 	stp	x10, x11, [x0, #64]
91 	stp	x12, x13, [x0, #80]
92 	/*
93 	 * Save x18 as it may be used as a platform register, e.g. by shadow
94 	 * call stack.
95 	 */
96 	str	x18, [x0, #96]
97 	ret
98 SYM_FUNC_END(cpu_do_suspend)
99 
100 /**
101  * cpu_do_resume - restore CPU register context
102  *
103  * x0: Address of context pointer
104  */
105 	.pushsection ".idmap.text", "awx"
106 SYM_FUNC_START(cpu_do_resume)
107 	ldp	x2, x3, [x0]
108 	ldp	x4, x5, [x0, #16]
109 	ldp	x6, x8, [x0, #32]
110 	ldp	x9, x10, [x0, #48]
111 	ldp	x11, x12, [x0, #64]
112 	ldp	x13, x14, [x0, #80]
113 	/*
114 	 * Restore x18, as it may be used as a platform register, and clear
115 	 * the buffer to minimize the risk of exposure when used for shadow
116 	 * call stack.
117 	 */
118 	ldr	x18, [x0, #96]
119 	str	xzr, [x0, #96]
120 	msr	tpidr_el0, x2
121 	msr	tpidrro_el0, x3
122 	msr	contextidr_el1, x4
123 	msr	cpacr_el1, x6
124 
125 	/* Don't change t0sz here, mask those bits when restoring */
126 	mrs	x7, tcr_el1
127 	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
128 
129 	msr	tcr_el1, x8
130 	msr	vbar_el1, x9
131 
132 	/*
133 	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
134 	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
135 	 * exception. Mask them until local_daif_restore() in cpu_suspend()
136 	 * resets them.
137 	 */
138 	disable_daif
139 	msr	mdscr_el1, x10
140 
141 	msr	sctlr_el1, x12
142 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
143 	msr	tpidr_el1, x13
144 alternative_else
145 	msr	tpidr_el2, x13
146 alternative_endif
147 	msr	sp_el0, x14
148 	/*
149 	 * Restore oslsr_el1 by writing oslar_el1
150 	 */
151 	msr	osdlr_el1, x5
152 	ubfx	x11, x11, #1, #1
153 	msr	oslar_el1, x11
154 	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
155 	reset_amuserenr_el0 x0			// Disable AMU access from EL0
156 
157 alternative_if ARM64_HAS_RAS_EXTN
158 	msr_s	SYS_DISR_EL1, xzr
159 alternative_else_nop_endif
160 
161 	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
162 	isb
163 	ret
164 SYM_FUNC_END(cpu_do_resume)
165 	.popsection
166 #endif
167 
168 	.pushsection ".idmap.text", "awx"
169 
170 .macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
171 	adrp	\tmp1, reserved_pg_dir
172 	phys_to_ttbr \tmp2, \tmp1
173 	offset_ttbr1 \tmp2, \tmp1
174 	msr	ttbr1_el1, \tmp2
175 	isb
176 	tlbi	vmalle1
177 	dsb	nsh
178 	isb
179 .endm
180 
181 /*
182  * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
183  *
184  * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
185  * called by anything else. It can only be executed from a TTBR0 mapping.
186  */
187 SYM_FUNC_START(idmap_cpu_replace_ttbr1)
188 	save_and_disable_daif flags=x2
189 
190 	__idmap_cpu_set_reserved_ttbr1 x1, x3
191 
192 	offset_ttbr1 x0, x3
193 	msr	ttbr1_el1, x0
194 	isb
195 
196 	restore_daif x2
197 
198 	ret
199 SYM_FUNC_END(idmap_cpu_replace_ttbr1)
200 	.popsection
201 
202 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
203 	.pushsection ".idmap.text", "awx"
204 
205 	.macro	__idmap_kpti_get_pgtable_ent, type
206 	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
207 	dmb	sy				// lines are written back before
208 	ldr	\type, [cur_\()\type\()p]	// loading the entry
209 	tbz	\type, #0, skip_\()\type	// Skip invalid and
210 	tbnz	\type, #11, skip_\()\type	// non-global entries
211 	.endm
212 
213 	.macro __idmap_kpti_put_pgtable_ent_ng, type
214 	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
215 	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
216 	dmb	sy				// that it is visible to all
217 	dc	civac, cur_\()\type\()p		// CPUs.
218 	.endm
219 
220 /*
221  * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
222  *
223  * Called exactly once from stop_machine context by each CPU found during boot.
224  */
225 __idmap_kpti_flag:
226 	.long	1
227 SYM_FUNC_START(idmap_kpti_install_ng_mappings)
228 	cpu		.req	w0
229 	num_cpus	.req	w1
230 	swapper_pa	.req	x2
231 	swapper_ttb	.req	x3
232 	flag_ptr	.req	x4
233 	cur_pgdp	.req	x5
234 	end_pgdp	.req	x6
235 	pgd		.req	x7
236 	cur_pudp	.req	x8
237 	end_pudp	.req	x9
238 	pud		.req	x10
239 	cur_pmdp	.req	x11
240 	end_pmdp	.req	x12
241 	pmd		.req	x13
242 	cur_ptep	.req	x14
243 	end_ptep	.req	x15
244 	pte		.req	x16
245 
246 	mrs	swapper_ttb, ttbr1_el1
247 	restore_ttbr1	swapper_ttb
248 	adr	flag_ptr, __idmap_kpti_flag
249 
250 	cbnz	cpu, __idmap_kpti_secondary
251 
252 	/* We're the boot CPU. Wait for the others to catch up */
253 	sevl
254 1:	wfe
255 	ldaxr	w17, [flag_ptr]
256 	eor	w17, w17, num_cpus
257 	cbnz	w17, 1b
258 
259 	/* We need to walk swapper, so turn off the MMU. */
260 	pre_disable_mmu_workaround
261 	mrs	x17, sctlr_el1
262 	bic	x17, x17, #SCTLR_ELx_M
263 	msr	sctlr_el1, x17
264 	isb
265 
266 	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
267 	/* PGD */
268 	mov	cur_pgdp, swapper_pa
269 	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
270 do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
271 	tbnz	pgd, #1, walk_puds
272 next_pgd:
273 	__idmap_kpti_put_pgtable_ent_ng	pgd
274 skip_pgd:
275 	add	cur_pgdp, cur_pgdp, #8
276 	cmp	cur_pgdp, end_pgdp
277 	b.ne	do_pgd
278 
279 	/* Publish the updated tables and nuke all the TLBs */
280 	dsb	sy
281 	tlbi	vmalle1is
282 	dsb	ish
283 	isb
284 
285 	/* We're done: fire up the MMU again */
286 	mrs	x17, sctlr_el1
287 	orr	x17, x17, #SCTLR_ELx_M
288 	msr	sctlr_el1, x17
289 	isb
290 
291 	/*
292 	 * Invalidate the local I-cache so that any instructions fetched
293 	 * speculatively from the PoC are discarded, since they may have
294 	 * been dynamically patched at the PoU.
295 	 */
296 	ic	iallu
297 	dsb	nsh
298 	isb
299 
300 	/* Set the flag to zero to indicate that we're all done */
301 	str	wzr, [flag_ptr]
302 	ret
303 
304 	/* PUD */
305 walk_puds:
306 	.if CONFIG_PGTABLE_LEVELS > 3
307 	pte_to_phys	cur_pudp, pgd
308 	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
309 do_pud:	__idmap_kpti_get_pgtable_ent	pud
310 	tbnz	pud, #1, walk_pmds
311 next_pud:
312 	__idmap_kpti_put_pgtable_ent_ng	pud
313 skip_pud:
314 	add	cur_pudp, cur_pudp, 8
315 	cmp	cur_pudp, end_pudp
316 	b.ne	do_pud
317 	b	next_pgd
318 	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
319 	mov	pud, pgd
320 	b	walk_pmds
321 next_pud:
322 	b	next_pgd
323 	.endif
324 
325 	/* PMD */
326 walk_pmds:
327 	.if CONFIG_PGTABLE_LEVELS > 2
328 	pte_to_phys	cur_pmdp, pud
329 	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
330 do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
331 	tbnz	pmd, #1, walk_ptes
332 next_pmd:
333 	__idmap_kpti_put_pgtable_ent_ng	pmd
334 skip_pmd:
335 	add	cur_pmdp, cur_pmdp, #8
336 	cmp	cur_pmdp, end_pmdp
337 	b.ne	do_pmd
338 	b	next_pud
339 	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
340 	mov	pmd, pud
341 	b	walk_ptes
342 next_pmd:
343 	b	next_pud
344 	.endif
345 
346 	/* PTE */
347 walk_ptes:
348 	pte_to_phys	cur_ptep, pmd
349 	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
350 do_pte:	__idmap_kpti_get_pgtable_ent	pte
351 	__idmap_kpti_put_pgtable_ent_ng	pte
352 skip_pte:
353 	add	cur_ptep, cur_ptep, #8
354 	cmp	cur_ptep, end_ptep
355 	b.ne	do_pte
356 	b	next_pmd
357 
358 	.unreq	cpu
359 	.unreq	num_cpus
360 	.unreq	swapper_pa
361 	.unreq	cur_pgdp
362 	.unreq	end_pgdp
363 	.unreq	pgd
364 	.unreq	cur_pudp
365 	.unreq	end_pudp
366 	.unreq	pud
367 	.unreq	cur_pmdp
368 	.unreq	end_pmdp
369 	.unreq	pmd
370 	.unreq	cur_ptep
371 	.unreq	end_ptep
372 	.unreq	pte
373 
374 	/* Secondary CPUs end up here */
375 __idmap_kpti_secondary:
376 	/* Uninstall swapper before surgery begins */
377 	__idmap_cpu_set_reserved_ttbr1 x16, x17
378 
379 	/* Increment the flag to let the boot CPU we're ready */
380 1:	ldxr	w16, [flag_ptr]
381 	add	w16, w16, #1
382 	stxr	w17, w16, [flag_ptr]
383 	cbnz	w17, 1b
384 
385 	/* Wait for the boot CPU to finish messing around with swapper */
386 	sevl
387 1:	wfe
388 	ldxr	w16, [flag_ptr]
389 	cbnz	w16, 1b
390 
391 	/* All done, act like nothing happened */
392 	offset_ttbr1 swapper_ttb, x16
393 	msr	ttbr1_el1, swapper_ttb
394 	isb
395 	ret
396 
397 	.unreq	swapper_ttb
398 	.unreq	flag_ptr
399 SYM_FUNC_END(idmap_kpti_install_ng_mappings)
400 	.popsection
401 #endif
402 
403 /*
404  *	__cpu_setup
405  *
406  *	Initialise the processor for turning the MMU on.
407  *
408  * Output:
409  *	Return in x0 the value of the SCTLR_EL1 register.
410  */
411 	.pushsection ".idmap.text", "awx"
412 SYM_FUNC_START(__cpu_setup)
413 	tlbi	vmalle1				// Invalidate local TLB
414 	dsb	nsh
415 
416 	mov	x1, #3 << 20
417 	msr	cpacr_el1, x1			// Enable FP/ASIMD
418 	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
419 	msr	mdscr_el1, x1			// access to the DCC from EL0
420 	isb					// Unmask debug exceptions now,
421 	enable_dbg				// since this is per-cpu
422 	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
423 	reset_amuserenr_el0 x1			// Disable AMU access from EL0
424 
425 	/*
426 	 * Memory region attributes
427 	 */
428 	mov_q	x5, MAIR_EL1_SET
429 #ifdef CONFIG_ARM64_MTE
430 	/*
431 	 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
432 	 * (ID_AA64PFR1_EL1[11:8] > 1).
433 	 */
434 	mrs	x10, ID_AA64PFR1_EL1
435 	ubfx	x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
436 	cmp	x10, #ID_AA64PFR1_MTE
437 	b.lt	1f
438 
439 	/* Normal Tagged memory type at the corresponding MAIR index */
440 	mov	x10, #MAIR_ATTR_NORMAL_TAGGED
441 	bfi	x5, x10, #(8 *  MT_NORMAL_TAGGED), #8
442 
443 	/* initialize GCR_EL1: all non-zero tags excluded by default */
444 	mov	x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
445 	msr_s	SYS_GCR_EL1, x10
446 
447 	/*
448 	 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
449 	 * RGSR_EL1.SEED must be non-zero for IRG to produce
450 	 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
451 	 * must initialize it.
452 	 */
453 	mrs	x10, CNTVCT_EL0
454 	ands	x10, x10, #SYS_RGSR_EL1_SEED_MASK
455 	csinc	x10, x10, xzr, ne
456 	lsl	x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
457 	msr_s	SYS_RGSR_EL1, x10
458 
459 	/* clear any pending tag check faults in TFSR*_EL1 */
460 	msr_s	SYS_TFSR_EL1, xzr
461 	msr_s	SYS_TFSRE0_EL1, xzr
462 1:
463 #endif
464 	msr	mair_el1, x5
465 	/*
466 	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
467 	 * both user and kernel.
468 	 */
469 	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
470 			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
471 			TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
472 	tcr_clear_errata_bits x10, x9, x5
473 
474 #ifdef CONFIG_ARM64_VA_BITS_52
475 	ldr_l		x9, vabits_actual
476 	sub		x9, xzr, x9
477 	add		x9, x9, #64
478 	tcr_set_t1sz	x10, x9
479 #else
480 	ldr_l		x9, idmap_t0sz
481 #endif
482 	tcr_set_t0sz	x10, x9
483 
484 	/*
485 	 * Set the IPS bits in TCR_EL1.
486 	 */
487 	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
488 #ifdef CONFIG_ARM64_HW_AFDBM
489 	/*
490 	 * Enable hardware update of the Access Flags bit.
491 	 * Hardware dirty bit management is enabled later,
492 	 * via capabilities.
493 	 */
494 	mrs	x9, ID_AA64MMFR1_EL1
495 	and	x9, x9, #0xf
496 	cbz	x9, 1f
497 	orr	x10, x10, #TCR_HA		// hardware Access flag update
498 1:
499 #endif	/* CONFIG_ARM64_HW_AFDBM */
500 	msr	tcr_el1, x10
501 	/*
502 	 * Prepare SCTLR
503 	 */
504 	mov_q	x0, SCTLR_EL1_SET
505 	ret					// return to head.S
506 SYM_FUNC_END(__cpu_setup)
507