18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 48c2ecf20Sopenharmony_ci * Author: Tony Xie <tony.xie@rock-chips.com> 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#include <linux/linkage.h> 88c2ecf20Sopenharmony_ci#include <asm/assembler.h> 98c2ecf20Sopenharmony_ci#include <asm/memory.h> 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci.data 128c2ecf20Sopenharmony_ci/* 138c2ecf20Sopenharmony_ci * this code will be copied from 148c2ecf20Sopenharmony_ci * ddr to sram for system resumeing. 158c2ecf20Sopenharmony_ci * so it is ".data section". 168c2ecf20Sopenharmony_ci */ 178c2ecf20Sopenharmony_ci .align 2 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciENTRY(rockchip_slp_cpu_resume) 208c2ecf20Sopenharmony_ci setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off 218c2ecf20Sopenharmony_ci mrc p15, 0, r1, c0, c0, 5 228c2ecf20Sopenharmony_ci and r1, r1, #0xf 238c2ecf20Sopenharmony_ci cmp r1, #0 248c2ecf20Sopenharmony_ci /* olny cpu0 can continue to run, the others is halt here */ 258c2ecf20Sopenharmony_ci beq cpu0run 268c2ecf20Sopenharmony_cisecondary_loop: 278c2ecf20Sopenharmony_ci wfe 288c2ecf20Sopenharmony_ci b secondary_loop 298c2ecf20Sopenharmony_cicpu0run: 308c2ecf20Sopenharmony_ci ldr r3, rkpm_bootdata_l2ctlr_f 318c2ecf20Sopenharmony_ci cmp r3, #0 328c2ecf20Sopenharmony_ci beq sp_set 338c2ecf20Sopenharmony_ci ldr r3, rkpm_bootdata_l2ctlr 348c2ecf20Sopenharmony_ci mcr p15, 1, r3, c9, c0, 2 358c2ecf20Sopenharmony_cisp_set: 368c2ecf20Sopenharmony_ci ldr sp, rkpm_bootdata_cpusp 378c2ecf20Sopenharmony_ci ldr r1, rkpm_bootdata_cpu_code 388c2ecf20Sopenharmony_ci bx r1 398c2ecf20Sopenharmony_ciENDPROC(rockchip_slp_cpu_resume) 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci/* Parameters filled in by the kernel */ 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci/* Flag for whether to restore L2CTLR on resume */ 448c2ecf20Sopenharmony_ci .global rkpm_bootdata_l2ctlr_f 458c2ecf20Sopenharmony_cirkpm_bootdata_l2ctlr_f: 468c2ecf20Sopenharmony_ci .long 0 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci/* Saved L2CTLR to restore on resume */ 498c2ecf20Sopenharmony_ci .global rkpm_bootdata_l2ctlr 508c2ecf20Sopenharmony_cirkpm_bootdata_l2ctlr: 518c2ecf20Sopenharmony_ci .long 0 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci/* CPU resume SP addr */ 548c2ecf20Sopenharmony_ci .globl rkpm_bootdata_cpusp 558c2ecf20Sopenharmony_cirkpm_bootdata_cpusp: 568c2ecf20Sopenharmony_ci .long 0 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci/* CPU resume function (physical address) */ 598c2ecf20Sopenharmony_ci .globl rkpm_bootdata_cpu_code 608c2ecf20Sopenharmony_cirkpm_bootdata_cpu_code: 618c2ecf20Sopenharmony_ci .long 0 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ciENTRY(rk3288_bootram_sz) 648c2ecf20Sopenharmony_ci .word . - rockchip_slp_cpu_resume 65