1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Tony Xie <tony.xie@rock-chips.com> 5 */ 6 7 #include <linux/linkage.h> 8 #include <asm/assembler.h> 9 #include <asm/memory.h> 10 11 .data 12 /* 13 * this code will be copied from 14 * ddr to sram for system resumeing. 15 * so it is ".data section". 16 */ 17 .align 2 18 19 ENTRY(rockchip_slp_cpu_resume) 20 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off 21 mrc p15, 0, r1, c0, c0, 5 22 and r1, r1, #0xf 23 cmp r1, #0 24 /* olny cpu0 can continue to run, the others is halt here */ 25 beq cpu0run 26 secondary_loop: 27 wfe 28 b secondary_loop 29 cpu0run: 30 ldr r3, rkpm_bootdata_l2ctlr_f 31 cmp r3, #0 32 beq sp_set 33 ldr r3, rkpm_bootdata_l2ctlr 34 mcr p15, 1, r3, c9, c0, 2 35 sp_set: 36 ldr sp, rkpm_bootdata_cpusp 37 ldr r1, rkpm_bootdata_cpu_code 38 bx r1 39 ENDPROC(rockchip_slp_cpu_resume) 40 41 /* Parameters filled in by the kernel */ 42 43 /* Flag for whether to restore L2CTLR on resume */ 44 .global rkpm_bootdata_l2ctlr_f 45 rkpm_bootdata_l2ctlr_f: 46 .long 0 47 48 /* Saved L2CTLR to restore on resume */ 49 .global rkpm_bootdata_l2ctlr 50 rkpm_bootdata_l2ctlr: 51 .long 0 52 53 /* CPU resume SP addr */ 54 .globl rkpm_bootdata_cpusp 55 rkpm_bootdata_cpusp: 56 .long 0 57 58 /* CPU resume function (physical address) */ 59 .globl rkpm_bootdata_cpu_code 60 rkpm_bootdata_cpu_code: 61 .long 0 62 63 ENTRY(rk3288_bootram_sz) 64 .word . - rockchip_slp_cpu_resume 65