1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S 4 * 5 * Based on linux/arch/arm/lib/floppydma.S 6 * Renamed and modified to work with 2.6 kernel by Matt Callow 7 * Copyright (C) 1995, 1996 Russell King 8 * Copyright (C) 2004 Pete Trapps 9 * Copyright (C) 2006 Matt Callow 10 * Copyright (C) 2010 Janusz Krzysztofik 11 */ 12 13 #include <linux/linkage.h> 14 #include <linux/platform_data/ams-delta-fiq.h> 15 #include <linux/platform_data/gpio-omap.h> 16 17 #include <asm/assembler.h> 18 #include <asm/irq.h> 19 20 #include "ams-delta-fiq.h" 21 #include "board-ams-delta.h" 22 #include "iomap.h" 23 #include "soc.h" 24 25 /* 26 * OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c. 27 * Unfortunately, it was not placed in a separate header file. 28 */ 29 #define OMAP1510_GPIO_BASE 0xFFFCE000 30 31 /* GPIO register bitmasks */ 32 #define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA) 33 #define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK) 34 #define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ) 35 #define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH) 36 #define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) 37 38 /* IRQ handler register bitmasks */ 39 #define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ) 40 #define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1) 41 42 /* Driver buffer byte offsets */ 43 #define BUF_MASK (FIQ_MASK * 4) 44 #define BUF_STATE (FIQ_STATE * 4) 45 #define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4) 46 #define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4) 47 #define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4) 48 #define BUF_BUF_LEN (FIQ_BUF_LEN * 4) 49 #define BUF_KEY (FIQ_KEY * 4) 50 #define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4) 51 #define BUF_BUFFER_START (FIQ_BUFFER_START * 4) 52 #define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4) 53 #define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4) 54 #define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4) 55 #define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4) 56 #define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4) 57 #define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4) 58 #define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4) 59 #define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4) 60 #define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4) 61 #define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4) 62 #define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4) 63 #define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4) 64 #define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4) 65 #define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4) 66 #define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4) 67 #define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4) 68 #define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4) 69 #define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4) 70 #define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4) 71 #define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4) 72 #define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4) 73 #define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4) 74 75 76 /* 77 * Register usage 78 * r8 - temporary 79 * r9 - the driver buffer 80 * r10 - temporary 81 * r11 - interrupts mask 82 * r12 - base pointers 83 * r13 - interrupts status 84 */ 85 86 .text 87 88 .global qwerty_fiqin_end 89 90 ENTRY(qwerty_fiqin_start) 91 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 92 @ FIQ intrrupt handler 93 ldr r12, omap_ih1_base @ set pointer to level1 handler 94 95 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask 96 97 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status 98 bics r13, r13, r11 @ clear masked - any left? 99 beq exit @ none - spurious FIQ? exit 100 101 ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number 102 103 mov r8, #2 @ reset FIQ agreement 104 str r8, [r12, #IRQ_CONTROL_REG_OFFSET] 105 106 cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt? 107 beq gpio @ yes - process it 108 109 mov r8, #1 110 orr r8, r11, r8, lsl r10 @ mask spurious interrupt 111 str r8, [r12, #IRQ_MIR_REG_OFFSET] 112 exit: 113 subs pc, lr, #4 @ return from FIQ 114 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 115 116 117 @@@@@@@@@@@@@@@@@@@@@@@@@@@ 118 gpio: @ GPIO bank interrupt handler 119 ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank 120 121 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask 122 restart: 123 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits 124 bics r13, r13, r11 @ clear masked - any left? 125 beq exit @ no - spurious interrupt? exit 126 127 orr r11, r11, r13 @ mask all requested interrupts 128 str r11, [r12, #OMAP1510_GPIO_INT_MASK] 129 130 str r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack all requested interrupts 131 132 ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set? 133 beq hksw @ no - try next source 134 135 136 @@@@@@@@@@@@@@@@@@@@@@ 137 @ Keyboard clock FIQ mode interrupt handler 138 @ r10 now contains KEYBRD_CLK_MASK, use it 139 bic r11, r11, r10 @ unmask it 140 str r11, [r12, #OMAP1510_GPIO_INT_MASK] 141 142 @ Process keyboard data 143 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input 144 145 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state 146 cmp r10, #0 @ are we expecting start bit? 147 bne data @ no - go to data processing 148 149 ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected? 150 beq hksw @ no - try next source 151 152 @ r8 contains KEYBRD_DATA_MASK, use it 153 str r8, [r9, #BUF_STATE] @ enter data processing state 154 @ r10 already contains 0, reuse it 155 str r10, [r9, #BUF_KEY] @ clear keycode 156 mov r10, #2 @ reset input bit mask 157 str r10, [r9, #BUF_MASK] 158 159 @ Mask other GPIO line interrupts till key done 160 str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore 161 mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask 162 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register 163 164 b restart @ restart 165 166 data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask 167 168 @ r8 still contains GPIO input bits 169 ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low? 170 ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far, 171 orreq r8, r8, r10 @ set 1 at current mask position 172 streq r8, [r9, #BUF_KEY] @ and save back 173 174 mov r10, r10, lsl #1 @ shift mask left 175 bics r10, r10, #0x800 @ have we got all the bits? 176 strne r10, [r9, #BUF_MASK] @ not yet - store the mask 177 bne restart @ and restart 178 179 @ r10 already contains 0, reuse it 180 str r10, [r9, #BUF_STATE] @ reset state to start 181 182 @ Key done - restore interrupt mask 183 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask 184 and r11, r11, r10 @ unmask all saved as unmasked 185 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register 186 187 @ Try appending the keycode to the circular buffer 188 ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count 189 ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size 190 cmp r10, r8 @ is buffer full? 191 beq hksw @ yes - key lost, next source 192 193 add r10, r10, #1 @ incremet keystrokes counter 194 str r10, [r9, #BUF_KEYS_CNT] 195 196 ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset 197 @ r8 already contains buffer size 198 cmp r10, r8 @ end of buffer? 199 moveq r10, #0 @ yes - rewind to buffer start 200 201 ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address 202 add r12, r12, r10, LSL #2 @ calculate buffer tail address 203 ldr r8, [r9, #BUF_KEY] @ get last keycode 204 str r8, [r12] @ append it to the buffer tail 205 206 add r10, r10, #1 @ increment buffer tail offset 207 str r10, [r9, #BUF_TAIL_OFFSET] 208 209 ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter 210 add r10, r10, #1 211 str r10, [r9, #BUF_CNT_INT_KEY] 212 @@@@@@@@@@@@@@@@@@@@@@@@ 213 214 215 hksw: @Is hook switch interrupt requested? 216 tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set? 217 beq mdm @ no - try next source 218 219 220 @@@@@@@@@@@@@@@@@@@@@@@@ 221 @ Hook switch interrupt FIQ mode simple handler 222 223 @ Don't toggle active edge, the switch always bounces 224 225 @ Increment hook switch interrupt counter 226 ldr r10, [r9, #BUF_CNT_INT_HSW] 227 add r10, r10, #1 228 str r10, [r9, #BUF_CNT_INT_HSW] 229 @@@@@@@@@@@@@@@@@@@@@@@@ 230 231 232 mdm: @Is it a modem interrupt? 233 tst r13, #MODEM_IRQ_MASK @ is modem status bit set? 234 beq irq @ no - check for next interrupt 235 236 237 @@@@@@@@@@@@@@@@@@@@@@@@ 238 @ Modem FIQ mode interrupt handler stub 239 240 @ Increment modem interrupt counter 241 ldr r10, [r9, #BUF_CNT_INT_MDM] 242 add r10, r10, #1 243 str r10, [r9, #BUF_CNT_INT_MDM] 244 @@@@@@@@@@@@@@@@@@@@@@@@ 245 246 247 irq: @ Place deferred_fiq interrupt request 248 ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler 249 mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit 250 str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register 251 252 ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank 253 b restart @ check for next GPIO interrupt 254 @@@@@@@@@@@@@@@@@@@@@@@@@@@ 255 256 257 /* 258 * Virtual addresses for IO 259 */ 260 omap_ih1_base: 261 .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE) 262 deferred_fiq_ih_base: 263 .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE) 264 omap1510_gpio_base: 265 .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE) 266 qwerty_fiqin_end: 267 268 /* 269 * Check the size of the FIQ, 270 * it cannot go beyond 0xffff0200, and is copied to 0xffff001c 271 */ 272 .if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c) 273 .err 274 .endif 275