1 /** 2 * Copyright (c) 2024 Bosch Sensortec GmbH. All rights reserved. 3 * 4 * accel_bmi270.h as part of the * /chipsets subdirectory 5 * is dual licensed: you can use it either under the terms of 6 * the GPL, or the BSD license, at your option. 7 * See the LICENSE file in the root of this repository for complete details. 8 */ 9 10 #ifndef ACC_BMI270_H 11 #define ACC_BMI270_H 12 13 #include "sensor_accel_driver.h" 14 #include "sensor_config_parser.h" 15 16 #define BMI270_ACC_DATA_FRAME_SIZE 6 17 #define BMI270_ONE_BYTE sizeof(uint8_t) 18 #define BMI270_TWO_BYTE sizeof(uint16_t) 19 20 // bus operation delay 21 #define BMI270_NORMAL_MODE_WRITE_DELAY_IN_US 4 22 #define BMI270_LP_MODE_WRITE_DELAY_IN_US 460 23 24 // feature operation delay 25 #define BMI270_RESET_DELAY_IN_MS 5 26 #define BMI270_LOAD_RAM_PATCH_DELAY_IN_MS 10 27 28 // bit definition 29 #define BMI270_ACC_POWER_BIT_POS_IN_PWR_CTRL_REG 2 30 31 #define BST_GET_VAL_BIT(val, bit) (((val) >> (bit)) & 0x01) 32 #define BST_GET_VAL_BITBLOCK(val, start, end) (((val) >> (start)) & ((1 << (end - start + 1))-1)) 33 34 #define BST_SET_VAL_BIT(val, bit) (val | (1 << (bit))) 35 #define BST_CLR_VAL_BIT(val, bit) (val & (~(1 << (bit)))) 36 37 #define BMI270_ACCEL_REGA_STATUS 0X03 38 #define BMI270_ACCEL_REGA_X_LSB_ADDR 0X0C 39 #define BMI270_ACCEL_REGA_X_MSB_ADDR 0X0D 40 #define BMI270_ACCEL_REGA_Y_LSB_ADDR 0X0E 41 #define BMI270_ACCEL_REGA_Y_MSB_ADDR 0X0F 42 #define BMI270_ACCEL_REGA_Z_LSB_ADDR 0X10 43 #define BMI270_ACCEL_REGA_Z_MSB_ADDR 0X11 44 #define BMI270_ACCEL_REGA_INT_STATUS 0X1D 45 46 /* ACCEL ODR */ 47 #define BMI270_ACCEL_REGA_ODR_RESERVED 0x00 48 #define BMI270_ACCEL_REGA_ODR_0_78HZ 0x01 49 #define BMI270_ACCEL_REGA_ODR_1_56HZ 0x02 50 #define BMI270_ACCEL_REGA_ODR_3_12HZ 0x03 51 #define BMI270_ACCEL_REGA_ODR_6_25HZ 0x04 52 #define BMI270_ACCEL_REGA_ODR_12_5HZ 0x05 53 #define BMI270_ACCEL_REGA_ODR_25HZ 0x06 54 #define BMI270_ACCEL_REGA_ODR_50HZ 0x07 55 #define BMI270_ACCEL_REGA_ODR_100HZ 0x08 56 #define BMI270_ACCEL_REGA_ODR_200HZ 0x09 57 #define BMI270_ACCEL_REGA_ODR_400HZ 0x0A 58 #define BMI270_ACCEL_REGA_ODR_800HZ 0x0B 59 #define BMI270_ACCEL_REGA_ODR_1600HZ 0x0C 60 #define BMI270_ACCEL_REGA_ODR_RESERVED0 0x0D 61 #define BMI270_ACCEL_REGA_ODR_RESERVED1 0x0E 62 #define BMI270_ACCEL_REGA_ODR_RESERVED2 0x0F 63 64 65 #define BMI270_REGA_INTERNAL_STATUS 0x21 66 67 #define BMI26X_REGA_ACC_ODR 0x40 68 #define BMI26X_REGA_ACC_RANGE 0x41 69 #define BMI26X_REGA_USR_ERR_REG_MASK 0x52 70 #define BMI26X_REGA_USR_INT1_IO_CTRL 0x53 71 #define BMI26X_REGA_USR_INT2_IO_CTRL 0x54 72 #define BMI26X_REGA_USR_INT_LATCH 0x55 73 #define BMI26X_REGA_USR_INT1_MAP 0x56 74 #define BMI26X_REGA_USR_INT2_MAP 0x57 75 #define BMI26X_REGA_USR_INT_MAP_HW 0x58 76 #define BMI26X_REGA_USR_TITAN_CTRL 0x59 77 #define BMI26X_REGA_USR_CONF_STREAM_IDX_LSB 0x5b 78 #define BMI26X_REGA_USR_CONF_STREAM_IN 0x5e 79 #define BMI26X_REGA_USR_INTERNAL_ERROR 0x5f 80 81 #define BMI270_REGA_PWR_CFG 0x7C 82 #define BMI270_REGA_PWR_CTRL 0x7D 83 #define BMI26X_REGA_USR_CMD 0x7E 84 85 #define BMI26X_REGV_WHOAMI 0x24 86 #define BMI26X_REGV_CMD_SOFT_RESET 0xB6 87 88 /* default HZ */ 89 #define BMI270_ACCEL_DEFAULT_ODR_100HZ 100 /*hw defualt value @0x8*/ 90 #define BMI270_ACCEL_DEFAULT_ODR_25HZ 25 91 92 #define BMI26X_CHECK_CONFIGURE_STATUS_TIMES 15 93 #define BMI270_ACCEL_DATA_READY_MASK 0x80 94 95 #define BMI270_ACC_ODR_FILTER_DEFAULT 0xA0 96 97 /* ACC sensitivity */ 98 #define BMI270_ACC_SENSITIVITY_2G 61 99 #define BMI270_ACC_SENSITIVITY_4G 122 100 #define BMI270_ACC_SENSITIVITY_8G 244 101 #define BMI270_ACC_SENSITIVITY_16G 488 102 103 struct Bmi270DrvData { 104 struct IDeviceIoService ioService; 105 struct HdfDeviceObject *device; 106 struct SensorCfgData *sensorCfg; 107 }; 108 109 #endif /* ACC_BMI270_H */ 110