1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov13855 camera driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 fix some errors.
9 * V0.0X01.0X02 add get_selection.
10 *
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/sysfs.h>
22 #include <linux/slab.h>
23 #include <linux/version.h>
24 #include <linux/compat.h>
25 #include <linux/rk-camera-module.h>
26 #include <media/media-entity.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-subdev.h>
30 #include <linux/pinctrl/consumer.h>
31
32 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
33
34 #ifndef V4L2_CID_DIGITAL_GAIN
35 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36 #endif
37
38 #define OV13855_LINK_FREQ_540MHZ 540000000U
39 #define OV13855_LINK_FREQ_270MHZ 270000000U
40 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
41 #define OV13855_PIXEL_RATE (OV13855_LINK_FREQ_540MHZ * 2LL * 4LL / 10LL)
42 #define OV13855_XVCLK_FREQ 24000000
43
44 #define CHIP_ID 0x00d855
45 #define OV13855_REG_CHIP_ID 0x300a
46
47 #define OV13855_REG_CTRL_MODE 0x0100
48 #define OV13855_MODE_SW_STANDBY 0x0
49 #define OV13855_MODE_STREAMING BIT(0)
50
51 #define OV13855_REG_EXPOSURE 0x3500
52 #define OV13855_EXPOSURE_MIN 4
53 #define OV13855_EXPOSURE_STEP 1
54 #define OV13855_VTS_MAX 0x7fff
55
56 #define OV13855_REG_GAIN_H 0x3508
57 #define OV13855_REG_GAIN_L 0x3509
58 #define OV13855_GAIN_H_MASK 0x1f
59 #define OV13855_GAIN_H_SHIFT 8
60 #define OV13855_GAIN_L_MASK 0xff
61 #define OV13855_GAIN_MIN 0x80
62 #define OV13855_GAIN_MAX 0x7c0
63 #define OV13855_GAIN_STEP 1
64 #define OV13855_GAIN_DEFAULT 0x80
65
66 #define OV13855_REG_TEST_PATTERN 0x5e00
67 #define OV13855_TEST_PATTERN_ENABLE 0x80
68 #define OV13855_TEST_PATTERN_DISABLE 0x0
69
70 #define OV13855_REG_VTS 0x380e
71
72 #define REG_NULL 0xFFFF
73
74 #define OV13855_REG_VALUE_08BIT 1
75 #define OV13855_REG_VALUE_16BIT 2
76 #define OV13855_REG_VALUE_24BIT 3
77
78 #define OV13855_LANES 4
79 #define OV13855_BITS_PER_SAMPLE 10
80
81 #define OV13855_CHIP_REVISION_REG 0x302A
82
83 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
84 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
85
86 #define OV13855_NAME "ov13855"
87 #define OV13855_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
88
89 static const char * const ov13855_supply_names[] = {
90 "avdd", /* Analog power */
91 "dovdd", /* Digital I/O power */
92 "dvdd", /* Digital core power */
93 };
94
95 #define OV13855_NUM_SUPPLIES ARRAY_SIZE(ov13855_supply_names)
96
97 struct regval {
98 u16 addr;
99 u8 val;
100 };
101
102 struct ov13855_mode {
103 u32 width;
104 u32 height;
105 struct v4l2_fract max_fps;
106 u32 hts_def;
107 u32 vts_def;
108 u32 exp_def;
109 u32 link_freq_idx;
110 u32 bpp;
111 const struct regval *reg_list;
112 };
113
114 struct ov13855 {
115 struct i2c_client *client;
116 struct clk *xvclk;
117 struct gpio_desc *power_gpio;
118 struct gpio_desc *reset_gpio;
119 struct gpio_desc *pwdn_gpio;
120 struct regulator_bulk_data supplies[OV13855_NUM_SUPPLIES];
121
122 struct pinctrl *pinctrl;
123 struct pinctrl_state *pins_default;
124 struct pinctrl_state *pins_sleep;
125
126 struct v4l2_subdev subdev;
127 struct media_pad pad;
128 struct v4l2_ctrl_handler ctrl_handler;
129 struct v4l2_ctrl *exposure;
130 struct v4l2_ctrl *anal_gain;
131 struct v4l2_ctrl *digi_gain;
132 struct v4l2_ctrl *hblank;
133 struct v4l2_ctrl *vblank;
134 struct v4l2_ctrl *pixel_rate;
135 struct v4l2_ctrl *link_freq;
136 struct v4l2_ctrl *test_pattern;
137 struct mutex mutex;
138 bool streaming;
139 bool power_on;
140 const struct ov13855_mode *cur_mode;
141 u32 module_index;
142 const char *module_facing;
143 const char *module_name;
144 const char *len_name;
145 };
146
147 #define to_ov13855(sd) container_of(sd, struct ov13855, subdev)
148
149 /*
150 * Xclk 24Mhz
151 */
152 static const struct regval ov13855_global_regs[] = {
153 {0x0103, 0x01},
154 {0x0300, 0x02},
155 {0x0301, 0x00},
156 {0x0302, 0x5a},
157 {0x0303, 0x00},
158 {0x0304, 0x00},
159 {0x0305, 0x01},
160 {0x030b, 0x06},
161 {0x030c, 0x02},
162 {0x030d, 0x88},
163 {0x0312, 0x11},
164 {0x3022, 0x01},
165 {0x3013, 0x32},
166 {0x3016, 0x72},
167 {0x301b, 0xF0},
168 {0x301f, 0xd0},
169 {0x3106, 0x15},
170 {0x3107, 0x23},
171 {0x3500, 0x00},
172 {0x3501, 0x80},
173 {0x3502, 0x00},
174 {0x3508, 0x02},
175 {0x3509, 0x00},
176 {0x350a, 0x00},
177 {0x350e, 0x00},
178 {0x3510, 0x00},
179 {0x3511, 0x02},
180 {0x3512, 0x00},
181 {0x3600, 0x2b},
182 {0x3601, 0x52},
183 {0x3602, 0x60},
184 {0x3612, 0x05},
185 {0x3613, 0xa4},
186 {0x3620, 0x80},
187 {0x3621, 0x10},
188 {0x3622, 0x30},
189 {0x3624, 0x1c},
190 {0x3640, 0x10},
191 {0x3661, 0x70},
192 {0x3661, 0x80},
193 {0x3662, 0x12},
194 {0x3664, 0x73},
195 {0x3665, 0xa7},
196 {0x366e, 0xff},
197 {0x366f, 0xf4},
198 {0x3674, 0x00},
199 {0x3679, 0x0c},
200 {0x367f, 0x01},
201 {0x3680, 0x0c},
202 {0x3681, 0x50},
203 {0x3682, 0x50},
204 {0x3683, 0xa9},
205 {0x3684, 0xa9},
206 {0x3709, 0x5f},
207 {0x3714, 0x24},
208 {0x371a, 0x3e},
209 {0x3737, 0x04},
210 {0x3738, 0xcc},
211 {0x3739, 0x12},
212 {0x373d, 0x26},
213 {0x3764, 0x20},
214 {0x3765, 0x20},
215 {0x37a1, 0x36},
216 {0x37a8, 0x3b},
217 {0x37ab, 0x31},
218 {0x37c2, 0x04},
219 {0x37c3, 0xf1},
220 {0x37c5, 0x00},
221 {0x37d8, 0x03},
222 {0x37d9, 0x0c},
223 {0x37da, 0xc2},
224 {0x37dc, 0x02},
225 {0x37e0, 0x00},
226 {0x37e1, 0x0a},
227 {0x37e2, 0x14},
228 {0x37e3, 0x04},
229 {0x37e4, 0x2a},
230 {0x37e5, 0x03},
231 {0x37e6, 0x04},
232 {0x3800, 0x00},
233 {0x3801, 0x00},
234 {0x3802, 0x00},
235 {0x3803, 0x08},
236 {0x3804, 0x10},
237 {0x3805, 0x9f},
238 {0x3806, 0x0c},
239 {0x3807, 0x57},
240 {0x3808, 0x10},
241 {0x3809, 0x80},
242 {0x380a, 0x0c},
243 {0x380b, 0x40},
244 {0x380c, 0x04},
245 {0x380d, 0x62},
246 {0x380e, 0x0c},
247 {0x380f, 0x8e},
248 {0x3811, 0x10},
249 {0x3813, 0x08},
250 {0x3814, 0x01},
251 {0x3815, 0x01},
252 {0x3816, 0x01},
253 {0x3817, 0x01},
254 {0x3820, 0xa8},
255 {0x3821, 0x00},
256 {0x3822, 0xc2},
257 {0x3823, 0x18},
258 {0x3826, 0x11},
259 {0x3827, 0x1c},
260 {0x3829, 0x03},
261 {0x3832, 0x00},
262 {0x3c80, 0x00},
263 {0x3c87, 0x01},
264 {0x3c8c, 0x19},
265 {0x3c8d, 0x1c},
266 {0x3c90, 0x00},
267 {0x3c91, 0x00},
268 {0x3c92, 0x00},
269 {0x3c93, 0x00},
270 {0x3c94, 0x40},
271 {0x3c95, 0x54},
272 {0x3c96, 0x34},
273 {0x3c97, 0x04},
274 {0x3c98, 0x00},
275 {0x3d8c, 0x73},
276 {0x3d8d, 0xc0},
277 {0x3f00, 0x0b},
278 {0x3f03, 0x00},
279 {0x4001, 0xe0},
280 {0x4008, 0x00},
281 {0x4009, 0x0f},
282 {0x4011, 0xf0},
283 {0x4050, 0x04},
284 {0x4051, 0x0b},
285 {0x4052, 0x00},
286 {0x4053, 0x80},
287 {0x4054, 0x00},
288 {0x4055, 0x80},
289 {0x4056, 0x00},
290 {0x4057, 0x80},
291 {0x4058, 0x00},
292 {0x4059, 0x80},
293 {0x405e, 0x00},
294 {0x4500, 0x07},
295 {0x4503, 0x00},
296 {0x450a, 0x04},
297 {0x4809, 0x04},
298 {0x480c, 0x12},
299 {0x481f, 0x30},
300 {0x4833, 0x10},
301 {0x4837, 0x0e},
302 {0x4902, 0x01},
303 {0x4d00, 0x03},
304 {0x4d01, 0xc9},
305 {0x4d02, 0xbc},
306 {0x4d03, 0xd7},
307 {0x4d04, 0xf0},
308 {0x4d05, 0xa2},
309 {0x5000, 0xff},
310 {0x5001, 0x07},
311 {0x5040, 0x39},
312 {0x5041, 0x10},
313 {0x5042, 0x10},
314 {0x5043, 0x84},
315 {0x5044, 0x62},
316 {0x5180, 0x00},
317 {0x5181, 0x10},
318 {0x5182, 0x02},
319 {0x5183, 0x0f},
320 {0x5200, 0x1b},
321 {0x520b, 0x07},
322 {0x520c, 0x0f},
323 {0x5300, 0x04},
324 {0x5301, 0x0C},
325 {0x5302, 0x0C},
326 {0x5303, 0x0f},
327 {0x5304, 0x00},
328 {0x5305, 0x70},
329 {0x5306, 0x00},
330 {0x5307, 0x80},
331 {0x5308, 0x00},
332 {0x5309, 0xa5},
333 {0x530a, 0x00},
334 {0x530b, 0xd3},
335 {0x530c, 0x00},
336 {0x530d, 0xf0},
337 {0x530e, 0x01},
338 {0x530f, 0x10},
339 {0x5310, 0x01},
340 {0x5311, 0x20},
341 {0x5312, 0x01},
342 {0x5313, 0x20},
343 {0x5314, 0x01},
344 {0x5315, 0x20},
345 {0x5316, 0x08},
346 {0x5317, 0x08},
347 {0x5318, 0x10},
348 {0x5319, 0x88},
349 {0x531a, 0x88},
350 {0x531b, 0xa9},
351 {0x531c, 0xaa},
352 {0x531d, 0x0a},
353 {0x5405, 0x02},
354 {0x5406, 0x67},
355 {0x5407, 0x01},
356 {0x5408, 0x4a},
357 {REG_NULL, 0x00},
358 };
359
360 /*
361 * Xclk 24Mhz
362 * max_framerate 30fps
363 * mipi_datarate per lane 540Mbps
364 */
365 static const struct regval ov13855_2112x1568_30fps_regs[] = {
366 {0x0103, 0x01},
367 {0x0300, 0x02},
368 {0x0301, 0x00},
369 {0x0302, 0x5a},
370 {0x0303, 0x01},
371 {0x0304, 0x00},
372 {0x0305, 0x01},
373 {0x3022, 0x01},
374 {0x3013, 0x32},
375 {0x3016, 0x72},
376 {0x301b, 0xF0},
377 {0x301f, 0xd0},
378 {0x3106, 0x15},
379 {0x3107, 0x23},
380 {0x3500, 0x00},
381 {0x3501, 0x40},
382 {0x3502, 0x00},
383 {0x3508, 0x02},
384 {0x3509, 0x00},
385 {0x350a, 0x00},
386 {0x350e, 0x00},
387 {0x3510, 0x00},
388 {0x3511, 0x02},
389 {0x3512, 0x00},
390 {0x3600, 0x2b},
391 {0x3601, 0x52},
392 {0x3602, 0x60},
393 {0x3612, 0x05},
394 {0x3613, 0xa4},
395 {0x3620, 0x80},
396 {0x3621, 0x08},
397 {0x3622, 0x30},
398 {0x3624, 0x1c},
399 {0x3640, 0x08},
400 {0x3641, 0x70},
401 {0x3661, 0x80},
402 {0x3662, 0x10},
403 {0x3664, 0x73},
404 {0x3665, 0xa7},
405 {0x366e, 0xff},
406 {0x366f, 0xf4},
407 {0x3674, 0x00},
408 {0x3679, 0x0c},
409 {0x367f, 0x01},
410 {0x3680, 0x0c},
411 {0x3681, 0x60},
412 {0x3682, 0x17},
413 {0x3683, 0xa9},
414 {0x3684, 0x9a},
415 {0x3709, 0x68},
416 {0x3714, 0x28},
417 {0x371a, 0x3e},
418 {0x3737, 0x08},
419 {0x3738, 0xcc},
420 {0x3739, 0x20},
421 {0x373d, 0x26},
422 {0x3764, 0x20},
423 {0x3765, 0x20},
424 {0x37a1, 0x36},
425 {0x37a8, 0x3b},
426 {0x37ab, 0x31},
427 {0x37c2, 0x14},
428 {0x37c3, 0xf1},
429 {0x37c5, 0x00},
430 {0x37d8, 0x03},
431 {0x37d9, 0x0c},
432 {0x37da, 0xc2},
433 {0x37dc, 0x02},
434 {0x37e0, 0x00},
435 {0x37e1, 0x0a},
436 {0x37e2, 0x14},
437 {0x37e3, 0x08},
438 {0x37e4, 0x38},
439 {0x37e5, 0x03},
440 {0x37e6, 0x08},
441 {0x3800, 0x00},
442 {0x3801, 0x00},
443 {0x3802, 0x00},
444 {0x3803, 0x08},
445 {0x3804, 0x10},
446 {0x3805, 0x9f},
447 {0x3806, 0x0c},
448 {0x3807, 0x4f},
449 {0x3808, 0x08},
450 {0x3809, 0x40},
451 {0x380a, 0x06},
452 {0x380b, 0x20},
453 {0x380c, 0x08},
454 {0x380d, 0xc4},
455 {0x380e, 0x06},
456 {0x380f, 0x48},
457 {0x3811, 0x08},
458 {0x3813, 0x02},
459 {0x3814, 0x03},
460 {0x3815, 0x01},
461 {0x3816, 0x03},
462 {0x3817, 0x01},
463 {0x3820, 0xab},
464 {0x3821, 0x00},
465 {0x3822, 0xc2},
466 {0x3823, 0x18},
467 {0x3826, 0x04},
468 {0x3827, 0x90},
469 {0x3829, 0x07},
470 {0x3832, 0x00},
471 {0x3c80, 0x00},
472 {0x3c87, 0x01},
473 {0x3c8c, 0x19},
474 {0x3c8d, 0x1c},
475 {0x3c90, 0x00},
476 {0x3c91, 0x00},
477 {0x3c92, 0x00},
478 {0x3c93, 0x00},
479 {0x3c94, 0x40},
480 {0x3c95, 0x54},
481 {0x3c96, 0x34},
482 {0x3c97, 0x04},
483 {0x3c98, 0x00},
484 {0x3d8c, 0x73},
485 {0x3d8d, 0xc0},
486 {0x3f00, 0x0b},
487 {0x3f03, 0x00},
488 {0x4001, 0xe0},
489 {0x4008, 0x00},
490 {0x4009, 0x0d},
491 {0x4011, 0xf0},
492 {0x4017, 0x08},
493 {0x4050, 0x04},
494 {0x4051, 0x0b},
495 {0x4052, 0x00},
496 {0x4053, 0x80},
497 {0x4054, 0x00},
498 {0x4055, 0x80},
499 {0x4056, 0x00},
500 {0x4057, 0x80},
501 {0x4058, 0x00},
502 {0x4059, 0x80},
503 {0x405e, 0x20},
504 {0x4500, 0x07},
505 {0x4503, 0x00},
506 {0x450a, 0x04},
507 {0x4809, 0x04},
508 {0x480c, 0x12},
509 {0x481f, 0x30},
510 {0x4833, 0x10},
511 {0x4837, 0x1c},
512 {0x4902, 0x01},
513 {0x4d00, 0x03},
514 {0x4d01, 0xc9},
515 {0x4d02, 0xbc},
516 {0x4d03, 0xd7},
517 {0x4d04, 0xf0},
518 {0x4d05, 0xa2},
519 {0x5000, 0xfd},
520 {0x5001, 0x01},
521 {0x5040, 0x39},
522 {0x5041, 0x10},
523 {0x5042, 0x10},
524 {0x5043, 0x84},
525 {0x5044, 0x62},
526 {0x5180, 0x00},
527 {0x5181, 0x10},
528 {0x5182, 0x02},
529 {0x5183, 0x0f},
530 {0x5200, 0x1b},
531 {0x520b, 0x07},
532 {0x520c, 0x0f},
533 {0x5300, 0x04},
534 {0x5301, 0x0C},
535 {0x5302, 0x0C},
536 {0x5303, 0x0f},
537 {0x5304, 0x00},
538 {0x5305, 0x70},
539 {0x5306, 0x00},
540 {0x5307, 0x80},
541 {0x5308, 0x00},
542 {0x5309, 0xa5},
543 {0x530a, 0x00},
544 {0x530b, 0xd3},
545 {0x530c, 0x00},
546 {0x530d, 0xf0},
547 {0x530e, 0x01},
548 {0x530f, 0x10},
549 {0x5310, 0x01},
550 {0x5311, 0x20},
551 {0x5312, 0x01},
552 {0x5313, 0x20},
553 {0x5314, 0x01},
554 {0x5315, 0x20},
555 {0x5316, 0x08},
556 {0x5317, 0x08},
557 {0x5318, 0x10},
558 {0x5319, 0x88},
559 {0x531a, 0x88},
560 {0x531b, 0xa9},
561 {0x531c, 0xaa},
562 {0x531d, 0x0a},
563 {0x5405, 0x02},
564 {0x5406, 0x67},
565 {0x5407, 0x01},
566 {0x5408, 0x4a},
567 {0x0100, 0x01},
568 {REG_NULL, 0x00},
569 };
570
571 /*
572 * Xclk 24Mhz
573 * max_framerate 30fps
574 * mipi_datarate per lane 1080Mbps
575 */
576 static const struct regval ov13855_4224x3136_30fps_regs[] = {
577 {0x0103, 0x01},
578 {0x0300, 0x02},
579 {0x0301, 0x00},
580 {0x0302, 0x5a},
581 {0x0303, 0x00},
582 {0x0304, 0x00},
583 {0x0305, 0x01},
584 {0x030b, 0x06},
585 {0x030c, 0x02},
586 {0x030d, 0x88},
587 {0x0312, 0x11},
588 {0x3022, 0x01},
589 {0x3012, 0x40},
590 {0x3013, 0x72},
591 {0x3016, 0x72},
592 {0x301b, 0xF0},
593 {0x301f, 0xd0},
594 {0x3106, 0x15},
595 {0x3107, 0x23},
596 {0x3500, 0x00},
597 {0x3501, 0x80},
598 {0x3502, 0x00},
599 {0x3508, 0x02},
600 {0x3509, 0x00},
601 {0x350a, 0x00},
602 {0x350e, 0x00},
603 {0x3510, 0x00},
604 {0x3511, 0x02},
605 {0x3512, 0x00},
606 {0x3600, 0x2b},
607 {0x3601, 0x52},
608 {0x3602, 0x60},
609 {0x3612, 0x05},
610 {0x3613, 0xa4},
611 {0x3620, 0x80},
612 {0x3621, 0x10},
613 {0x3622, 0x30},
614 {0x3624, 0x1c},
615 {0x3640, 0x10},
616 {0x3641, 0x70},
617 {0x3660, 0x04},
618 {0x3661, 0x80},
619 {0x3662, 0x12},
620 {0x3664, 0x73},
621 {0x3665, 0xa7},
622 {0x366e, 0xff},
623 {0x366f, 0xf4},
624 {0x3674, 0x00},
625 {0x3679, 0x0c},
626 {0x367f, 0x01},
627 {0x3680, 0x0c},
628 {0x3681, 0x50},
629 {0x3682, 0x50},
630 {0x3683, 0xa9},
631 {0x3684, 0xa9},
632 {0x3706, 0x40},
633 {0x3709, 0x5f},
634 {0x3714, 0x24},
635 {0x371a, 0x3e},
636 {0x3737, 0x04},
637 {0x3738, 0xcc},
638 {0x3739, 0x12},
639 {0x373d, 0x26},
640 {0x3764, 0x20},
641 {0x3765, 0x20},
642 {0x37a1, 0x36},
643 {0x37a8, 0x3b},
644 {0x37ab, 0x31},
645 {0x37c2, 0x04},
646 {0x37c3, 0xf1},
647 {0x37c5, 0x00},
648 {0x37d8, 0x03},
649 {0x37d9, 0x0c},
650 {0x37da, 0xc2},
651 {0x37dc, 0x02},
652 {0x37e0, 0x00},
653 {0x37e1, 0x0a},
654 {0x37e2, 0x14},
655 {0x37e3, 0x04},
656 {0x37e4, 0x2A},
657 {0x37e5, 0x03},
658 {0x37e6, 0x04},
659 {0x3800, 0x00},
660 {0x3801, 0x00},
661 {0x3802, 0x00},
662 {0x3803, 0x08},
663 {0x3804, 0x10},
664 {0x3805, 0x9f},
665 {0x3806, 0x0c},
666 {0x3807, 0x57},
667 {0x3808, 0x10},
668 {0x3809, 0x80},
669 {0x380a, 0x0c},
670 {0x380b, 0x40},
671 {0x380c, 0x04},
672 {0x380d, 0x62},
673 {0x380e, 0x0c},
674 {0x380f, 0x8e},
675 {0x3811, 0x10},
676 {0x3813, 0x08},
677 {0x3814, 0x01},
678 {0x3815, 0x01},
679 {0x3816, 0x01},
680 {0x3817, 0x01},
681 {0x3820, 0xa8},
682 {0x3821, 0x00},
683 {0x3822, 0xd2},
684 {0x3823, 0x18},
685 {0x3826, 0x11},
686 {0x3827, 0x1c},
687 {0x3829, 0x03},
688 {0x3832, 0x00},
689 {0x3c80, 0x00},
690 {0x3c87, 0x01},
691 {0x3c8c, 0x19},
692 {0x3c8d, 0x1c},
693 {0x3c90, 0x00},
694 {0x3c91, 0x00},
695 {0x3c92, 0x00},
696 {0x3c93, 0x00},
697 {0x3c94, 0x40},
698 {0x3c95, 0x54},
699 {0x3c96, 0x34},
700 {0x3c97, 0x04},
701 {0x3c98, 0x00},
702 {0x3d8c, 0x73},
703 {0x3d8d, 0xc0},
704 {0x3f00, 0x0b},
705 {0x3f03, 0x00},
706 {0x4001, 0xe0},
707 {0x4008, 0x00},
708 {0x4009, 0x0f},
709 {0x4011, 0xf0},
710 {0x4017, 0x08},
711 {0x4050, 0x04},
712 {0x4051, 0x0b},
713 {0x4052, 0x00},
714 {0x4053, 0x80},
715 {0x4054, 0x00},
716 {0x4055, 0x80},
717 {0x4056, 0x00},
718 {0x4057, 0x80},
719 {0x4058, 0x00},
720 {0x4059, 0x80},
721 {0x405e, 0x00},
722 {0x4500, 0x07},
723 {0x4503, 0x00},
724 {0x450a, 0x04},
725 {0x4800, 0x60},
726 {0x4809, 0x04},
727 {0x480c, 0x12},
728 {0x481f, 0x30},
729 {0x4833, 0x10},
730 {0x4837, 0x0e},
731 {0x4902, 0x01},
732 {0x4d00, 0x03},
733 {0x4d01, 0xc9},
734 {0x4d02, 0xbc},
735 {0x4d03, 0xd7},
736 {0x4d04, 0xf0},
737 {0x4d05, 0xa2},
738 {0x5000, 0xff},
739 {0x5001, 0x07},
740 {0x5040, 0x39},
741 {0x5041, 0x10},
742 {0x5042, 0x10},
743 {0x5043, 0x84},
744 {0x5044, 0x62},
745 {0x5180, 0x00},
746 {0x5181, 0x10},
747 {0x5182, 0x02},
748 {0x5183, 0x0f},
749 {0x5200, 0x1b},
750 {0x520b, 0x07},
751 {0x520c, 0x0f},
752 {0x5300, 0x04},
753 {0x5301, 0x0C},
754 {0x5302, 0x0C},
755 {0x5303, 0x0f},
756 {0x5304, 0x00},
757 {0x5305, 0x70},
758 {0x5306, 0x00},
759 {0x5307, 0x80},
760 {0x5308, 0x00},
761 {0x5309, 0xa5},
762 {0x530a, 0x00},
763 {0x530b, 0xd3},
764 {0x530c, 0x00},
765 {0x530d, 0xf0},
766 {0x530e, 0x01},
767 {0x530f, 0x10},
768 {0x5310, 0x01},
769 {0x5311, 0x20},
770 {0x5312, 0x01},
771 {0x5313, 0x20},
772 {0x5314, 0x01},
773 {0x5315, 0x20},
774 {0x5316, 0x08},
775 {0x5317, 0x08},
776 {0x5318, 0x10},
777 {0x5319, 0x88},
778 {0x531a, 0x88},
779 {0x531b, 0xa9},
780 {0x531c, 0xaa},
781 {0x531d, 0x0a},
782 {0x5405, 0x02},
783 {0x5406, 0x67},
784 {0x5407, 0x01},
785 {0x5408, 0x4a},
786 {0x0100, 0x01},
787 {0x0100, 0x00},
788 {0x380c, 0x04},
789 {0x380d, 0x62},
790 {0x0303, 0x00},
791 {0x4837, 0x0e},
792 {0x0100, 0x01},
793 {REG_NULL, 0x00},
794 };
795
796 /*
797 * Xclk 24Mhz
798 * max_framerate 15fps
799 * mipi_datarate per lane 1080Mbps
800 */
801 static const struct regval ov13855_4224x3136_15fps_regs[] = {
802 {0x0103, 0x01},
803 {0x0300, 0x02},
804 {0x0301, 0x00},
805 {0x0302, 0x5a},
806 {0x0303, 0x00},
807 {0x0304, 0x00},
808 {0x0305, 0x01},
809 {0x030b, 0x06},
810 {0x030c, 0x02},
811 {0x030d, 0x88},
812 {0x0312, 0x11},
813 {0x3022, 0x01},
814 {0x3012, 0x40},
815 {0x3013, 0x72},
816 {0x3016, 0x72},
817 {0x301b, 0xF0},
818 {0x301f, 0xd0},
819 {0x3106, 0x15},
820 {0x3107, 0x23},
821 {0x3500, 0x00},
822 {0x3501, 0x80},
823 {0x3502, 0x00},
824 {0x3508, 0x02},
825 {0x3509, 0x00},
826 {0x350a, 0x00},
827 {0x350e, 0x00},
828 {0x3510, 0x00},
829 {0x3511, 0x02},
830 {0x3512, 0x00},
831 {0x3600, 0x2b},
832 {0x3601, 0x52},
833 {0x3602, 0x60},
834 {0x3612, 0x05},
835 {0x3613, 0xa4},
836 {0x3620, 0x80},
837 {0x3621, 0x10},
838 {0x3622, 0x30},
839 {0x3624, 0x1c},
840 {0x3640, 0x10},
841 {0x3641, 0x70},
842 {0x3660, 0x04},
843 {0x3661, 0x80},
844 {0x3662, 0x12},
845 {0x3664, 0x73},
846 {0x3665, 0xa7},
847 {0x366e, 0xff},
848 {0x366f, 0xf4},
849 {0x3674, 0x00},
850 {0x3679, 0x0c},
851 {0x367f, 0x01},
852 {0x3680, 0x0c},
853 {0x3681, 0x50},
854 {0x3682, 0x50},
855 {0x3683, 0xa9},
856 {0x3684, 0xa9},
857 {0x3706, 0x40},
858 {0x3709, 0x5f},
859 {0x3714, 0x24},
860 {0x371a, 0x3e},
861 {0x3737, 0x04},
862 {0x3738, 0xcc},
863 {0x3739, 0x12},
864 {0x373d, 0x26},
865 {0x3764, 0x20},
866 {0x3765, 0x20},
867 {0x37a1, 0x36},
868 {0x37a8, 0x3b},
869 {0x37ab, 0x31},
870 {0x37c2, 0x04},
871 {0x37c3, 0xf1},
872 {0x37c5, 0x00},
873 {0x37d8, 0x03},
874 {0x37d9, 0x0c},
875 {0x37da, 0xc2},
876 {0x37dc, 0x02},
877 {0x37e0, 0x00},
878 {0x37e1, 0x0a},
879 {0x37e2, 0x14},
880 {0x37e3, 0x04},
881 {0x37e4, 0x2A},
882 {0x37e5, 0x03},
883 {0x37e6, 0x04},
884 {0x3800, 0x00},
885 {0x3801, 0x00},
886 {0x3802, 0x00},
887 {0x3803, 0x08},
888 {0x3804, 0x10},
889 {0x3805, 0x9f},
890 {0x3806, 0x0c},
891 {0x3807, 0x57},
892 {0x3808, 0x10},
893 {0x3809, 0x80},
894 {0x380a, 0x0c},
895 {0x380b, 0x40},
896 {0x380c, 0x04},
897 {0x380d, 0x62},
898 {0x380e, 0x0c},
899 {0x380f, 0x8e},
900 {0x3811, 0x10},
901 {0x3813, 0x08},
902 {0x3814, 0x01},
903 {0x3815, 0x01},
904 {0x3816, 0x01},
905 {0x3817, 0x01},
906 {0x3820, 0xa8},
907 {0x3821, 0x00},
908 {0x3822, 0xd2},
909 {0x3823, 0x18},
910 {0x3826, 0x11},
911 {0x3827, 0x1c},
912 {0x3829, 0x03},
913 {0x3832, 0x00},
914 {0x3c80, 0x00},
915 {0x3c87, 0x01},
916 {0x3c8c, 0x19},
917 {0x3c8d, 0x1c},
918 {0x3c90, 0x00},
919 {0x3c91, 0x00},
920 {0x3c92, 0x00},
921 {0x3c93, 0x00},
922 {0x3c94, 0x40},
923 {0x3c95, 0x54},
924 {0x3c96, 0x34},
925 {0x3c97, 0x04},
926 {0x3c98, 0x00},
927 {0x3d8c, 0x73},
928 {0x3d8d, 0xc0},
929 {0x3f00, 0x0b},
930 {0x3f03, 0x00},
931 {0x4001, 0xe0},
932 {0x4008, 0x00},
933 {0x4009, 0x0f},
934 {0x4011, 0xf0},
935 {0x4017, 0x08},
936 {0x4050, 0x04},
937 {0x4051, 0x0b},
938 {0x4052, 0x00},
939 {0x4053, 0x80},
940 {0x4054, 0x00},
941 {0x4055, 0x80},
942 {0x4056, 0x00},
943 {0x4057, 0x80},
944 {0x4058, 0x00},
945 {0x4059, 0x80},
946 {0x405e, 0x00},
947 {0x4500, 0x07},
948 {0x4503, 0x00},
949 {0x450a, 0x04},
950 {0x4800, 0x60},
951 {0x4809, 0x04},
952 {0x480c, 0x12},
953 {0x481f, 0x30},
954 {0x4833, 0x10},
955 {0x4837, 0x0e},
956 {0x4902, 0x01},
957 {0x4d00, 0x03},
958 {0x4d01, 0xc9},
959 {0x4d02, 0xbc},
960 {0x4d03, 0xd7},
961 {0x4d04, 0xf0},
962 {0x4d05, 0xa2},
963 {0x5000, 0xff},
964 {0x5001, 0x07},
965 {0x5040, 0x39},
966 {0x5041, 0x10},
967 {0x5042, 0x10},
968 {0x5043, 0x84},
969 {0x5044, 0x62},
970 {0x5180, 0x00},
971 {0x5181, 0x10},
972 {0x5182, 0x02},
973 {0x5183, 0x0f},
974 {0x5200, 0x1b},
975 {0x520b, 0x07},
976 {0x520c, 0x0f},
977 {0x5300, 0x04},
978 {0x5301, 0x0C},
979 {0x5302, 0x0C},
980 {0x5303, 0x0f},
981 {0x5304, 0x00},
982 {0x5305, 0x70},
983 {0x5306, 0x00},
984 {0x5307, 0x80},
985 {0x5308, 0x00},
986 {0x5309, 0xa5},
987 {0x530a, 0x00},
988 {0x530b, 0xd3},
989 {0x530c, 0x00},
990 {0x530d, 0xf0},
991 {0x530e, 0x01},
992 {0x530f, 0x10},
993 {0x5310, 0x01},
994 {0x5311, 0x20},
995 {0x5312, 0x01},
996 {0x5313, 0x20},
997 {0x5314, 0x01},
998 {0x5315, 0x20},
999 {0x5316, 0x08},
1000 {0x5317, 0x08},
1001 {0x5318, 0x10},
1002 {0x5319, 0x88},
1003 {0x531a, 0x88},
1004 {0x531b, 0xa9},
1005 {0x531c, 0xaa},
1006 {0x531d, 0x0a},
1007 {0x5405, 0x02},
1008 {0x5406, 0x67},
1009 {0x5407, 0x01},
1010 {0x5408, 0x4a},
1011 {0x0100, 0x01},
1012 {0x0100, 0x00},
1013 {0x380c, 0x08},
1014 {0x380d, 0xC4},
1015 {0x0303, 0x01},
1016 {0x4837, 0x1c},
1017 {0x0100, 0x01},
1018 {REG_NULL, 0x00},
1019 };
1020
1021 static const struct ov13855_mode supported_modes[] = {
1022 {
1023 .width = 4224,
1024 .height = 3136,
1025 .max_fps = {
1026 .numerator = 10000,
1027 .denominator = 300000,
1028 },
1029 .exp_def = 0x0c8a,
1030 .hts_def = 0x0462,
1031 .vts_def = 0x0c8e,
1032 .bpp = 10,
1033 .reg_list = ov13855_4224x3136_30fps_regs,
1034 .link_freq_idx = 0,
1035 },
1036 {
1037 .width = 4224,
1038 .height = 3136,
1039 .max_fps = {
1040 .numerator = 10000,
1041 .denominator = 150000,
1042 },
1043 .exp_def = 0x0c8a,
1044 .hts_def = 0x0462,
1045 .vts_def = 0x0c8e,
1046 .bpp = 10,
1047 .reg_list = ov13855_4224x3136_15fps_regs,
1048 .link_freq_idx = 0,
1049 },
1050 {
1051 .width = 2112,
1052 .height = 1568,
1053 .max_fps = {
1054 .numerator = 10000,
1055 .denominator = 300000,
1056 },
1057 .exp_def = 0x0644,
1058 .hts_def = 0x08c4,
1059 .vts_def = 0x0648,
1060 .bpp = 10,
1061 .reg_list = ov13855_2112x1568_30fps_regs,
1062 .link_freq_idx = 1,
1063 },
1064 };
1065
1066 static const s64 link_freq_items[] = {
1067 OV13855_LINK_FREQ_540MHZ,
1068 OV13855_LINK_FREQ_270MHZ,
1069 };
1070
1071 static const char * const ov13855_test_pattern_menu[] = {
1072 "Disabled",
1073 "Vertical Color Bar Type 1",
1074 "Vertical Color Bar Type 2",
1075 "Vertical Color Bar Type 3",
1076 "Vertical Color Bar Type 4"
1077 };
1078
1079 /* Write registers up to 4 at a time */
ov13855_write_reg(struct i2c_client *client, u16 reg, u32 len, u32 val)1080 static int ov13855_write_reg(struct i2c_client *client, u16 reg,
1081 u32 len, u32 val)
1082 {
1083 u32 buf_i, val_i;
1084 u8 buf[6];
1085 u8 *val_p;
1086 __be32 val_be;
1087
1088 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
1089
1090 if (len > 4)
1091 return -EINVAL;
1092
1093 buf[0] = reg >> 8;
1094 buf[1] = reg & 0xff;
1095
1096 val_be = cpu_to_be32(val);
1097 val_p = (u8 *)&val_be;
1098 buf_i = 2;
1099 val_i = 4 - len;
1100
1101 while (val_i < 4)
1102 buf[buf_i++] = val_p[val_i++];
1103
1104 if (i2c_master_send(client, buf, len + 2) != len + 2)
1105 return -EIO;
1106
1107 return 0;
1108 }
1109
ov13855_write_array(struct i2c_client *client, const struct regval *regs)1110 static int ov13855_write_array(struct i2c_client *client,
1111 const struct regval *regs)
1112 {
1113 u32 i;
1114 int ret = 0;
1115
1116 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
1117 ret = ov13855_write_reg(client, regs[i].addr,
1118 OV13855_REG_VALUE_08BIT,
1119 regs[i].val);
1120
1121 return ret;
1122 }
1123
1124 /* Read registers up to 4 at a time */
ov13855_read_reg(struct i2c_client *client, u16 reg, unsigned int len, u32 *val)1125 static int ov13855_read_reg(struct i2c_client *client, u16 reg,
1126 unsigned int len, u32 *val)
1127 {
1128 struct i2c_msg msgs[2];
1129 u8 *data_be_p;
1130 __be32 data_be = 0;
1131 __be16 reg_addr_be = cpu_to_be16(reg);
1132 int ret;
1133
1134 if (len > 4 || !len)
1135 return -EINVAL;
1136
1137 data_be_p = (u8 *)&data_be;
1138 /* Write register address */
1139 msgs[0].addr = client->addr;
1140 msgs[0].flags = 0;
1141 msgs[0].len = 2;
1142 msgs[0].buf = (u8 *)®_addr_be;
1143
1144 /* Read data from register */
1145 msgs[1].addr = client->addr;
1146 msgs[1].flags = I2C_M_RD;
1147 msgs[1].len = len;
1148 msgs[1].buf = &data_be_p[4 - len];
1149
1150 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1151 if (ret != ARRAY_SIZE(msgs))
1152 return -EIO;
1153
1154 *val = be32_to_cpu(data_be);
1155
1156 return 0;
1157 }
1158
ov13855_get_reso_dist(const struct ov13855_mode *mode, struct v4l2_mbus_framefmt *framefmt)1159 static int ov13855_get_reso_dist(const struct ov13855_mode *mode,
1160 struct v4l2_mbus_framefmt *framefmt)
1161 {
1162 return abs(mode->width - framefmt->width) +
1163 abs(mode->height - framefmt->height);
1164 }
1165
1166 static const struct ov13855_mode *
ov13855_find_best_fit(struct v4l2_subdev_format *fmt)1167 ov13855_find_best_fit(struct v4l2_subdev_format *fmt)
1168 {
1169 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1170 int dist;
1171 int cur_best_fit = 0;
1172 int cur_best_fit_dist = -1;
1173 unsigned int i;
1174
1175 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1176 dist = ov13855_get_reso_dist(&supported_modes[i], framefmt);
1177 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1178 cur_best_fit_dist = dist;
1179 cur_best_fit = i;
1180 }
1181 }
1182
1183 return &supported_modes[cur_best_fit];
1184 }
1185
ov13855_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_format *fmt)1186 static int ov13855_set_fmt(struct v4l2_subdev *sd,
1187 struct v4l2_subdev_pad_config *cfg,
1188 struct v4l2_subdev_format *fmt)
1189 {
1190 struct ov13855 *ov13855 = to_ov13855(sd);
1191 const struct ov13855_mode *mode;
1192 s64 h_blank, vblank_def;
1193 u64 pixel_rate = 0;
1194 u32 lane_num = OV13855_LANES;
1195
1196 mutex_lock(&ov13855->mutex);
1197
1198 mode = ov13855_find_best_fit(fmt);
1199 fmt->format.code = OV13855_MEDIA_BUS_FMT;
1200 fmt->format.width = mode->width;
1201 fmt->format.height = mode->height;
1202 fmt->format.field = V4L2_FIELD_NONE;
1203 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1204 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1205 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1206 #else
1207 mutex_unlock(&ov13855->mutex);
1208 return -ENOTTY;
1209 #endif
1210 } else {
1211 ov13855->cur_mode = mode;
1212 h_blank = mode->hts_def - mode->width;
1213 __v4l2_ctrl_modify_range(ov13855->hblank, h_blank,
1214 h_blank, 1, h_blank);
1215 vblank_def = mode->vts_def - mode->height;
1216 __v4l2_ctrl_modify_range(ov13855->vblank, vblank_def,
1217 OV13855_VTS_MAX - mode->height,
1218 1, vblank_def);
1219 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1220
1221 __v4l2_ctrl_s_ctrl_int64(ov13855->pixel_rate,
1222 pixel_rate);
1223 __v4l2_ctrl_s_ctrl(ov13855->link_freq,
1224 mode->link_freq_idx);
1225 }
1226
1227 mutex_unlock(&ov13855->mutex);
1228
1229 return 0;
1230 }
1231
ov13855_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_format *fmt)1232 static int ov13855_get_fmt(struct v4l2_subdev *sd,
1233 struct v4l2_subdev_pad_config *cfg,
1234 struct v4l2_subdev_format *fmt)
1235 {
1236 struct ov13855 *ov13855 = to_ov13855(sd);
1237 const struct ov13855_mode *mode = ov13855->cur_mode;
1238
1239 mutex_lock(&ov13855->mutex);
1240 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1241 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1242 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1243 #else
1244 mutex_unlock(&ov13855->mutex);
1245 return -ENOTTY;
1246 #endif
1247 } else {
1248 fmt->format.width = mode->width;
1249 fmt->format.height = mode->height;
1250 fmt->format.code = OV13855_MEDIA_BUS_FMT;
1251 fmt->format.field = V4L2_FIELD_NONE;
1252 }
1253 mutex_unlock(&ov13855->mutex);
1254
1255 return 0;
1256 }
1257
ov13855_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_mbus_code_enum *code)1258 static int ov13855_enum_mbus_code(struct v4l2_subdev *sd,
1259 struct v4l2_subdev_pad_config *cfg,
1260 struct v4l2_subdev_mbus_code_enum *code)
1261 {
1262 if (code->index != 0)
1263 return -EINVAL;
1264 code->code = OV13855_MEDIA_BUS_FMT;
1265
1266 return 0;
1267 }
1268
ov13855_enum_frame_sizes(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_frame_size_enum *fse)1269 static int ov13855_enum_frame_sizes(struct v4l2_subdev *sd,
1270 struct v4l2_subdev_pad_config *cfg,
1271 struct v4l2_subdev_frame_size_enum *fse)
1272 {
1273 if (fse->index >= ARRAY_SIZE(supported_modes))
1274 return -EINVAL;
1275
1276 if (fse->code != OV13855_MEDIA_BUS_FMT)
1277 return -EINVAL;
1278
1279 fse->min_width = supported_modes[fse->index].width;
1280 fse->max_width = supported_modes[fse->index].width;
1281 fse->max_height = supported_modes[fse->index].height;
1282 fse->min_height = supported_modes[fse->index].height;
1283
1284 return 0;
1285 }
1286
ov13855_enable_test_pattern(struct ov13855 *ov13855, u32 pattern)1287 static int ov13855_enable_test_pattern(struct ov13855 *ov13855, u32 pattern)
1288 {
1289 u32 val;
1290
1291 if (pattern)
1292 val = (pattern - 1) | OV13855_TEST_PATTERN_ENABLE;
1293 else
1294 val = OV13855_TEST_PATTERN_DISABLE;
1295
1296 return ov13855_write_reg(ov13855->client,
1297 OV13855_REG_TEST_PATTERN,
1298 OV13855_REG_VALUE_08BIT,
1299 val);
1300 }
1301
ov13855_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *fi)1302 static int ov13855_g_frame_interval(struct v4l2_subdev *sd,
1303 struct v4l2_subdev_frame_interval *fi)
1304 {
1305 struct ov13855 *ov13855 = to_ov13855(sd);
1306 const struct ov13855_mode *mode = ov13855->cur_mode;
1307
1308 mutex_lock(&ov13855->mutex);
1309 fi->interval = mode->max_fps;
1310 mutex_unlock(&ov13855->mutex);
1311
1312 return 0;
1313 }
1314
ov13855_get_module_inf(struct ov13855 *ov13855, struct rkmodule_inf *inf)1315 static void ov13855_get_module_inf(struct ov13855 *ov13855,
1316 struct rkmodule_inf *inf)
1317 {
1318 memset(inf, 0, sizeof(*inf));
1319 strscpy(inf->base.sensor, OV13855_NAME, sizeof(inf->base.sensor));
1320 strscpy(inf->base.module, ov13855->module_name,
1321 sizeof(inf->base.module));
1322 strscpy(inf->base.lens, ov13855->len_name, sizeof(inf->base.lens));
1323 }
1324
ov13855_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)1325 static long ov13855_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1326 {
1327 struct ov13855 *ov13855 = to_ov13855(sd);
1328 long ret = 0;
1329 u32 stream = 0;
1330
1331 switch (cmd) {
1332 case RKMODULE_GET_MODULE_INFO:
1333 ov13855_get_module_inf(ov13855, (struct rkmodule_inf *)arg);
1334 break;
1335 case RKMODULE_SET_QUICK_STREAM:
1336
1337 stream = *((u32 *)arg);
1338
1339 if (stream)
1340 ret = ov13855_write_reg(ov13855->client,
1341 OV13855_REG_CTRL_MODE,
1342 OV13855_REG_VALUE_08BIT,
1343 OV13855_MODE_STREAMING);
1344 else
1345 ret = ov13855_write_reg(ov13855->client,
1346 OV13855_REG_CTRL_MODE,
1347 OV13855_REG_VALUE_08BIT,
1348 OV13855_MODE_SW_STANDBY);
1349 break;
1350 default:
1351 ret = -ENOIOCTLCMD;
1352 break;
1353 }
1354
1355 return ret;
1356 }
1357
1358 #ifdef CONFIG_COMPAT
ov13855_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, unsigned long arg)1359 static long ov13855_compat_ioctl32(struct v4l2_subdev *sd,
1360 unsigned int cmd, unsigned long arg)
1361 {
1362 void __user *up = compat_ptr(arg);
1363 struct rkmodule_inf *inf;
1364 struct rkmodule_awb_cfg *cfg;
1365 long ret = 0;
1366 u32 stream = 0;
1367
1368 switch (cmd) {
1369 case RKMODULE_GET_MODULE_INFO:
1370 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1371 if (!inf) {
1372 ret = -ENOMEM;
1373 return ret;
1374 }
1375
1376 ret = ov13855_ioctl(sd, cmd, inf);
1377 if (!ret) {
1378 ret = copy_to_user(up, inf, sizeof(*inf));
1379 if (ret)
1380 ret = -EFAULT;
1381 }
1382 kfree(inf);
1383 break;
1384 case RKMODULE_AWB_CFG:
1385 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1386 if (!cfg) {
1387 ret = -ENOMEM;
1388 return ret;
1389 }
1390
1391 ret = copy_from_user(cfg, up, sizeof(*cfg));
1392 if (!ret)
1393 ret = ov13855_ioctl(sd, cmd, cfg);
1394 else
1395 ret = -EFAULT;
1396 kfree(cfg);
1397 break;
1398 case RKMODULE_SET_QUICK_STREAM:
1399 ret = copy_from_user(&stream, up, sizeof(u32));
1400 if (!ret)
1401 ret = ov13855_ioctl(sd, cmd, &stream);
1402 else
1403 ret = -EFAULT;
1404 break;
1405 default:
1406 ret = -ENOIOCTLCMD;
1407 break;
1408 }
1409
1410 return ret;
1411 }
1412 #endif
1413
__ov13855_start_stream(struct ov13855 *ov13855)1414 static int __ov13855_start_stream(struct ov13855 *ov13855)
1415 {
1416 int ret;
1417
1418 ret = ov13855_write_array(ov13855->client, ov13855->cur_mode->reg_list);
1419 if (ret)
1420 return ret;
1421
1422 /* In case these controls are set before streaming */
1423 mutex_unlock(&ov13855->mutex);
1424 ret = v4l2_ctrl_handler_setup(&ov13855->ctrl_handler);
1425 mutex_lock(&ov13855->mutex);
1426 if (ret)
1427 return ret;
1428
1429 return ov13855_write_reg(ov13855->client,
1430 OV13855_REG_CTRL_MODE,
1431 OV13855_REG_VALUE_08BIT,
1432 OV13855_MODE_STREAMING);
1433 }
1434
__ov13855_stop_stream(struct ov13855 *ov13855)1435 static int __ov13855_stop_stream(struct ov13855 *ov13855)
1436 {
1437 return ov13855_write_reg(ov13855->client,
1438 OV13855_REG_CTRL_MODE,
1439 OV13855_REG_VALUE_08BIT,
1440 OV13855_MODE_SW_STANDBY);
1441 }
1442
ov13855_s_stream(struct v4l2_subdev *sd, int on)1443 static int ov13855_s_stream(struct v4l2_subdev *sd, int on)
1444 {
1445 struct ov13855 *ov13855 = to_ov13855(sd);
1446 struct i2c_client *client = ov13855->client;
1447 int ret = 0;
1448
1449 mutex_lock(&ov13855->mutex);
1450 on = !!on;
1451 if (on == ov13855->streaming)
1452 goto unlock_and_return;
1453
1454 if (on) {
1455 ret = pm_runtime_get_sync(&client->dev);
1456 if (ret < 0) {
1457 pm_runtime_put_noidle(&client->dev);
1458 goto unlock_and_return;
1459 }
1460
1461 ret = __ov13855_start_stream(ov13855);
1462 if (ret) {
1463 v4l2_err(sd, "start stream failed while write regs\n");
1464 pm_runtime_put(&client->dev);
1465 goto unlock_and_return;
1466 }
1467 } else {
1468 __ov13855_stop_stream(ov13855);
1469 pm_runtime_put(&client->dev);
1470 }
1471
1472 ov13855->streaming = on;
1473
1474 unlock_and_return:
1475 mutex_unlock(&ov13855->mutex);
1476
1477 return ret;
1478 }
1479
ov13855_s_power(struct v4l2_subdev *sd, int on)1480 static int ov13855_s_power(struct v4l2_subdev *sd, int on)
1481 {
1482 struct ov13855 *ov13855 = to_ov13855(sd);
1483 struct i2c_client *client = ov13855->client;
1484 int ret = 0;
1485
1486 mutex_lock(&ov13855->mutex);
1487
1488 /* If the power state is not modified - no work to do. */
1489 if (ov13855->power_on == !!on)
1490 goto unlock_and_return;
1491
1492 if (on) {
1493 ret = pm_runtime_get_sync(&client->dev);
1494 if (ret < 0) {
1495 pm_runtime_put_noidle(&client->dev);
1496 goto unlock_and_return;
1497 }
1498
1499 ret = ov13855_write_array(ov13855->client, ov13855_global_regs);
1500 if (ret) {
1501 v4l2_err(sd, "could not set init registers\n");
1502 pm_runtime_put_noidle(&client->dev);
1503 goto unlock_and_return;
1504 }
1505
1506 ov13855->power_on = true;
1507 } else {
1508 pm_runtime_put(&client->dev);
1509 ov13855->power_on = false;
1510 }
1511
1512 unlock_and_return:
1513 mutex_unlock(&ov13855->mutex);
1514
1515 return ret;
1516 }
1517
1518 /* Calculate the delay in us by clock rate and clock cycles */
ov13855_cal_delay(u32 cycles)1519 static inline u32 ov13855_cal_delay(u32 cycles)
1520 {
1521 return DIV_ROUND_UP(cycles, OV13855_XVCLK_FREQ / 1000 / 1000);
1522 }
1523
__ov13855_power_on(struct ov13855 *ov13855)1524 static int __ov13855_power_on(struct ov13855 *ov13855)
1525 {
1526 int ret;
1527 u32 delay_us;
1528 struct device *dev = &ov13855->client->dev;
1529
1530 if (!IS_ERR(ov13855->power_gpio))
1531 gpiod_set_value_cansleep(ov13855->power_gpio, 1);
1532
1533 usleep_range(1000, 2000);
1534
1535 if (!IS_ERR_OR_NULL(ov13855->pins_default)) {
1536 ret = pinctrl_select_state(ov13855->pinctrl,
1537 ov13855->pins_default);
1538 if (ret < 0)
1539 dev_err(dev, "could not set pins\n");
1540 }
1541 ret = clk_set_rate(ov13855->xvclk, OV13855_XVCLK_FREQ);
1542 if (ret < 0)
1543 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1544 if (clk_get_rate(ov13855->xvclk) != OV13855_XVCLK_FREQ)
1545 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1546 ret = clk_prepare_enable(ov13855->xvclk);
1547 if (ret < 0) {
1548 dev_err(dev, "Failed to enable xvclk\n");
1549 return ret;
1550 }
1551 if (!IS_ERR(ov13855->reset_gpio))
1552 gpiod_set_value_cansleep(ov13855->reset_gpio, 0);
1553
1554 ret = regulator_bulk_enable(OV13855_NUM_SUPPLIES, ov13855->supplies);
1555 if (ret < 0) {
1556 dev_err(dev, "Failed to enable regulators\n");
1557 goto disable_clk;
1558 }
1559
1560 if (!IS_ERR(ov13855->reset_gpio))
1561 gpiod_set_value_cansleep(ov13855->reset_gpio, 1);
1562
1563 usleep_range(500, 1000);
1564 if (!IS_ERR(ov13855->pwdn_gpio))
1565 gpiod_set_value_cansleep(ov13855->pwdn_gpio, 1);
1566
1567 /* 8192 cycles prior to first SCCB transaction */
1568 delay_us = ov13855_cal_delay(8192);
1569 usleep_range(delay_us, delay_us * 2);
1570
1571 return 0;
1572
1573 disable_clk:
1574 clk_disable_unprepare(ov13855->xvclk);
1575
1576 return ret;
1577 }
1578
__ov13855_power_off(struct ov13855 *ov13855)1579 static void __ov13855_power_off(struct ov13855 *ov13855)
1580 {
1581 int ret;
1582 struct device *dev = &ov13855->client->dev;
1583
1584 if (!IS_ERR(ov13855->pwdn_gpio))
1585 gpiod_set_value_cansleep(ov13855->pwdn_gpio, 0);
1586 clk_disable_unprepare(ov13855->xvclk);
1587 if (!IS_ERR(ov13855->reset_gpio))
1588 gpiod_set_value_cansleep(ov13855->reset_gpio, 0);
1589
1590 if (!IS_ERR_OR_NULL(ov13855->pins_sleep)) {
1591 ret = pinctrl_select_state(ov13855->pinctrl,
1592 ov13855->pins_sleep);
1593 if (ret < 0)
1594 dev_dbg(dev, "could not set pins\n");
1595 }
1596 if (!IS_ERR(ov13855->power_gpio))
1597 gpiod_set_value_cansleep(ov13855->power_gpio, 0);
1598
1599 regulator_bulk_disable(OV13855_NUM_SUPPLIES, ov13855->supplies);
1600 }
1601
ov13855_runtime_resume(struct device *dev)1602 static int ov13855_runtime_resume(struct device *dev)
1603 {
1604 struct i2c_client *client = to_i2c_client(dev);
1605 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1606 struct ov13855 *ov13855 = to_ov13855(sd);
1607
1608 return __ov13855_power_on(ov13855);
1609 }
1610
ov13855_runtime_suspend(struct device *dev)1611 static int ov13855_runtime_suspend(struct device *dev)
1612 {
1613 struct i2c_client *client = to_i2c_client(dev);
1614 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1615 struct ov13855 *ov13855 = to_ov13855(sd);
1616
1617 __ov13855_power_off(ov13855);
1618
1619 return 0;
1620 }
1621
1622 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov13855_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)1623 static int ov13855_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1624 {
1625 struct ov13855 *ov13855 = to_ov13855(sd);
1626 struct v4l2_mbus_framefmt *try_fmt =
1627 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1628 const struct ov13855_mode *def_mode = &supported_modes[0];
1629
1630 mutex_lock(&ov13855->mutex);
1631 /* Initialize try_fmt */
1632 try_fmt->width = def_mode->width;
1633 try_fmt->height = def_mode->height;
1634 try_fmt->code = OV13855_MEDIA_BUS_FMT;
1635 try_fmt->field = V4L2_FIELD_NONE;
1636
1637 mutex_unlock(&ov13855->mutex);
1638 /* No crop or compose */
1639
1640 return 0;
1641 }
1642 #endif
1643
ov13855_enum_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_frame_interval_enum *fie)1644 static int ov13855_enum_frame_interval(struct v4l2_subdev *sd,
1645 struct v4l2_subdev_pad_config *cfg,
1646 struct v4l2_subdev_frame_interval_enum *fie)
1647 {
1648 if (fie->index >= ARRAY_SIZE(supported_modes))
1649 return -EINVAL;
1650
1651 if (fie->code != OV13855_MEDIA_BUS_FMT)
1652 return -EINVAL;
1653
1654 fie->width = supported_modes[fie->index].width;
1655 fie->height = supported_modes[fie->index].height;
1656 fie->interval = supported_modes[fie->index].max_fps;
1657
1658 return 0;
1659 }
1660
ov13855_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad, struct v4l2_mbus_config *config)1661 static int ov13855_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1662 struct v4l2_mbus_config *config)
1663 {
1664 if (2 == OV13855_LANES) {
1665 config->type = V4L2_MBUS_CSI2_DPHY;
1666 config->flags = V4L2_MBUS_CSI2_2_LANE |
1667 V4L2_MBUS_CSI2_CHANNEL_0 |
1668 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1669 } else if (4 == OV13855_LANES) {
1670 config->type = V4L2_MBUS_CSI2_DPHY;
1671 config->flags = V4L2_MBUS_CSI2_4_LANE |
1672 V4L2_MBUS_CSI2_CHANNEL_0 |
1673 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1674 }
1675
1676 return 0;
1677 }
1678
ov13855_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_selection *sel)1679 static int ov13855_get_selection(struct v4l2_subdev *sd,
1680 struct v4l2_subdev_pad_config *cfg,
1681 struct v4l2_subdev_selection *sel)
1682 {
1683 struct ov13855 *ov13855 = to_ov13855(sd);
1684
1685 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1686 sel->r.left = 0;
1687 sel->r.width = ov13855->cur_mode->width;
1688 sel->r.top = 0;
1689 sel->r.height = ov13855->cur_mode->height;
1690 return 0;
1691 }
1692
1693 return -EINVAL;
1694 }
1695
1696 static const struct dev_pm_ops ov13855_pm_ops = {
1697 SET_RUNTIME_PM_OPS(ov13855_runtime_suspend,
1698 ov13855_runtime_resume, NULL)
1699 };
1700
1701 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1702 static const struct v4l2_subdev_internal_ops ov13855_internal_ops = {
1703 .open = ov13855_open,
1704 };
1705 #endif
1706
1707 static const struct v4l2_subdev_core_ops ov13855_core_ops = {
1708 .s_power = ov13855_s_power,
1709 .ioctl = ov13855_ioctl,
1710 #ifdef CONFIG_COMPAT
1711 .compat_ioctl32 = ov13855_compat_ioctl32,
1712 #endif
1713 };
1714
1715 static const struct v4l2_subdev_video_ops ov13855_video_ops = {
1716 .s_stream = ov13855_s_stream,
1717 .g_frame_interval = ov13855_g_frame_interval,
1718 };
1719
1720 static const struct v4l2_subdev_pad_ops ov13855_pad_ops = {
1721 .enum_mbus_code = ov13855_enum_mbus_code,
1722 .enum_frame_size = ov13855_enum_frame_sizes,
1723 .enum_frame_interval = ov13855_enum_frame_interval,
1724 .get_fmt = ov13855_get_fmt,
1725 .set_fmt = ov13855_set_fmt,
1726 .get_selection = ov13855_get_selection,
1727 .get_mbus_config = ov13855_g_mbus_config,
1728 };
1729
1730 static const struct v4l2_subdev_ops ov13855_subdev_ops = {
1731 .core = &ov13855_core_ops,
1732 .video = &ov13855_video_ops,
1733 .pad = &ov13855_pad_ops,
1734 };
1735
ov13855_set_ctrl(struct v4l2_ctrl *ctrl)1736 static int ov13855_set_ctrl(struct v4l2_ctrl *ctrl)
1737 {
1738 struct ov13855 *ov13855 = container_of(ctrl->handler,
1739 struct ov13855, ctrl_handler);
1740 struct i2c_client *client = ov13855->client;
1741 s64 max;
1742 int ret = 0;
1743
1744 /* Propagate change of current control to all related controls */
1745 switch (ctrl->id) {
1746 case V4L2_CID_VBLANK:
1747 /* Update max exposure while meeting expected vblanking */
1748 max = ov13855->cur_mode->height + ctrl->val - 4;
1749 __v4l2_ctrl_modify_range(ov13855->exposure,
1750 ov13855->exposure->minimum, max,
1751 ov13855->exposure->step,
1752 ov13855->exposure->default_value);
1753 break;
1754 }
1755
1756 if (!pm_runtime_get_if_in_use(&client->dev))
1757 return 0;
1758
1759 switch (ctrl->id) {
1760 case V4L2_CID_EXPOSURE:
1761 /* 4 least significant bits of expsoure are fractional part */
1762 ret = ov13855_write_reg(ov13855->client,
1763 OV13855_REG_EXPOSURE,
1764 OV13855_REG_VALUE_24BIT,
1765 ctrl->val << 4);
1766 break;
1767 case V4L2_CID_ANALOGUE_GAIN:
1768 ret = ov13855_write_reg(ov13855->client,
1769 OV13855_REG_GAIN_H,
1770 OV13855_REG_VALUE_08BIT,
1771 (ctrl->val >> OV13855_GAIN_H_SHIFT) &
1772 OV13855_GAIN_H_MASK);
1773 ret |= ov13855_write_reg(ov13855->client,
1774 OV13855_REG_GAIN_L,
1775 OV13855_REG_VALUE_08BIT,
1776 ctrl->val & OV13855_GAIN_L_MASK);
1777 break;
1778 case V4L2_CID_VBLANK:
1779 ret = ov13855_write_reg(ov13855->client,
1780 OV13855_REG_VTS,
1781 OV13855_REG_VALUE_16BIT,
1782 ctrl->val + ov13855->cur_mode->height);
1783 break;
1784 case V4L2_CID_TEST_PATTERN:
1785 ret = ov13855_enable_test_pattern(ov13855, ctrl->val);
1786 break;
1787 default:
1788 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1789 __func__, ctrl->id, ctrl->val);
1790 break;
1791 }
1792
1793 pm_runtime_put(&client->dev);
1794
1795 return ret;
1796 }
1797
1798 static const struct v4l2_ctrl_ops ov13855_ctrl_ops = {
1799 .s_ctrl = ov13855_set_ctrl,
1800 };
1801
ov13855_initialize_controls(struct ov13855 *ov13855)1802 static int ov13855_initialize_controls(struct ov13855 *ov13855)
1803 {
1804 const struct ov13855_mode *mode;
1805 struct v4l2_ctrl_handler *handler;
1806 s64 exposure_max, vblank_def;
1807 u32 h_blank;
1808 int ret;
1809 u64 dst_pixel_rate = 0;
1810 u32 lane_num = OV13855_LANES;
1811
1812 handler = &ov13855->ctrl_handler;
1813 mode = ov13855->cur_mode;
1814 ret = v4l2_ctrl_handler_init(handler, 8);
1815 if (ret)
1816 return ret;
1817 handler->lock = &ov13855->mutex;
1818
1819 ov13855->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1820 V4L2_CID_LINK_FREQ,
1821 1, 0, link_freq_items);
1822
1823 dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1824
1825 ov13855->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1826 V4L2_CID_PIXEL_RATE,
1827 0, OV13855_PIXEL_RATE,
1828 1, dst_pixel_rate);
1829
1830 __v4l2_ctrl_s_ctrl(ov13855->link_freq,
1831 mode->link_freq_idx);
1832
1833 h_blank = mode->hts_def - mode->width;
1834 ov13855->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1835 h_blank, h_blank, 1, h_blank);
1836 if (ov13855->hblank)
1837 ov13855->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1838
1839 vblank_def = mode->vts_def - mode->height;
1840 ov13855->vblank = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
1841 V4L2_CID_VBLANK, vblank_def,
1842 OV13855_VTS_MAX - mode->height,
1843 1, vblank_def);
1844
1845 exposure_max = mode->vts_def - 4;
1846 ov13855->exposure = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
1847 V4L2_CID_EXPOSURE, OV13855_EXPOSURE_MIN,
1848 exposure_max, OV13855_EXPOSURE_STEP,
1849 mode->exp_def);
1850
1851 ov13855->anal_gain = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
1852 V4L2_CID_ANALOGUE_GAIN, OV13855_GAIN_MIN,
1853 OV13855_GAIN_MAX, OV13855_GAIN_STEP,
1854 OV13855_GAIN_DEFAULT);
1855
1856 ov13855->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1857 &ov13855_ctrl_ops, V4L2_CID_TEST_PATTERN,
1858 ARRAY_SIZE(ov13855_test_pattern_menu) - 1,
1859 0, 0, ov13855_test_pattern_menu);
1860
1861 if (handler->error) {
1862 ret = handler->error;
1863 dev_err(&ov13855->client->dev,
1864 "Failed to init controls(%d)\n", ret);
1865 goto err_free_handler;
1866 }
1867
1868 ov13855->subdev.ctrl_handler = handler;
1869
1870 return 0;
1871
1872 err_free_handler:
1873 v4l2_ctrl_handler_free(handler);
1874
1875 return ret;
1876 }
1877
ov13855_check_sensor_id(struct ov13855 *ov13855, struct i2c_client *client)1878 static int ov13855_check_sensor_id(struct ov13855 *ov13855,
1879 struct i2c_client *client)
1880 {
1881 struct device *dev = &ov13855->client->dev;
1882 u32 id = 0;
1883 int ret;
1884
1885 ret = ov13855_read_reg(client, OV13855_REG_CHIP_ID,
1886 OV13855_REG_VALUE_24BIT, &id);
1887 if (id != CHIP_ID) {
1888 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1889 return -ENODEV;
1890 }
1891
1892 ret = ov13855_read_reg(client, OV13855_CHIP_REVISION_REG,
1893 OV13855_REG_VALUE_08BIT, &id);
1894 if (ret) {
1895 dev_err(dev, "Read chip revision register error\n");
1896 return ret;
1897 }
1898
1899 dev_info(dev, "Detected OV%06x sensor, REVISION 0x%x\n", CHIP_ID, id);
1900
1901 return 0;
1902 }
1903
ov13855_configure_regulators(struct ov13855 *ov13855)1904 static int ov13855_configure_regulators(struct ov13855 *ov13855)
1905 {
1906 unsigned int i;
1907
1908 for (i = 0; i < OV13855_NUM_SUPPLIES; i++)
1909 ov13855->supplies[i].supply = ov13855_supply_names[i];
1910
1911 return devm_regulator_bulk_get(&ov13855->client->dev,
1912 OV13855_NUM_SUPPLIES,
1913 ov13855->supplies);
1914 }
1915
ov13855_probe(struct i2c_client *client, const struct i2c_device_id *id)1916 static int ov13855_probe(struct i2c_client *client,
1917 const struct i2c_device_id *id)
1918 {
1919 struct device *dev = &client->dev;
1920 struct device_node *node = dev->of_node;
1921 struct ov13855 *ov13855;
1922 struct v4l2_subdev *sd;
1923 char facing[2];
1924 int ret;
1925
1926 dev_info(dev, "driver version: %02x.%02x.%02x",
1927 DRIVER_VERSION >> 16,
1928 (DRIVER_VERSION & 0xff00) >> 8,
1929 DRIVER_VERSION & 0x00ff);
1930
1931 ov13855 = devm_kzalloc(dev, sizeof(*ov13855), GFP_KERNEL);
1932 if (!ov13855)
1933 return -ENOMEM;
1934
1935 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1936 &ov13855->module_index);
1937 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1938 &ov13855->module_facing);
1939 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1940 &ov13855->module_name);
1941 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1942 &ov13855->len_name);
1943 if (ret) {
1944 dev_err(dev, "could not get module information!\n");
1945 return -EINVAL;
1946 }
1947
1948 ov13855->client = client;
1949 ov13855->cur_mode = &supported_modes[0];
1950
1951 ov13855->xvclk = devm_clk_get(dev, "xvclk");
1952 if (IS_ERR(ov13855->xvclk)) {
1953 dev_err(dev, "Failed to get xvclk\n");
1954 return -EINVAL;
1955 }
1956
1957 ov13855->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1958 if (IS_ERR(ov13855->power_gpio))
1959 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1960
1961 ov13855->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1962 if (IS_ERR(ov13855->reset_gpio))
1963 dev_warn(dev, "Failed to get reset-gpios\n");
1964
1965 ov13855->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1966 if (IS_ERR(ov13855->pwdn_gpio))
1967 dev_warn(dev, "Failed to get pwdn-gpios\n");
1968
1969 ret = ov13855_configure_regulators(ov13855);
1970 if (ret) {
1971 dev_err(dev, "Failed to get power regulators\n");
1972 return ret;
1973 }
1974
1975 ov13855->pinctrl = devm_pinctrl_get(dev);
1976 if (!IS_ERR(ov13855->pinctrl)) {
1977 ov13855->pins_default =
1978 pinctrl_lookup_state(ov13855->pinctrl,
1979 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1980 if (IS_ERR(ov13855->pins_default))
1981 dev_err(dev, "could not get default pinstate\n");
1982
1983 ov13855->pins_sleep =
1984 pinctrl_lookup_state(ov13855->pinctrl,
1985 OF_CAMERA_PINCTRL_STATE_SLEEP);
1986 if (IS_ERR(ov13855->pins_sleep))
1987 dev_err(dev, "could not get sleep pinstate\n");
1988 }
1989
1990 mutex_init(&ov13855->mutex);
1991
1992 sd = &ov13855->subdev;
1993 v4l2_i2c_subdev_init(sd, client, &ov13855_subdev_ops);
1994 ret = ov13855_initialize_controls(ov13855);
1995 if (ret)
1996 goto err_destroy_mutex;
1997
1998 ret = __ov13855_power_on(ov13855);
1999 if (ret)
2000 goto err_free_handler;
2001
2002 ret = ov13855_check_sensor_id(ov13855, client);
2003 if (ret)
2004 goto err_power_off;
2005
2006 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2007 sd->internal_ops = &ov13855_internal_ops;
2008 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2009 #endif
2010 #if defined(CONFIG_MEDIA_CONTROLLER)
2011 ov13855->pad.flags = MEDIA_PAD_FL_SOURCE;
2012 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2013 ret = media_entity_pads_init(&sd->entity, 1, &ov13855->pad);
2014 if (ret < 0)
2015 goto err_power_off;
2016 #endif
2017
2018 memset(facing, 0, sizeof(facing));
2019 if (strcmp(ov13855->module_facing, "back") == 0)
2020 facing[0] = 'b';
2021 else
2022 facing[0] = 'f';
2023
2024 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2025 ov13855->module_index, facing,
2026 OV13855_NAME, dev_name(sd->dev));
2027 ret = v4l2_async_register_subdev_sensor_common(sd);
2028 if (ret) {
2029 dev_err(dev, "v4l2 async register subdev failed\n");
2030 goto err_clean_entity;
2031 }
2032
2033 pm_runtime_set_active(dev);
2034 pm_runtime_enable(dev);
2035 pm_runtime_idle(dev);
2036
2037 return 0;
2038
2039 err_clean_entity:
2040 #if defined(CONFIG_MEDIA_CONTROLLER)
2041 media_entity_cleanup(&sd->entity);
2042 #endif
2043 err_power_off:
2044 __ov13855_power_off(ov13855);
2045 err_free_handler:
2046 v4l2_ctrl_handler_free(&ov13855->ctrl_handler);
2047 err_destroy_mutex:
2048 mutex_destroy(&ov13855->mutex);
2049
2050 return ret;
2051 }
2052
ov13855_remove(struct i2c_client *client)2053 static int ov13855_remove(struct i2c_client *client)
2054 {
2055 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2056 struct ov13855 *ov13855 = to_ov13855(sd);
2057
2058 v4l2_async_unregister_subdev(sd);
2059 #if defined(CONFIG_MEDIA_CONTROLLER)
2060 media_entity_cleanup(&sd->entity);
2061 #endif
2062 v4l2_ctrl_handler_free(&ov13855->ctrl_handler);
2063 mutex_destroy(&ov13855->mutex);
2064
2065 pm_runtime_disable(&client->dev);
2066 if (!pm_runtime_status_suspended(&client->dev))
2067 __ov13855_power_off(ov13855);
2068 pm_runtime_set_suspended(&client->dev);
2069
2070 return 0;
2071 }
2072
2073 #if IS_ENABLED(CONFIG_OF)
2074 static const struct of_device_id ov13855_of_match[] = {
2075 { .compatible = "ovti,ov13855" },
2076 {},
2077 };
2078 MODULE_DEVICE_TABLE(of, ov13855_of_match);
2079 #endif
2080
2081 static const struct i2c_device_id ov13855_match_id[] = {
2082 { "ovti,ov13855", 0 },
2083 {},
2084 };
2085
2086 static struct i2c_driver ov13855_i2c_driver = {
2087 .driver = {
2088 .name = OV13855_NAME,
2089 .pm = &ov13855_pm_ops,
2090 .of_match_table = of_match_ptr(ov13855_of_match),
2091 },
2092 .probe = &ov13855_probe,
2093 .remove = &ov13855_remove,
2094 .id_table = ov13855_match_id,
2095 };
2096
sensor_mod_init(void)2097 static int __init sensor_mod_init(void)
2098 {
2099 return i2c_add_driver(&ov13855_i2c_driver);
2100 }
2101
sensor_mod_exit(void)2102 static void __exit sensor_mod_exit(void)
2103 {
2104 i2c_del_driver(&ov13855_i2c_driver);
2105 }
2106
2107 device_initcall_sync(sensor_mod_init);
2108 module_exit(sensor_mod_exit);
2109
2110 MODULE_DESCRIPTION("OmniVision ov13855 sensor driver");
2111 MODULE_LICENSE("GPL v2");
2112