1 /* 2 * Copyright (C) 2016 Rockchip Electronics Co., Ltd. 3 * Authors: 4 * Zhiqin Wei <wzq@rock-chips.com> 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef _RGA_DRIVER_H_ 20 #define _RGA_DRIVER_H_ 21 22 #include <asm/ioctl.h> 23 #include <stdint.h> 24 25 #ifdef __cplusplus 26 extern "C" 27 { 28 #endif 29 30 /* Use 'r' as magic number */ 31 #define RGA_IOC_MAGIC 'r' 32 #define RGA_IOW(nr, type) _IOW(RGA_IOC_MAGIC, nr, type) 33 #define RGA_IOR(nr, type) _IOR(RGA_IOC_MAGIC, nr, type) 34 #define RGA_IOWR(nr, type) _IOWR(RGA_IOC_MAGIC, nr, type) 35 36 #define RGA_IOC_GET_DRVIER_VERSION RGA_IOR(0x1, struct rga_version_t) 37 #define RGA_IOC_GET_HW_VERSION RGA_IOR(0x2, struct rga_hw_versions_t) 38 #define RGA_IOC_IMPORT_BUFFER RGA_IOWR(0x3, struct rga_buffer_pool) 39 #define RGA_IOC_RELEASE_BUFFER RGA_IOW(0x4, struct rga_buffer_pool) 40 #define RGA_START_CONFIG RGA_IOR(0x5, uint32_t) 41 #define RGA_END_CONFIG RGA_IOWR(0x6, struct rga_user_ctx_t) 42 #define RGA_CMD_CONFIG RGA_IOWR(0x7, struct rga_user_ctx_t) 43 #define RGA_CANCEL_CONFIG RGA_IOWR(0x8, uint32_t) 44 45 #define RGA_BLIT_SYNC 0x5017 46 #define RGA_BLIT_ASYNC 0x5018 47 #define RGA_FLUSH 0x5019 48 #define RGA_GET_RESULT 0x501a 49 #define RGA_GET_VERSION 0x501b 50 51 #define RGA2_BLIT_SYNC 0x6017 52 #define RGA2_BLIT_ASYNC 0x6018 53 #define RGA2_FLUSH 0x6019 54 #define RGA2_GET_RESULT 0x601a 55 #define RGA2_GET_VERSION 0x601b 56 57 #define RGA_REG_CTRL_LEN 0x8 /* 8 */ 58 #define RGA_REG_CMD_LEN 0x1c /* 28 */ 59 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 60 61 #ifndef ENABLE 62 #define ENABLE 1 63 #endif 64 65 #ifndef DISABLE 66 #define DISABLE 0 67 #endif 68 69 enum rga_memory_type { 70 RGA_DMA_BUFFER = 0, 71 RGA_VIRTUAL_ADDRESS, 72 RGA_PHYSICAL_ADDRESS 73 }; 74 75 /* RGA process mode enum */ 76 enum { 77 bitblt_mode = 0x0, 78 color_palette_mode = 0x1, 79 color_fill_mode = 0x2, 80 line_point_drawing_mode = 0x3, 81 blur_sharp_filter_mode = 0x4, 82 pre_scaling_mode = 0x5, 83 update_palette_table_mode = 0x6, 84 update_patten_buff_mode = 0x7, 85 }; 86 87 88 enum { 89 rop_enable_mask = 0x2, 90 dither_enable_mask = 0x8, 91 fading_enable_mask = 0x10, 92 PD_enbale_mask = 0x20, 93 }; 94 95 enum { 96 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 97 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 98 yuv2rgb_mode2 = 0x2, /* BT.709 */ 99 100 rgb2yuv_601_full = 0x1 << 8, 101 rgb2yuv_709_full = 0x2 << 8, 102 yuv2yuv_601_limit_2_709_limit = 0x3 << 8, 103 yuv2yuv_601_limit_2_709_full = 0x4 << 8, 104 yuv2yuv_709_limit_2_601_limit = 0x5 << 8, 105 yuv2yuv_709_limit_2_601_full = 0x6 << 8, //not support 106 yuv2yuv_601_full_2_709_limit = 0x7 << 8, 107 yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support 108 yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support 109 yuv2yuv_709_full_2_601_full = 0xa << 8, //not support 110 full_csc_mask = 0xf00, 111 }; 112 113 /* RGA rotate mode */ 114 enum { 115 rotate_mode0 = 0x0, /* no rotate */ 116 rotate_mode1 = 0x1, /* rotate */ 117 rotate_mode2 = 0x2, /* x_mirror */ 118 rotate_mode3 = 0x3, /* y_mirror */ 119 }; 120 121 enum { 122 color_palette_mode0 = 0x0, /* 1K */ 123 color_palette_mode1 = 0x1, /* 2K */ 124 color_palette_mode2 = 0x2, /* 4K */ 125 color_palette_mode3 = 0x3, /* 8K */ 126 }; 127 128 enum { 129 BB_BYPASS = 0x0, /* no rotate */ 130 BB_ROTATE = 0x1, /* rotate */ 131 BB_X_MIRROR = 0x2, /* x_mirror */ 132 BB_Y_MIRROR = 0x3 /* y_mirror */ 133 }; 134 135 enum { 136 nearby = 0x0, /* no rotate */ 137 bilinear = 0x1, /* rotate */ 138 bicubic = 0x2, /* x_mirror */ 139 }; 140 141 #define RGA_SCHED_PRIORITY_DEFAULT 0 142 #define RGA_SCHED_PRIORITY_MAX 6 143 144 enum { 145 RGA3_SCHEDULER_CORE0 = 1 << 0, 146 RGA3_SCHEDULER_CORE1 = 1 << 1, 147 RGA2_SCHEDULER_CORE0 = 1 << 2, 148 }; 149 150 /* 151 // Alpha Red Green Blue 152 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 153 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 154 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 155 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 156 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 157 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 158 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 159 { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888 160 161 */ 162 /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, 163 * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ 164 typedef enum _Rga_SURF_FORMAT { 165 RK_FORMAT_RGBA_8888 = 0x0 << 8, 166 RK_FORMAT_RGBX_8888 = 0x1 << 8, 167 RK_FORMAT_RGB_888 = 0x2 << 8, 168 RK_FORMAT_BGRA_8888 = 0x3 << 8, 169 RK_FORMAT_RGB_565 = 0x4 << 8, 170 RK_FORMAT_RGBA_5551 = 0x5 << 8, 171 RK_FORMAT_RGBA_4444 = 0x6 << 8, 172 RK_FORMAT_BGR_888 = 0x7 << 8, 173 174 RK_FORMAT_YCbCr_422_SP = 0x8 << 8, 175 RK_FORMAT_YCbCr_422_P = 0x9 << 8, 176 RK_FORMAT_YCbCr_420_SP = 0xa << 8, 177 RK_FORMAT_YCbCr_420_P = 0xb << 8, 178 179 RK_FORMAT_YCrCb_422_SP = 0xc << 8, 180 RK_FORMAT_YCrCb_422_P = 0xd << 8, 181 RK_FORMAT_YCrCb_420_SP = 0xe << 8, 182 RK_FORMAT_YCrCb_420_P = 0xf << 8, 183 184 RK_FORMAT_BPP1 = 0x10 << 8, 185 RK_FORMAT_BPP2 = 0x11 << 8, 186 RK_FORMAT_BPP4 = 0x12 << 8, 187 RK_FORMAT_BPP8 = 0x13 << 8, 188 189 RK_FORMAT_Y4 = 0x14 << 8, 190 RK_FORMAT_YCbCr_400 = 0x15 << 8, 191 192 RK_FORMAT_BGRX_8888 = 0x16 << 8, 193 194 RK_FORMAT_YVYU_422 = 0x18 << 8, 195 RK_FORMAT_YVYU_420 = 0x19 << 8, 196 RK_FORMAT_VYUY_422 = 0x1a << 8, 197 RK_FORMAT_VYUY_420 = 0x1b << 8, 198 RK_FORMAT_YUYV_422 = 0x1c << 8, 199 RK_FORMAT_YUYV_420 = 0x1d << 8, 200 RK_FORMAT_UYVY_422 = 0x1e << 8, 201 RK_FORMAT_UYVY_420 = 0x1f << 8, 202 203 RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, 204 RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, 205 RK_FORMAT_YCbCr_422_SP_10B = 0x22 << 8, 206 RK_FORMAT_YCrCb_422_SP_10B = 0x23 << 8, 207 /* For compatibility with misspellings */ 208 RK_FORMAT_YCbCr_422_10b_SP = RK_FORMAT_YCbCr_422_SP_10B, 209 RK_FORMAT_YCrCb_422_10b_SP = RK_FORMAT_YCrCb_422_SP_10B, 210 211 RK_FORMAT_BGR_565 = 0x24 << 8, 212 RK_FORMAT_BGRA_5551 = 0x25 << 8, 213 RK_FORMAT_BGRA_4444 = 0x26 << 8, 214 215 RK_FORMAT_ARGB_8888 = 0x28 << 8, 216 RK_FORMAT_XRGB_8888 = 0x29 << 8, 217 RK_FORMAT_ARGB_5551 = 0x2a << 8, 218 RK_FORMAT_ARGB_4444 = 0x2b << 8, 219 RK_FORMAT_ABGR_8888 = 0x2c << 8, 220 RK_FORMAT_XBGR_8888 = 0x2d << 8, 221 RK_FORMAT_ABGR_5551 = 0x2e << 8, 222 RK_FORMAT_ABGR_4444 = 0x2f << 8, 223 224 RK_FORMAT_RGBA2BPP = 0x30 << 8, 225 226 RK_FORMAT_UNKNOWN = 0x100 << 8, 227 } RgaSURF_FORMAT; 228 229 /* RGA3 rd_mode */ 230 enum 231 { 232 raster_mode = 0x1 << 0, 233 fbc_mode = 0x1 << 1, 234 tile_mode = 0x1 << 2, 235 }; 236 237 typedef struct rga_img_info_t { 238 uint64_t yrgb_addr; /* yrgb mem addr */ 239 uint64_t uv_addr; /* cb/cr mem addr */ 240 uint64_t v_addr; /* cr mem addr */ 241 242 uint32_t format; //definition by RK_FORMAT 243 uint16_t act_w; 244 uint16_t act_h; 245 uint16_t x_offset; 246 uint16_t y_offset; 247 248 uint16_t vir_w; 249 uint16_t vir_h; 250 251 uint16_t endian_mode; //for BPP 252 uint16_t alpha_swap; 253 254 //used by RGA3 255 uint16_t rotate_mode; 256 uint16_t rd_mode; 257 258 uint16_t is_10b_compact; 259 uint16_t is_10b_endian; 260 261 uint16_t enable; 262 } 263 rga_img_info_t; 264 265 typedef struct POINT { 266 uint16_t x; 267 uint16_t y; 268 } 269 POINT; 270 271 typedef struct RECT { 272 uint16_t xmin; 273 uint16_t xmax; // width - 1 274 uint16_t ymin; 275 uint16_t ymax; // height - 1 276 } RECT; 277 278 typedef struct MMU { 279 uint8_t mmu_en; 280 uint64_t base_addr; 281 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ 282 } MMU; 283 284 typedef struct COLOR_FILL { 285 int16_t gr_x_a; 286 int16_t gr_y_a; 287 int16_t gr_x_b; 288 int16_t gr_y_b; 289 int16_t gr_x_g; 290 int16_t gr_y_g; 291 int16_t gr_x_r; 292 int16_t gr_y_r; 293 //u8 cp_gr_saturation; 294 } 295 COLOR_FILL; 296 297 typedef struct FADING { 298 uint8_t b; 299 uint8_t g; 300 uint8_t r; 301 uint8_t res; 302 } 303 FADING; 304 305 typedef struct line_draw_t { 306 POINT start_point; /* LineDraw_start_point */ 307 POINT end_point; /* LineDraw_end_point */ 308 uint32_t color; /* LineDraw_color */ 309 uint32_t flag; /* (enum) LineDrawing mode sel */ 310 uint32_t line_width; /* range 1~16 */ 311 } 312 line_draw_t; 313 314 /* color space convert coefficient. */ 315 typedef struct csc_coe_t { 316 int16_t r_v; 317 int16_t g_y; 318 int16_t b_u; 319 int32_t off; 320 } csc_coe_t; 321 322 typedef struct full_csc_t { 323 uint8_t flag; 324 csc_coe_t coe_y; 325 csc_coe_t coe_u; 326 csc_coe_t coe_v; 327 } full_csc_t; 328 329 struct rga_mosaic_info { 330 uint8_t enable; 331 uint8_t mode; 332 }; 333 334 struct rga_pre_intr_info { 335 uint8_t enable; 336 337 uint8_t read_intr_en; 338 uint8_t write_intr_en; 339 uint8_t read_hold_en; 340 uint32_t read_threshold; 341 uint32_t write_start; 342 uint32_t write_step; 343 }; 344 345 /* MAX(min, (max - channel_value)) */ 346 struct rga_osd_invert_factor { 347 uint8_t alpha_max; 348 uint8_t alpha_min; 349 uint8_t yg_max; 350 uint8_t yg_min; 351 uint8_t crb_max; 352 uint8_t crb_min; 353 }; 354 355 struct rga_color { 356 union { 357 struct { 358 uint8_t red; 359 uint8_t green; 360 uint8_t blue; 361 uint8_t alpha; 362 }; 363 uint32_t value; 364 }; 365 }; 366 367 struct rga_osd_bpp2 { 368 uint8_t ac_swap; // ac swap flag 369 // 0: CA 370 // 1: AC 371 uint8_t endian_swap; // rgba2bpp endian swap 372 // 0: Big endian 373 // 1: Little endian 374 struct rga_color color0; 375 struct rga_color color1; 376 }; 377 378 struct rga_osd_mode_ctrl { 379 uint8_t mode; // OSD cal mode: 380 // 0b'1: statistics mode 381 // 1b'1: auto inversion overlap mode 382 uint8_t direction_mode; // horizontal or vertical 383 // 0: horizontal 384 // 1: vertical 385 uint8_t width_mode; // using @fix_width or LUT width 386 // 0: fix width 387 // 1: LUT width 388 uint16_t block_fix_width; // OSD block fixed width 389 // real width = (fix_width + 1) * 2 390 uint8_t block_num; // OSD block num 391 uint16_t flags_index; // auto invert flags index 392 393 /* invertion config */ 394 uint8_t color_mode; // selete color 395 // 0: src1 color 396 // 1: config data color 397 uint8_t invert_flags_mode; // invert flag selete 398 // 0: use RAM flag 399 // 1: usr last result 400 uint8_t default_color_sel; // default color mode 401 // 0: default is bright 402 // 1: default is dark 403 uint8_t invert_enable; // invert channel enable 404 // 1 << 0: aplha enable 405 // 1 << 1: Y/G disable 406 // 1 << 2: C/RB disable 407 uint8_t invert_mode; // invert cal mode 408 // 0: normal(max-data) 409 // 1: swap 410 uint8_t invert_thresh; // if luma > thresh, osd_flag to be 1 411 uint8_t unfix_index; // OSD width config index 412 }; 413 414 struct rga_osd_info { 415 uint8_t enable; 416 417 struct rga_osd_mode_ctrl mode_ctrl; 418 struct rga_osd_invert_factor cal_factor; 419 struct rga_osd_bpp2 bpp2_info; 420 421 union { 422 struct { 423 uint32_t last_flags1; 424 uint32_t last_flags0; 425 }; 426 uint64_t last_flags; 427 }; 428 429 union { 430 struct { 431 uint32_t cur_flags1; 432 uint32_t cur_flags0; 433 }; 434 uint64_t cur_flags; 435 }; 436 }; 437 438 #define RGA_VERSION_SIZE 16 439 #define RGA_HW_SIZE 5 440 441 struct rga_version_t { 442 uint32_t major; 443 uint32_t minor; 444 uint32_t revision; 445 uint8_t str[RGA_VERSION_SIZE]; 446 }; 447 448 struct rga_hw_versions_t { 449 struct rga_version_t version[RGA_HW_SIZE]; 450 uint32_t size; 451 }; 452 453 struct rga_memory_parm { 454 uint32_t width; 455 uint32_t height; 456 uint32_t format; 457 458 uint32_t size; 459 }; 460 461 struct rga_external_buffer { 462 uint64_t memory; 463 uint32_t type; 464 465 uint32_t handle; 466 struct rga_memory_parm memory_info; 467 468 uint8_t reserve[252]; 469 }; 470 471 struct rga_buffer_pool { 472 uint64_t buffers; 473 uint32_t size; 474 }; 475 476 struct rga_req { 477 uint8_t render_mode; /* (enum) process mode sel */ 478 479 rga_img_info_t src; /* src image info */ 480 rga_img_info_t dst; /* dst image info */ 481 rga_img_info_t pat; /* patten image info */ 482 483 uint64_t rop_mask_addr; /* rop4 mask addr */ 484 uint64_t LUT_addr; /* LUT addr */ 485 486 RECT clip; /* dst clip window default value is dst_vir */ 487 /* value from [0, w-1] / [0, h-1]*/ 488 489 int32_t sina; /* dst angle default value 0 16.16 scan from table */ 490 int32_t cosa; /* dst angle default value 0 16.16 scan from table */ 491 492 uint16_t alpha_rop_flag; /* alpha rop process flag */ 493 /* ([0] = 1 alpha_rop_enable) */ 494 /* ([1] = 1 rop enable) */ 495 /* ([2] = 1 fading_enable) */ 496 /* ([3] = 1 PD_enable) */ 497 /* ([4] = 1 alpha cal_mode_sel) */ 498 /* ([5] = 1 dither_enable) */ 499 /* ([6] = 1 gradient fill mode sel) */ 500 /* ([7] = 1 AA_enable) */ 501 /* ([8] = 1 nn_quantize) */ 502 /* ([9] = 1 Real color mode) */ 503 504 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 505 506 uint32_t color_key_max; /* color key max */ 507 uint32_t color_key_min; /* color key min */ 508 509 uint32_t fg_color; /* foreground color */ 510 uint32_t bg_color; /* background color */ 511 512 COLOR_FILL gr_color; /* color fill use gradient */ 513 514 line_draw_t line_draw_info; 515 516 FADING fading; 517 518 uint8_t PD_mode; /* porter duff alpha mode sel */ 519 520 uint8_t alpha_global_value; /* global alpha value */ 521 522 uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ 523 524 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 525 526 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 527 528 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 529 530 uint8_t endian_mode; /* 0/big endian 1/little endian*/ 531 532 uint8_t rotate_mode; /* (enum) rotate mode */ 533 /* 0x0, no rotate */ 534 /* 0x1, rotate */ 535 /* 0x2, x_mirror */ 536 /* 0x3, y_mirror */ 537 538 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ 539 540 MMU mmu_info; /* mmu information */ 541 542 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ 543 /* ([2~3] rop mode) */ 544 /* ([4] zero mode en) */ 545 /* ([5] dst alpha mode) (RGA1) */ 546 547 uint8_t src_trans_mode; 548 549 uint8_t dither_mode; 550 551 full_csc_t full_csc; /* full color space convert */ 552 553 int32_t in_fence_fd; 554 uint8_t core; 555 uint8_t priority; 556 int32_t out_fence_fd; 557 558 uint8_t handle_flag; 559 560 /* RGA2 1106 add */ 561 struct rga_mosaic_info mosaic_info; 562 563 uint8_t uvhds_mode; 564 uint8_t uvvds_mode; 565 566 struct rga_osd_info osd_info; 567 568 struct rga_pre_intr_info pre_intr_info; 569 570 uint8_t reservr[59]; 571 }; 572 573 struct rga_user_ctx_t { 574 uint64_t cmd_ptr; 575 uint32_t cmd_num; 576 uint32_t id; 577 uint32_t sync_mode; 578 uint32_t out_fence_fd; 579 580 uint32_t mpi_config_flags; 581 582 uint8_t reservr[124]; 583 }; 584 585 #ifdef __cplusplus 586 } 587 #endif 588 589 #endif /*_RK29_IPP_DRIVER_H_*/ 590