1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #ifndef DW_MMC_H_ 17 #define DW_MMC_H_ 18 #include "rk_sdmmc_dbg.h" 19 20 #define DW_MMC_240A 0x240a 21 #define DW_MMC_270A 0x270a 22 23 #define SDMMC_CTRL 0x000 24 #define SDMMC_PWREN 0x004 25 #define SDMMC_CLKDIV 0x008 26 #define SDMMC_CLKSRC 0x00c 27 #define SDMMC_CLKENA 0x010 28 #define SDMMC_TMOUT 0x014 29 #define SDMMC_CTYPE 0x018 30 #define SDMMC_BLKSIZ 0x01c 31 #define SDMMC_BYTCNT 0x020 32 #define SDMMC_INTMASK 0x024 33 #define SDMMC_CMDARG 0x028 34 #define SDMMC_CMD 0x02c 35 #define SDMMC_RESP0 0x030 36 #define SDMMC_RESP1 0x034 37 #define SDMMC_RESP2 0x038 38 #define SDMMC_RESP3 0x03c 39 #define SDMMC_MINTSTS 0x040 40 #define SDMMC_RINTSTS 0x044 41 #define SDMMC_STATUS 0x048 42 #define SDMMC_FIFOTH 0x04c 43 #define SDMMC_CDETECT 0x050 44 #define SDMMC_WRTPRT 0x054 45 #define SDMMC_GPIO 0x058 46 #define SDMMC_TCBCNT 0x05c 47 #define SDMMC_TBBCNT 0x060 48 #define SDMMC_DEBNCE 0x064 49 #define SDMMC_USRID 0x068 50 #define SDMMC_VERID 0x06c 51 #define SDMMC_HCON 0x070 52 #define SDMMC_UHS_REG 0x074 53 #define SDMMC_RST_N 0x078 54 #define SDMMC_BMOD 0x080 55 #define SDMMC_PLDMND 0x084 56 #define SDMMC_DBADDR 0x088 57 #define SDMMC_IDSTS 0x08c 58 #define SDMMC_IDINTEN 0x090 59 #define SDMMC_DSCADDR 0x094 60 #define SDMMC_BUFADDR 0x098 61 #define SDMMC_CDTHRCTL 0x100 62 #define SDMMC_DATA(x) (x) 63 64 static const u8 tuning_blk_pattern_4bit[] = { 65 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, 66 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb, 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef, 67 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c, 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee, 68 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff, 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde, 69 }; 70 71 static const u8 tuning_blk_pattern_8bit[] = { 72 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, 0xcc, 0x33, 0x33, 73 0xcc, 0xcc, 0xcc, 0xff, 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 74 0xdd, 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 0x77, 75 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0xcc, 76 0xcc, 0xcc, 0x33, 0xcc, 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 77 0xee, 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, 0xbb, 78 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 79 }; 80 81 /* 82 * Data offset is difference according to Version 83 * Lower than 2.40a : data register offest is 0x100 84 */ 85 #define DATA_OFFSET 0x100 86 #define DATA_240A_OFFSET 0x200 87 88 /* shift bit field */ 89 #define RK_SDMMC_SBF(f, v) ((v) << (f)) 90 91 struct sdmmc_reg { 92 u32 addr; 93 char *name; 94 }; 95 96 static const struct sdmmc_reg dw_mci_regs[] = {{0x0000, "CTRL"}, 97 {0x0004, "PWREN"}, 98 {0x0008, "CLKDIV"}, 99 {0x000C, "CLKSRC"}, 100 {0x0010, "CLKENA"}, 101 {0x0014, "TMOUT"}, 102 {0x0018, "CTYPE"}, 103 {0x001C, "BLKSIZ"}, 104 {0x0020, "BYTCNT"}, 105 {0x0024, "INTMASK"}, 106 {0x0028, "CMDARG"}, 107 {0x002C, "CMD"}, 108 {0x0030, "RESP0"}, 109 {0x0034, "RESP1"}, 110 {0x0038, "RESP2"}, 111 {0x003C, "RESP3"}, 112 {0x0040, "MINSTS"}, 113 {0x0044, "RINTSTS"}, 114 {0x0048, "STATUS"}, 115 {0x004C, "FIFOTH"}, 116 {0x0050, "CDETECT"}, 117 {0x0054, "WRTPRT"}, 118 {0x0058, "GPIO"}, 119 {0x005C, "TCBCNT"}, 120 {0x0060, "TBBCNT"}, 121 {0x0064, "DEBNCE"}, 122 {0x0068, "USRID"}, 123 {0x006C, "VERID"}, 124 {0x0070, "HCON"}, 125 {0x0074, "UHS_REG"}, 126 {0x0078, "RST_n"}, 127 {0x0080, "BMOD"}, 128 {0x0084, "PLDMND"}, 129 {0x0088, "DBADDR"}, 130 {0x008C, "IDSTS"}, 131 {0x0090, "IDINTEN"}, 132 {0x0094, "DSCADDR"}, 133 {0x0098, "BUFADDR"}, 134 {0x0100, "CARDTHRCTL"}, 135 {0x0104, "BackEndPwr"}, 136 {0, 0}}; 137 138 /* Control register defines */ 139 #define SDMMC_CTRL_USE_IDMAC BIT(25) 140 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 141 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 142 #define SDMMC_CTRL_SEND_CCSD BIT(9) 143 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 144 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 145 #define SDMMC_CTRL_READ_WAIT BIT(6) 146 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 147 #define SDMMC_CTRL_INT_ENABLE BIT(4) 148 #define SDMMC_CTRL_DMA_RESET BIT(2) 149 #define SDMMC_CTRL_FIFO_RESET BIT(1) 150 #define SDMMC_CTRL_RESET BIT(0) 151 /* Clock Enable register defines */ 152 #define SDMMC_CLKEN_LOW_PWR BIT(16) 153 #define SDMMC_CLKEN_ENABLE BIT(0) 154 /* time-out register defines */ 155 #define SDMMC_TMOUT_DATA(n) RK_SDMMC_SBF(8, (n)) 156 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 157 #define SDMMC_TMOUT_RESP(n) ((n)&0xFF) 158 #define SDMMC_TMOUT_RESP_MSK 0xFF 159 /* card-type register defines */ 160 #define SDMMC_CTYPE_8BIT BIT(16) 161 #define SDMMC_CTYPE_4BIT BIT(0) 162 #define SDMMC_CTYPE_1BIT 0 163 /* Interrupt status & mask register defines */ 164 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 165 #define SDMMC_INT_EBE BIT(15) 166 #define SDMMC_INT_ACD BIT(14) 167 #define SDMMC_INT_SBE BIT(13) 168 #define SDMMC_INT_HLE BIT(12) 169 #define SDMMC_INT_FRUN BIT(11) 170 #define SDMMC_INT_HTO BIT(10) 171 #define SDMMC_INT_VSI SDMMC_INT_HTO 172 #define SDMMC_INT_DRTO BIT(9) 173 #define SDMMC_INT_RTO BIT(8) 174 #define SDMMC_INT_DCRC BIT(7) 175 #define SDMMC_INT_RCRC BIT(6) 176 #define SDMMC_INT_RXDR BIT(5) 177 #define SDMMC_INT_TXDR BIT(4) 178 #define SDMMC_INT_DATA_OVER BIT(3) 179 #define SDMMC_INT_CMD_DONE BIT(2) 180 #define SDMMC_INT_RESP_ERR BIT(1) 181 #define SDMMC_INT_CD BIT(0) 182 #define SDMMC_INT_ERROR 0xbfc2 183 /* Command register defines */ 184 #define SDMMC_CMD_START BIT(31) 185 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 186 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 187 #define SDMMC_CMD_BOOT_MODE BIT(27) 188 #define SDMMC_CMD_DISABLE_BOOT BIT(26) 189 #define SDMMC_CMD_EXPECT_BOOT_ACK BIT(25) 190 #define SDMMC_CMD_ENABLE_BOOT BIT(24) 191 #define SDMMC_CMD_CCS_EXP BIT(23) 192 #define SDMMC_CMD_CEATA_RD BIT(22) 193 #define SDMMC_CMD_UPD_CLK BIT(21) 194 #define SDMMC_CMD_INIT BIT(15) 195 #define SDMMC_CMD_STOP BIT(14) 196 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 197 #define SDMMC_CMD_SEND_STOP BIT(12) 198 #define SDMMC_CMD_STRM_MODE BIT(11) 199 #define SDMMC_CMD_DAT_WR BIT(10) 200 #define SDMMC_CMD_DAT_EXP BIT(9) 201 #define SDMMC_CMD_RESP_CRC BIT(8) 202 #define SDMMC_CMD_RESP_LONG BIT(7) 203 #define SDMMC_CMD_RESP_EXP BIT(6) 204 #define SDMMC_CMD_INDX(n) ((n)&0x1F) 205 /* Status register defines */ 206 #define SDMMC_GET_FCNT(x) (((x) >> 17) & 0x1FFF) 207 #define SDMMC_STAUTS_MC_BUSY BIT(10) 208 #define SDMMC_STAUTS_DATA_BUSY BIT(9) 209 #define SDMMC_CMD_FSM_MASK (0x0F << 4) 210 #define SDMMC_CMD_FSM_IDLE (0x00) 211 #define SDMMC_STAUTS_FIFO_FULL BIT(3) 212 #define SDMMC_STAUTS_FIFO_EMPTY BIT(2) 213 214 /* Control SDMMC_UHS_REG defines (base+ 0x74) */ 215 #define SDMMC_UHS_DDR_MODE BIT(16) 216 #define SDMMC_UHS_VOLT_REG_18 BIT(0) 217 218 /* FIFOTH register defines */ 219 #define SDMMC_SET_FIFOTH(m, r, t) (((m)&0x7) << 28 | ((r)&0xFFF) << 16 | ((t)&0xFFF)) 220 /* Internal DMAC interrupt defines */ 221 #define SDMMC_IDMAC_INT_AI BIT(9) 222 #define SDMMC_IDMAC_INT_NI BIT(8) 223 #define SDMMC_IDMAC_INT_CES BIT(5) 224 #define SDMMC_IDMAC_INT_DU BIT(4) 225 #define SDMMC_IDMAC_INT_FBE BIT(2) 226 #define SDMMC_IDMAC_INT_RI BIT(1) 227 #define SDMMC_IDMAC_INT_TI BIT(0) 228 /* Internal DMAC bus mode bits */ 229 #define SDMMC_IDMAC_ENABLE BIT(7) 230 #define SDMMC_IDMAC_FB BIT(1) 231 #define SDMMC_IDMAC_SWRESET BIT(0) 232 /* Version ID register define */ 233 #define SDMMC_GET_VERID(x) ((x)&0xFFFF) 234 /* Card read threshold */ 235 #define SDMMC_SET_RD_THLD(v, x) (((v)&0xFFF) << 16 | (x)) 236 237 /* Register access macros */ 238 #define mci_readl(dev, reg) __raw_readl((dev)->regs + SDMMC_##reg) 239 #define mci_writel(dev, reg, value) __raw_writel((value), (dev)->regs + SDMMC_##reg) 240 #define mci_readreg(dev, addr) __raw_readl((dev)->regs + (addr)) 241 #define mci_writereg(dev, addr, value) __raw_writel((value), (dev)->regs + (addr)) 242 243 /* 16-bit FIFO access macros */ 244 #define mci_readw(dev, reg) __raw_readw((dev)->regs + SDMMC_##reg) 245 #define mci_writew(dev, reg, value) __raw_writew((value), (dev)->regs + SDMMC_##reg) 246 247 /* 64-bit FIFO access macros */ 248 #ifdef readq 249 #define mci_readq(dev, reg) __raw_readq((dev)->regs + SDMMC_##reg) 250 #define mci_writeq(dev, reg, value) __raw_writeq((value), (dev)->regs + SDMMC_##reg) 251 #else 252 /* 253 * Dummy readq implementation for architectures that don't define it. 254 * 255 * We would assume that none of these architectures would configure 256 * the IP block with a 64bit FIFO width, so this code will never be 257 * executed on those machines. Defining these macros here keeps the 258 * rest of the code free from ifdefs. 259 */ 260 #define mci_readq(dev, reg) (*(u64 __force *)((dev)->regs + SDMMC_##reg)) 261 #define mci_writeq(dev, reg, value) (*(u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 262 #endif 263 #ifdef CONFIG_PM 264 extern int dw_mci_suspend(struct dw_mci *host); 265 extern int dw_mci_resume(struct dw_mci *host); 266 #endif 267 static const struct dw_mci_rst_ops dw_mci_pdrst_ops; 268 269 /** 270 * struct dw_mci_slot - MMC slot state 271 * @mmc: The mmc_host representing this slot. 272 * @host: The MMC controller this slot is using. 273 * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) 274 * @wp_gpio: If gpio_is_valid() we'll use this to read write protect. 275 * @ctype: Card type for this slot. 276 * @mrq: mmc_request currently being processed or waiting to be 277 * processed, or NULL when the slot is idle. 278 * @queue_node: List node for placing this node in the @queue list of 279 * &struct dw_mci. 280 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 281 * @__clk_old: The last updated clock with reflecting clock divider. 282 * Keeping track of this helps us to avoid spamming the console 283 * with CONFIG_MMC_CLKGATE. 284 * @flags: Random state bits associated with the slot. 285 * @id: Number of this slot. 286 * @last_detect_state: Most recently observed card detect state. 287 */ 288 struct dw_mci_slot { 289 struct mmc_host *mmc; 290 struct dw_mci *host; 291 int quirks; 292 int wp_gpio; 293 int cd_gpio; 294 int pwr_en_gpio; 295 u32 ctype; 296 u32 pre_ctype; 297 298 struct mmc_request *mrq; 299 struct list_head queue_node; 300 301 unsigned int clock; 302 unsigned int rk_sdmmc_clk_old; 303 304 unsigned long flags; 305 #define DW_MMC_CARD_PRESENT 0 306 #define DW_MMC_CARD_NEED_INIT 1 307 int id; 308 int last_detect_state; 309 }; 310 311 struct dw_mci_tuning_data { 312 const u8 *blk_pattern; 313 unsigned int blksz; 314 }; 315 316 /** 317 * dw_mci driver data - dw-mshc implementation specific driver data. 318 * @caps: mmc subsystem specified capabilities of the controller(s). 319 * @hold_reg_flag: Fixed the value of HOLG_REG 320 * @init: early implementation specific initialization. 321 * @setup_clock: implementation specific clock configuration. 322 * @prepare_command: handle CMD register extensions. 323 * @set_ios: handle bus specific extensions. 324 * @parse_dt: parse implementation specific device tree properties. 325 * 326 * Provide controller implementation specific extensions. The usage of this 327 * data structure is fully optional and usage of each member in this structure 328 * is optional as well. 329 */ 330 331 struct dw_mci_drv_data { 332 unsigned long *caps; 333 unsigned int *hold_reg_flag; 334 335 int (*init)(struct dw_mci *host); 336 int (*setup_clock)(struct dw_mci *host); 337 void (*prepare_command)(struct dw_mci *host, u32 *cmdr); 338 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 339 int (*parse_dt)(struct dw_mci *host); 340 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode, struct dw_mci_tuning_data *tuning_data); 341 }; 342 343 /* Variations in Rockchip specific dw-mshc controller */ 344 enum dw_mci_rockchip_type { 345 DW_MCI_TYPE_RK3188, 346 DW_MCI_TYPE_RK3288, 347 DW_MCI_TYPE_RK3036, 348 DW_MCI_TYPE_RK312X, 349 DW_MCI_TYPE_RK3368, 350 DW_MCI_TYPE_RK3228, 351 }; 352 353 #endif /* _DW_MMC_H_ */ 354