1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31
32 #include <video/display_timing.h>
33 #include <video/mipi_display.h>
34 #include <video/of_display_timing.h>
35 #include <video/videomode.h>
36
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_device.h>
39 #include <drm/drm_mipi_dsi.h>
40 #include <drm/drm_panel.h>
41 #include <drm/drm_dsc.h>
42
43 #include "panel-simple.h"
44
45 struct panel_cmd_header {
46 u8 data_type;
47 u8 delay;
48 u8 payload_length;
49 };
50
51 struct panel_cmd_desc {
52 struct panel_cmd_header header;
53 u8 *payload;
54 };
55
56 struct panel_cmd_seq {
57 struct panel_cmd_desc *cmds;
58 unsigned int cmd_cnt;
59 };
60
61 /**
62 * @modes: Pointer to array of fixed modes appropriate for this panel. If
63 * only one mode then this can just be the address of this the mode.
64 * NOTE: cannot be used with "timings" and also if this is specified
65 * then you cannot override the mode in the device tree.
66 * @num_modes: Number of elements in modes array.
67 * @timings: Pointer to array of display timings. NOTE: cannot be used with
68 * "modes" and also these will be used to validate a device tree
69 * override if one is present.
70 * @num_timings: Number of elements in timings array.
71 * @bpc: Bits per color.
72 * @size: Structure containing the physical size of this panel.
73 * @delay: Structure containing various delay values for this panel.
74 * @bus_format: See MEDIA_BUS_FMT_... defines.
75 * @bus_flags: See DRM_BUS_FLAG_... defines.
76 */
77 struct panel_desc {
78 const struct drm_display_mode *modes;
79 unsigned int num_modes;
80 const struct display_timing *timings;
81 unsigned int num_timings;
82
83 unsigned int bpc;
84
85 /**
86 * @width: width (in millimeters) of the panel's active display area
87 * @height: height (in millimeters) of the panel's active display area
88 */
89 struct {
90 unsigned int width;
91 unsigned int height;
92 } size;
93
94 /**
95 * @prepare: the time (in milliseconds) that it takes for the panel to
96 * become ready and start receiving video data
97 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
98 * Plug Detect isn't used.
99 * @enable: the time (in milliseconds) that it takes for the panel to
100 * display the first valid frame after starting to receive
101 * video data
102 * @disable: the time (in milliseconds) that it takes for the panel to
103 * turn the display off (no content is visible)
104 * @unprepare: the time (in milliseconds) that it takes for the panel
105 * to power itself down completely
106 * @reset: the time (in milliseconds) that it takes for the panel
107 * to reset itself completely
108 * @init: the time (in milliseconds) that it takes for the panel to
109 * send init command sequence after reset deassert
110 */
111 struct {
112 unsigned int prepare;
113 unsigned int hpd_absent_delay;
114 unsigned int enable;
115 unsigned int disable;
116 unsigned int unprepare;
117 unsigned int reset;
118 unsigned int init;
119 } delay;
120
121 u32 bus_format;
122 u32 bus_flags;
123 int connector_type;
124
125 struct panel_cmd_seq *init_seq;
126 struct panel_cmd_seq *exit_seq;
127 };
128
129 struct panel_simple {
130 struct drm_panel base;
131 struct mipi_dsi_device *dsi;
132 bool prepared;
133 bool enabled;
134 bool power_invert;
135 bool no_hpd;
136
137 const struct panel_desc *desc;
138
139 struct regulator *supply;
140 struct i2c_adapter *ddc;
141
142 struct gpio_desc *enable_gpio;
143 struct gpio_desc *reset_gpio;
144 struct gpio_desc *hpd_gpio;
145
146 struct drm_display_mode override_mode;
147
148 struct drm_dsc_picture_parameter_set *pps;
149 enum drm_panel_orientation orientation;
150 };
151
to_panel_simple(struct drm_panel *panel)152 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
153 {
154 return container_of(panel, struct panel_simple, base);
155 }
156
panel_simple_parse_cmd_seq(struct device *dev, const u8 *data, int length, struct panel_cmd_seq *seq)157 static int panel_simple_parse_cmd_seq(struct device *dev, const u8 *data, int length, struct panel_cmd_seq *seq)
158 {
159 struct panel_cmd_header *header;
160 struct panel_cmd_desc *desc;
161 char *buf, *d;
162 unsigned int i, cnt, len;
163
164 if (!seq) {
165 return -EINVAL;
166 }
167
168 buf = devm_kmemdup(dev, data, length, GFP_KERNEL);
169 if (!buf) {
170 return -ENOMEM;
171 }
172
173 d = buf;
174 len = length;
175 cnt = 0;
176 while (len > sizeof(*header)) {
177 header = (struct panel_cmd_header *)d;
178
179 d += sizeof(*header);
180 len -= sizeof(*header);
181
182 if (header->payload_length > len) {
183 return -EINVAL;
184 }
185
186 d += header->payload_length;
187 len -= header->payload_length;
188 cnt++;
189 }
190
191 if (len) {
192 return -EINVAL;
193 }
194
195 seq->cmd_cnt = cnt;
196 seq->cmds = devm_kcalloc(dev, cnt, sizeof(*desc), GFP_KERNEL);
197 if (!seq->cmds) {
198 return -ENOMEM;
199 }
200
201 d = buf;
202 len = length;
203 for (i = 0; i < cnt; i++) {
204 header = (struct panel_cmd_header *)d;
205 len -= sizeof(*header);
206 d += sizeof(*header);
207
208 desc = &seq->cmds[i];
209 desc->header = *header;
210 desc->payload = d;
211
212 d += header->payload_length;
213 len -= header->payload_length;
214 }
215
216 return 0;
217 }
218
panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel, struct panel_cmd_seq *seq)219 static int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel, struct panel_cmd_seq *seq)
220 {
221 struct device *dev = panel->base.dev;
222 struct mipi_dsi_device *dsi = panel->dsi;
223 unsigned int i;
224 int err;
225
226 if (!IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
227 return -EINVAL;
228 }
229 if (!seq) {
230 return -EINVAL;
231 }
232
233 for (i = 0; i < seq->cmd_cnt; i++) {
234 struct panel_cmd_desc *cmd = &seq->cmds[i];
235
236 switch (cmd->header.data_type) {
237 case MIPI_DSI_COMPRESSION_MODE:
238 err = mipi_dsi_compression_mode(dsi, cmd->payload[0]);
239 break;
240 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
241 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
242 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
243 case MIPI_DSI_GENERIC_LONG_WRITE:
244 err = mipi_dsi_generic_write(dsi, cmd->payload, cmd->header.payload_length);
245 break;
246 case MIPI_DSI_DCS_SHORT_WRITE:
247 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
248 case MIPI_DSI_DCS_LONG_WRITE:
249 err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload, cmd->header.payload_length);
250 break;
251 case MIPI_DSI_PICTURE_PARAMETER_SET:
252 if (!panel->pps) {
253 panel->pps = devm_kzalloc(dev, sizeof(*panel->pps), GFP_KERNEL);
254 if (!panel->pps) {
255 return -ENOMEM;
256 }
257
258 memcpy(panel->pps, cmd->payload, cmd->header.payload_length);
259 }
260
261 err = mipi_dsi_picture_parameter_set(dsi, panel->pps);
262 break;
263 default:
264 return -EINVAL;
265 }
266
267 if (err < 0) {
268 dev_err(dev, "failed to write dcs cmd: %d\n", err);
269 }
270
271 if (cmd->header.delay) {
272 msleep(cmd->header.delay);
273 }
274 }
275
276 return 0;
277 }
278
panel_simple_get_timings_modes(struct panel_simple *panel, struct drm_connector *connector)279 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, struct drm_connector *connector)
280 {
281 struct drm_display_mode *mode;
282 unsigned int i, num = 0;
283
284 for (i = 0; i < panel->desc->num_timings; i++) {
285 const struct display_timing *dt = &panel->desc->timings[i];
286 struct videomode vm;
287
288 videomode_from_timing(dt, &vm);
289 mode = drm_mode_create(connector->dev);
290 if (!mode) {
291 dev_err(panel->base.dev, "failed to add mode %ux%u\n", dt->hactive.typ, dt->vactive.typ);
292 continue;
293 }
294
295 drm_display_mode_from_videomode(&vm, mode);
296
297 mode->type |= DRM_MODE_TYPE_DRIVER;
298
299 if (panel->desc->num_timings == 1) {
300 mode->type |= DRM_MODE_TYPE_PREFERRED;
301 }
302
303 drm_mode_probed_add(connector, mode);
304 num++;
305 }
306
307 return num;
308 }
309
panel_simple_get_display_modes(struct panel_simple *panel, struct drm_connector *connector)310 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, struct drm_connector *connector)
311 {
312 struct drm_display_mode *mode;
313 unsigned int i, num = 0;
314
315 for (i = 0; i < panel->desc->num_modes; i++) {
316 const struct drm_display_mode *m = &panel->desc->modes[i];
317
318 mode = drm_mode_duplicate(connector->dev, m);
319 if (!mode) {
320 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
321 continue;
322 }
323
324 mode->type |= DRM_MODE_TYPE_DRIVER;
325
326 if (panel->desc->num_modes == 1) {
327 mode->type |= DRM_MODE_TYPE_PREFERRED;
328 }
329
330 drm_mode_set_name(mode);
331
332 drm_mode_probed_add(connector, mode);
333 num++;
334 }
335
336 return num;
337 }
338
panel_simple_get_non_edid_modes(struct panel_simple *panel, struct drm_connector *connector)339 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, struct drm_connector *connector)
340 {
341 struct drm_display_mode *mode;
342 bool has_override = panel->override_mode.type;
343 unsigned int num = 0;
344
345 if (!panel->desc) {
346 return 0;
347 }
348
349 if (has_override) {
350 mode = drm_mode_duplicate(connector->dev, &panel->override_mode);
351 if (mode) {
352 drm_mode_probed_add(connector, mode);
353 num = 1;
354 } else {
355 dev_err(panel->base.dev, "failed to add override mode\n");
356 }
357 }
358
359 /* Only add timings if override was not there or failed to validate */
360 if (num == 0 && panel->desc->num_timings) {
361 num = panel_simple_get_timings_modes(panel, connector);
362 }
363
364 /*
365 * Only add fixed modes if timings/override added no mode.
366 *
367 * We should only ever have either the display timings specified
368 * or a fixed mode. Anything else is rather bogus.
369 */
370 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
371 if (num == 0) {
372 num = panel_simple_get_display_modes(panel, connector);
373 }
374
375 if (panel->desc->bpc) {
376 connector->display_info.bpc = panel->desc->bpc;
377 }
378 if (panel->desc->size.width) {
379 connector->display_info.width_mm = panel->desc->size.width;
380 }
381 if (panel->desc->size.height) {
382 connector->display_info.height_mm = panel->desc->size.height;
383 }
384 if (panel->desc->bus_format) {
385 drm_display_info_set_bus_formats(&connector->display_info, &panel->desc->bus_format, 1);
386 }
387 if (panel->desc->bus_flags) {
388 connector->display_info.bus_flags = panel->desc->bus_flags;
389 }
390
391 return num;
392 }
393
panel_simple_regulator_enable(struct panel_simple *p)394 static int panel_simple_regulator_enable(struct panel_simple *p)
395 {
396 int err;
397
398 if (p->power_invert) {
399 if (regulator_is_enabled(p->supply) > 0) {
400 regulator_disable(p->supply);
401 }
402 } else {
403 err = regulator_enable(p->supply);
404 if (err < 0) {
405 return err;
406 }
407 }
408
409 return 0;
410 }
411
panel_simple_regulator_disable(struct panel_simple *p)412 static int panel_simple_regulator_disable(struct panel_simple *p)
413 {
414 int err;
415
416 if (p->power_invert) {
417 if (!regulator_is_enabled(p->supply)) {
418 err = regulator_enable(p->supply);
419 if (err < 0) {
420 return err;
421 }
422 }
423 } else {
424 regulator_disable(p->supply);
425 }
426
427 return 0;
428 }
429
panel_simple_loader_protect(struct drm_panel *panel)430 int panel_simple_loader_protect(struct drm_panel *panel)
431 {
432 struct panel_simple *p = to_panel_simple(panel);
433 int err;
434
435 err = panel_simple_regulator_enable(p);
436 if (err < 0) {
437 dev_err(panel->dev, "failed to enable supply: %d\n", err);
438 return err;
439 }
440
441 p->prepared = true;
442 p->enabled = true;
443
444 return 0;
445 }
446 EXPORT_SYMBOL(panel_simple_loader_protect);
447
panel_simple_disable(struct drm_panel *panel)448 static int panel_simple_disable(struct drm_panel *panel)
449 {
450 struct panel_simple *p = to_panel_simple(panel);
451
452 if (!p->enabled) {
453 return 0;
454 }
455
456 if (p->desc->delay.disable) {
457 msleep(p->desc->delay.disable);
458 }
459
460 p->enabled = false;
461
462 return 0;
463 }
464
panel_simple_unprepare(struct drm_panel *panel)465 static int panel_simple_unprepare(struct drm_panel *panel)
466 {
467 struct panel_simple *p = to_panel_simple(panel);
468
469 if (!p->prepared) {
470 return 0;
471 }
472
473 if (p->desc->exit_seq) {
474 if (p->dsi) {
475 panel_simple_xfer_dsi_cmd_seq(p, p->desc->exit_seq);
476 }
477 }
478
479 gpiod_direction_output(p->reset_gpio, 1);
480 gpiod_direction_output(p->enable_gpio, 0);
481
482 panel_simple_regulator_disable(p);
483
484 if (p->desc->delay.unprepare) {
485 msleep(p->desc->delay.unprepare);
486 }
487
488 p->prepared = false;
489
490 return 0;
491 }
492
panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p, bool from_probe)493 static int panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p, bool from_probe)
494 {
495 int err;
496
497 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
498 if (IS_ERR(p->hpd_gpio)) {
499 err = PTR_ERR(p->hpd_gpio);
500 /*
501 * If we're called from probe we won't consider '-EPROBE_DEFER'
502 * to be an error--we'll leave the error code in "hpd_gpio".
503 * When we try to use it we'll try again. This allows for
504 * circular dependencies where the component providing the
505 * hpd gpio needs the panel to init before probing.
506 */
507 if (err != -EPROBE_DEFER || !from_probe) {
508 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
509 return err;
510 }
511 }
512
513 return 0;
514 }
515
panel_simple_prepare(struct drm_panel *panel)516 static int panel_simple_prepare(struct drm_panel *panel)
517 {
518 struct panel_simple *p = to_panel_simple(panel);
519 unsigned int delay;
520 int err;
521 int hpd_asserted;
522
523 if (p->prepared) {
524 return 0;
525 }
526
527 err = panel_simple_regulator_enable(p);
528 if (err < 0) {
529 dev_err(panel->dev, "failed to enable supply: %d\n", err);
530 return err;
531 }
532
533 gpiod_direction_output(p->enable_gpio, 1);
534
535 if (p->desc->delay.reset) {
536 msleep(p->desc->delay.prepare);
537 }
538
539 gpiod_direction_output(p->reset_gpio, 1);
540
541 if (p->desc->delay.reset) {
542 msleep(p->desc->delay.reset);
543 }
544
545 gpiod_direction_output(p->reset_gpio, 0);
546
547 delay = p->desc->delay.prepare;
548 if (p->no_hpd) {
549 delay += p->desc->delay.hpd_absent_delay;
550 }
551 if (delay) {
552 msleep(delay);
553 }
554
555 if (p->hpd_gpio) {
556 if (IS_ERR(p->hpd_gpio)) {
557 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
558 if (err) {
559 return err;
560 }
561 }
562
563 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, hpd_asserted, hpd_asserted, 0x3e8, 0x1e8480);
564 if (hpd_asserted < 0) {
565 err = hpd_asserted;
566 }
567
568 if (err) {
569 dev_err(panel->dev, "error waiting for hpd GPIO: %d\n", err);
570 return err;
571 }
572 }
573
574 if (p->desc->init_seq) {
575 if (p->dsi) {
576 panel_simple_xfer_dsi_cmd_seq(p, p->desc->init_seq);
577 }
578 }
579
580 if (p->desc->delay.init) {
581 msleep(p->desc->delay.init);
582 }
583
584 p->prepared = true;
585
586 return 0;
587 }
588
panel_simple_enable(struct drm_panel *panel)589 static int panel_simple_enable(struct drm_panel *panel)
590 {
591 struct panel_simple *p = to_panel_simple(panel);
592
593 if (p->enabled) {
594 return 0;
595 }
596
597 if (p->desc->delay.enable) {
598 msleep(p->desc->delay.enable);
599 }
600
601 p->enabled = true;
602
603 return 0;
604 }
605
panel_simple_get_modes(struct drm_panel *panel, struct drm_connector *connector)606 static int panel_simple_get_modes(struct drm_panel *panel, struct drm_connector *connector)
607 {
608 struct panel_simple *p = to_panel_simple(panel);
609 int num = 0;
610
611 /* probe EDID if a DDC bus is available */
612 if (p->ddc) {
613 struct edid *edid = drm_get_edid(connector, p->ddc);
614
615 drm_connector_update_edid_property(connector, edid);
616 if (edid) {
617 num += drm_add_edid_modes(connector, edid);
618 kfree(edid);
619 }
620 }
621
622 /* add hard-coded panel modes */
623 num += panel_simple_get_non_edid_modes(p, connector);
624
625 /* set up connector's "panel orientation" property */
626 drm_connector_set_panel_orientation(connector, p->orientation);
627
628 return num;
629 }
630
panel_simple_get_timings(struct drm_panel *panel, unsigned int num_timings, struct display_timing *timings)631 static int panel_simple_get_timings(struct drm_panel *panel, unsigned int num_timings, struct display_timing *timings)
632 {
633 struct panel_simple *p = to_panel_simple(panel);
634 unsigned int i;
635
636 if (p->desc->num_timings < num_timings) {
637 num_timings = p->desc->num_timings;
638 }
639
640 if (timings) {
641 for (i = 0; i < num_timings; i++) {
642 timings[i] = p->desc->timings[i];
643 }
644 }
645
646 return p->desc->num_timings;
647 }
648
649 static const struct drm_panel_funcs panel_simple_funcs = {
650 .disable = panel_simple_disable,
651 .unprepare = panel_simple_unprepare,
652 .prepare = panel_simple_prepare,
653 .enable = panel_simple_enable,
654 .get_modes = panel_simple_get_modes,
655 .get_timings = panel_simple_get_timings,
656 };
657
658 static struct panel_desc panel_dpi;
659
panel_dpi_probe(struct device *dev, struct panel_simple *panel)660 static int panel_dpi_probe(struct device *dev, struct panel_simple *panel)
661 {
662 struct display_timing *timing;
663 const struct device_node *np;
664 struct panel_desc *desc;
665 unsigned int bus_flags;
666 struct videomode vm;
667 int ret;
668
669 np = dev->of_node;
670 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
671 if (!desc) {
672 return -ENOMEM;
673 }
674
675 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
676 if (!timing) {
677 return -ENOMEM;
678 }
679
680 ret = of_get_display_timing(np, "panel-timing", timing);
681 if (ret < 0) {
682 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", np);
683 return ret;
684 }
685
686 desc->timings = timing;
687 desc->num_timings = 1;
688
689 of_property_read_u32(np, "width-mm", &desc->size.width);
690 of_property_read_u32(np, "height-mm", &desc->size.height);
691
692 /* Extract bus_flags from display_timing */
693 bus_flags = 0;
694 vm.flags = timing->flags;
695 drm_bus_flags_from_videomode(&vm, &bus_flags);
696 desc->bus_flags = bus_flags;
697
698 /* We do not know the connector for the DT node, so guess it */
699 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
700
701 panel->desc = desc;
702
703 return 0;
704 }
705
706 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
707 ((to_check)->field.typ >= (bounds)->field.min && (to_check)->field.typ <= (bounds)->field.max)
panel_simple_parse_panel_timing_node(struct device *dev, struct panel_simple *panel, const struct display_timing *ot)708 static void panel_simple_parse_panel_timing_node(struct device *dev, struct panel_simple *panel,
709 const struct display_timing *ot)
710 {
711 const struct panel_desc *desc = panel->desc;
712 struct videomode vm;
713 unsigned int i;
714
715 if (WARN_ON(desc->num_modes)) {
716 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
717 return;
718 }
719 if (WARN_ON(!desc->num_timings)) {
720 dev_err(dev, "Reject override mode: no timings specified\n");
721 return;
722 }
723
724 for (i = 0; i < panel->desc->num_timings; i++) {
725 const struct display_timing *dt = &panel->desc->timings[i];
726
727 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
728 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
729 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
730 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) {
731 continue;
732 }
733
734 if (ot->flags != dt->flags) {
735 continue;
736 }
737
738 videomode_from_timing(ot, &vm);
739 drm_display_mode_from_videomode(&vm, &panel->override_mode);
740 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
741 break;
742 }
743
744 if (WARN_ON(!panel->override_mode.type)) {
745 dev_err(dev, "Reject override mode: No display_timing found\n");
746 }
747 }
748
dcs_bl_update_status(struct backlight_device *bl)749 static int dcs_bl_update_status(struct backlight_device *bl)
750 {
751 struct panel_simple *p = bl_get_data(bl);
752 struct mipi_dsi_device *dsi = p->dsi;
753 int ret;
754
755 if (!p->prepared) {
756 return 0;
757 }
758
759 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
760
761 ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness);
762 if (ret < 0) {
763 return ret;
764 }
765
766 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
767
768 return 0;
769 }
770
dcs_bl_get_brightness(struct backlight_device *bl)771 static int dcs_bl_get_brightness(struct backlight_device *bl)
772 {
773 struct panel_simple *p = bl_get_data(bl);
774 struct mipi_dsi_device *dsi = p->dsi;
775 u16 brightness = bl->props.brightness;
776 int ret;
777
778 if (!p->prepared) {
779 return 0;
780 }
781
782 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
783
784 ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
785 if (ret < 0) {
786 return ret;
787 }
788
789 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
790
791 return brightness & 0xff;
792 }
793
794 static const struct backlight_ops dcs_bl_ops = {
795 .update_status = dcs_bl_update_status,
796 .get_brightness = dcs_bl_get_brightness,
797 };
798
panel_simple_probe(struct device *dev, const struct panel_desc *desc)799 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
800 {
801 struct panel_simple *panel;
802 struct display_timing dt;
803 struct device_node *ddc;
804 int connector_type;
805 u32 bus_flags;
806 int err;
807
808 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
809 if (!panel) {
810 return -ENOMEM;
811 }
812
813 panel->enabled = false;
814 panel->prepared = false;
815 panel->desc = desc;
816
817 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
818 if (!panel->no_hpd) {
819 err = panel_simple_get_hpd_gpio(dev, panel, true);
820 if (err) {
821 return err;
822 }
823 }
824
825 panel->supply = devm_regulator_get(dev, "power");
826 if (IS_ERR(panel->supply)) {
827 return PTR_ERR(panel->supply);
828 }
829
830 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_ASIS);
831 if (IS_ERR(panel->enable_gpio)) {
832 err = PTR_ERR(panel->enable_gpio);
833 if (err != -EPROBE_DEFER) {
834 dev_err(dev, "failed to get enable GPIO: %d\n", err);
835 }
836 return err;
837 }
838
839 panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
840 if (IS_ERR(panel->reset_gpio)) {
841 err = PTR_ERR(panel->reset_gpio);
842 if (err != -EPROBE_DEFER) {
843 dev_err(dev, "failed to get reset GPIO: %d\n", err);
844 }
845 return err;
846 }
847
848 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
849 if (err) {
850 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
851 return err;
852 }
853
854 panel->power_invert = of_property_read_bool(dev->of_node, "power-invert");
855
856 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
857 if (ddc) {
858 panel->ddc = of_find_i2c_adapter_by_node(ddc);
859 of_node_put(ddc);
860
861 if (!panel->ddc) {
862 return -EPROBE_DEFER;
863 }
864 }
865
866 if (desc == &panel_dpi) {
867 /* Handle the generic panel-dpi binding */
868 err = panel_dpi_probe(dev, panel);
869 if (err) {
870 goto free_ddc;
871 }
872 } else {
873 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) {
874 panel_simple_parse_panel_timing_node(dev, panel, &dt);
875 }
876 }
877
878 connector_type = desc->connector_type;
879 /* Catch common mistakes for panels. */
880 switch (connector_type) {
881 case 0:
882 dev_dbg(dev, "Specify missing connector_type\n");
883 connector_type = DRM_MODE_CONNECTOR_DPI;
884 break;
885 case DRM_MODE_CONNECTOR_LVDS:
886 WARN_ON(desc->bus_flags & ~(DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_DATA_MSB_TO_LSB |
887 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
888 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
889 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
890 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
891 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && desc->bpc != 0x6);
892 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
893 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
894 desc->bpc != 0x8);
895 break;
896 case DRM_MODE_CONNECTOR_eDP:
897 if (desc->bus_format == 0) {
898 dev_warn(dev, "Specify missing bus_format\n");
899 }
900 if (desc->bpc != 0x6 && desc->bpc != 0x8) {
901 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
902 }
903 break;
904 case DRM_MODE_CONNECTOR_DSI:
905 if (desc->bpc != 0x6 && desc->bpc != 0x8) {
906 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
907 }
908 break;
909 case DRM_MODE_CONNECTOR_DPI:
910 bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
911 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | DRM_BUS_FLAG_DATA_MSB_TO_LSB |
912 DRM_BUS_FLAG_DATA_LSB_TO_MSB | DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
913 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
914 if (desc->bus_flags & ~bus_flags) {
915 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
916 }
917 if (!(desc->bus_flags & bus_flags)) {
918 dev_warn(dev, "Specify missing bus_flags\n");
919 }
920 if (desc->bus_format == 0) {
921 dev_warn(dev, "Specify missing bus_format\n");
922 }
923 if (desc->bpc != 0x6 && desc->bpc != 0x8) {
924 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
925 }
926 break;
927 default:
928 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
929 connector_type = DRM_MODE_CONNECTOR_DPI;
930 break;
931 }
932
933 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
934
935 err = drm_panel_of_backlight(&panel->base);
936 if (err) {
937 goto free_ddc;
938 }
939
940 drm_panel_add(&panel->base);
941
942 dev_set_drvdata(dev, panel);
943
944 return 0;
945
946 free_ddc:
947 if (panel->ddc) {
948 put_device(&panel->ddc->dev);
949 }
950
951 return err;
952 }
953
panel_simple_remove(struct device *dev)954 static int panel_simple_remove(struct device *dev)
955 {
956 struct panel_simple *panel = dev_get_drvdata(dev);
957
958 drm_panel_remove(&panel->base);
959 drm_panel_disable(&panel->base);
960 drm_panel_unprepare(&panel->base);
961
962 if (panel->ddc) {
963 put_device(&panel->ddc->dev);
964 }
965
966 return 0;
967 }
968
panel_simple_shutdown(struct device *dev)969 static void panel_simple_shutdown(struct device *dev)
970 {
971 struct panel_simple *panel = dev_get_drvdata(dev);
972
973 drm_panel_disable(&panel->base);
974 drm_panel_unprepare(&panel->base);
975 }
976
977 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
978 .clock = 71100,
979 .hdisplay = 1280,
980 .hsync_start = 1280 + 40,
981 .hsync_end = 1280 + 40 + 80,
982 .htotal = 1280 + 40 + 80 + 40,
983 .vdisplay = 800,
984 .vsync_start = 800 + 3,
985 .vsync_end = 800 + 3 + 10,
986 .vtotal = 800 + 3 + 10 + 10,
987 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
988 };
989
990 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
991 .modes = &ire_am_1280800n3tzqw_t00h_mode,
992 .num_modes = 1,
993 .bpc = 8,
994 .size =
995 {
996 .width = 217,
997 .height = 136,
998 },
999 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1000 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1001 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1002 };
1003
1004 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
1005 .clock = 9000,
1006 .hdisplay = 480,
1007 .hsync_start = 480 + 2,
1008 .hsync_end = 480 + 2 + 41,
1009 .htotal = 480 + 2 + 41 + 2,
1010 .vdisplay = 272,
1011 .vsync_start = 272 + 2,
1012 .vsync_end = 272 + 2 + 10,
1013 .vtotal = 272 + 2 + 10 + 2,
1014 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1015 };
1016
1017 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
1018 .modes = &ire_am_480272h3tmqw_t01h_mode,
1019 .num_modes = 1,
1020 .bpc = 8,
1021 .size =
1022 {
1023 .width = 105,
1024 .height = 67,
1025 },
1026 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1027 };
1028
1029 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
1030 .clock = 33333,
1031 .hdisplay = 800,
1032 .hsync_start = 800 + 0,
1033 .hsync_end = 800 + 0 + 255,
1034 .htotal = 800 + 0 + 255 + 0,
1035 .vdisplay = 480,
1036 .vsync_start = 480 + 2,
1037 .vsync_end = 480 + 2 + 45,
1038 .vtotal = 480 + 2 + 45 + 0,
1039 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1040 };
1041
1042 static const struct panel_desc ampire_am800480r3tmqwa1h = {
1043 .modes = &ire_am800480r3tmqwa1h_mode,
1044 .num_modes = 1,
1045 .bpc = 6,
1046 .size =
1047 {
1048 .width = 152,
1049 .height = 91,
1050 },
1051 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1052 };
1053
1054 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
1055 .pixelclock = {26400000, 33300000, 46800000},
1056 .hactive = {800, 800, 800},
1057 .hfront_porch = {16, 210, 354},
1058 .hback_porch = {45, 36, 6},
1059 .hsync_len = {1, 10, 40},
1060 .vactive = {480, 480, 480},
1061 .vfront_porch = {7, 22, 147},
1062 .vback_porch = {22, 13, 3},
1063 .vsync_len = {1, 10, 20},
1064 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE};
1065
1066 static const struct panel_desc armadeus_st0700_adapt = {
1067 .timings = &santek_st0700i5y_rbslw_f_timing,
1068 .num_timings = 1,
1069 .bpc = 6,
1070 .size =
1071 {
1072 .width = 154,
1073 .height = 86,
1074 },
1075 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1076 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1077 };
1078
1079 static const struct drm_display_mode auo_b101aw03_mode = {
1080 .clock = 51450,
1081 .hdisplay = 1024,
1082 .hsync_start = 1024 + 156,
1083 .hsync_end = 1024 + 156 + 8,
1084 .htotal = 1024 + 156 + 8 + 156,
1085 .vdisplay = 600,
1086 .vsync_start = 600 + 16,
1087 .vsync_end = 600 + 16 + 6,
1088 .vtotal = 600 + 16 + 6 + 16,
1089 };
1090
1091 static const struct panel_desc auo_b101aw03 = {
1092 .modes = &auo_b101aw03_mode,
1093 .num_modes = 1,
1094 .bpc = 6,
1095 .size =
1096 {
1097 .width = 223,
1098 .height = 125,
1099 },
1100 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1101 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1102 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1103 };
1104
1105 static const struct display_timing auo_b101ean01_timing = {
1106 .pixelclock = {65300000, 72500000, 75000000},
1107 .hactive = {1280, 1280, 1280},
1108 .hfront_porch = {18, 119, 119},
1109 .hback_porch = {21, 21, 21},
1110 .hsync_len = {32, 32, 32},
1111 .vactive = {800, 800, 800},
1112 .vfront_porch = {4, 4, 4},
1113 .vback_porch = {8, 8, 8},
1114 .vsync_len = {18, 20, 20},
1115 };
1116
1117 static const struct panel_desc auo_b101ean01 = {
1118 .timings = &auo_b101ean01_timing,
1119 .num_timings = 1,
1120 .bpc = 6,
1121 .size =
1122 {
1123 .width = 217,
1124 .height = 136,
1125 },
1126 };
1127
1128 static const struct drm_display_mode auo_b101xtn01_mode = {
1129 .clock = 72000,
1130 .hdisplay = 1366,
1131 .hsync_start = 1366 + 20,
1132 .hsync_end = 1366 + 20 + 70,
1133 .htotal = 1366 + 20 + 70,
1134 .vdisplay = 768,
1135 .vsync_start = 768 + 14,
1136 .vsync_end = 768 + 14 + 42,
1137 .vtotal = 768 + 14 + 42,
1138 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1139 };
1140
1141 static const struct panel_desc auo_b101xtn01 = {
1142 .modes = &auo_b101xtn01_mode,
1143 .num_modes = 1,
1144 .bpc = 6,
1145 .size =
1146 {
1147 .width = 223,
1148 .height = 125,
1149 },
1150 };
1151
1152 static const struct drm_display_mode auo_b116xak01_mode = {
1153 .clock = 69300,
1154 .hdisplay = 1366,
1155 .hsync_start = 1366 + 48,
1156 .hsync_end = 1366 + 48 + 32,
1157 .htotal = 1366 + 48 + 32 + 10,
1158 .vdisplay = 768,
1159 .vsync_start = 768 + 4,
1160 .vsync_end = 768 + 4 + 6,
1161 .vtotal = 768 + 4 + 6 + 15,
1162 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1163 };
1164
1165 static const struct panel_desc auo_b116xak01 = {
1166 .modes = &auo_b116xak01_mode,
1167 .num_modes = 1,
1168 .bpc = 6,
1169 .size =
1170 {
1171 .width = 256,
1172 .height = 144,
1173 },
1174 .delay =
1175 {
1176 .hpd_absent_delay = 200,
1177 },
1178 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1179 .connector_type = DRM_MODE_CONNECTOR_eDP,
1180 };
1181
1182 static const struct drm_display_mode auo_b116xw03_mode = {
1183 .clock = 70589,
1184 .hdisplay = 1366,
1185 .hsync_start = 1366 + 40,
1186 .hsync_end = 1366 + 40 + 40,
1187 .htotal = 1366 + 40 + 40 + 32,
1188 .vdisplay = 768,
1189 .vsync_start = 768 + 10,
1190 .vsync_end = 768 + 10 + 12,
1191 .vtotal = 768 + 10 + 12 + 6,
1192 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1193 };
1194
1195 static const struct panel_desc auo_b116xw03 = {
1196 .modes = &auo_b116xw03_mode,
1197 .num_modes = 1,
1198 .bpc = 6,
1199 .size =
1200 {
1201 .width = 256,
1202 .height = 144,
1203 },
1204 .delay =
1205 {
1206 .enable = 400,
1207 },
1208 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
1209 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1210 .connector_type = DRM_MODE_CONNECTOR_eDP,
1211 };
1212
1213 static const struct drm_display_mode auo_b133xtn01_mode = {
1214 .clock = 69500,
1215 .hdisplay = 1366,
1216 .hsync_start = 1366 + 48,
1217 .hsync_end = 1366 + 48 + 32,
1218 .htotal = 1366 + 48 + 32 + 20,
1219 .vdisplay = 768,
1220 .vsync_start = 768 + 3,
1221 .vsync_end = 768 + 3 + 6,
1222 .vtotal = 768 + 3 + 6 + 13,
1223 };
1224
1225 static const struct panel_desc auo_b133xtn01 = {
1226 .modes = &auo_b133xtn01_mode,
1227 .num_modes = 1,
1228 .bpc = 6,
1229 .size =
1230 {
1231 .width = 293,
1232 .height = 165,
1233 },
1234 };
1235
1236 static const struct drm_display_mode auo_b133htn01_mode = {
1237 .clock = 150660,
1238 .hdisplay = 1920,
1239 .hsync_start = 1920 + 172,
1240 .hsync_end = 1920 + 172 + 80,
1241 .htotal = 1920 + 172 + 80 + 60,
1242 .vdisplay = 1080,
1243 .vsync_start = 1080 + 25,
1244 .vsync_end = 1080 + 25 + 10,
1245 .vtotal = 1080 + 25 + 10 + 10,
1246 };
1247
1248 static const struct panel_desc auo_b133htn01 = {
1249 .modes = &auo_b133htn01_mode,
1250 .num_modes = 1,
1251 .bpc = 6,
1252 .size =
1253 {
1254 .width = 293,
1255 .height = 165,
1256 },
1257 .delay =
1258 {
1259 .prepare = 105,
1260 .enable = 20,
1261 .unprepare = 50,
1262 },
1263 };
1264
1265 static const struct display_timing auo_g070vvn01_timings = {
1266 .pixelclock = {33300000, 34209000, 45000000},
1267 .hactive = {800, 800, 800},
1268 .hfront_porch = {20, 40, 200},
1269 .hback_porch = {87, 40, 1},
1270 .hsync_len = {1, 48, 87},
1271 .vactive = {480, 480, 480},
1272 .vfront_porch = {5, 13, 200},
1273 .vback_porch = {31, 31, 29},
1274 .vsync_len = {1, 1, 3},
1275 };
1276
1277 static const struct panel_desc auo_g070vvn01 = {
1278 .timings = &auo_g070vvn01_timings,
1279 .num_timings = 1,
1280 .bpc = 8,
1281 .size =
1282 {
1283 .width = 152,
1284 .height = 91,
1285 },
1286 .delay =
1287 {
1288 .prepare = 200,
1289 .enable = 50,
1290 .disable = 50,
1291 .unprepare = 1000,
1292 },
1293 };
1294
1295 static const struct drm_display_mode auo_g101evn010_mode = {
1296 .clock = 68930,
1297 .hdisplay = 1280,
1298 .hsync_start = 1280 + 82,
1299 .hsync_end = 1280 + 82 + 2,
1300 .htotal = 1280 + 82 + 2 + 84,
1301 .vdisplay = 800,
1302 .vsync_start = 800 + 8,
1303 .vsync_end = 800 + 8 + 2,
1304 .vtotal = 800 + 8 + 2 + 6,
1305 };
1306
1307 static const struct panel_desc auo_g101evn010 = {
1308 .modes = &auo_g101evn010_mode,
1309 .num_modes = 1,
1310 .bpc = 6,
1311 .size =
1312 {
1313 .width = 216,
1314 .height = 135,
1315 },
1316 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1317 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1318 };
1319
1320 static const struct drm_display_mode auo_g104sn02_mode = {
1321 .clock = 40000,
1322 .hdisplay = 800,
1323 .hsync_start = 800 + 40,
1324 .hsync_end = 800 + 40 + 216,
1325 .htotal = 800 + 40 + 216 + 128,
1326 .vdisplay = 600,
1327 .vsync_start = 600 + 10,
1328 .vsync_end = 600 + 10 + 35,
1329 .vtotal = 600 + 10 + 35 + 2,
1330 };
1331
1332 static const struct panel_desc auo_g104sn02 = {
1333 .modes = &auo_g104sn02_mode,
1334 .num_modes = 1,
1335 .bpc = 8,
1336 .size =
1337 {
1338 .width = 211,
1339 .height = 158,
1340 },
1341 };
1342
1343 static const struct drm_display_mode auo_g121ean01_mode = {
1344 .clock = 66700,
1345 .hdisplay = 1280,
1346 .hsync_start = 1280 + 58,
1347 .hsync_end = 1280 + 58 + 8,
1348 .htotal = 1280 + 58 + 8 + 70,
1349 .vdisplay = 800,
1350 .vsync_start = 800 + 6,
1351 .vsync_end = 800 + 6 + 4,
1352 .vtotal = 800 + 6 + 4 + 10,
1353 };
1354
1355 static const struct panel_desc auo_g121ean01 = {
1356 .modes = &auo_g121ean01_mode,
1357 .num_modes = 1,
1358 .bpc = 8,
1359 .size =
1360 {
1361 .width = 261,
1362 .height = 163,
1363 },
1364 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1365 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1366 };
1367
1368 static const struct display_timing auo_g133han01_timings = {
1369 .pixelclock = {134000000, 141200000, 149000000},
1370 .hactive = {1920, 1920, 1920},
1371 .hfront_porch = {39, 58, 77},
1372 .hback_porch = {59, 88, 117},
1373 .hsync_len = {28, 42, 56},
1374 .vactive = {1080, 1080, 1080},
1375 .vfront_porch = {3, 8, 11},
1376 .vback_porch = {5, 14, 19},
1377 .vsync_len = {4, 14, 19},
1378 };
1379
1380 static const struct panel_desc auo_g133han01 = {
1381 .timings = &auo_g133han01_timings,
1382 .num_timings = 1,
1383 .bpc = 8,
1384 .size =
1385 {
1386 .width = 293,
1387 .height = 165,
1388 },
1389 .delay =
1390 {
1391 .prepare = 200,
1392 .enable = 50,
1393 .disable = 50,
1394 .unprepare = 1000,
1395 },
1396 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1397 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1398 };
1399
1400 static const struct drm_display_mode auo_g156xtn01_mode = {
1401 .clock = 76000,
1402 .hdisplay = 1366,
1403 .hsync_start = 1366 + 33,
1404 .hsync_end = 1366 + 33 + 67,
1405 .htotal = 1560,
1406 .vdisplay = 768,
1407 .vsync_start = 768 + 4,
1408 .vsync_end = 768 + 4 + 4,
1409 .vtotal = 806,
1410 };
1411
1412 static const struct panel_desc auo_g156xtn01 = {
1413 .modes = &auo_g156xtn01_mode,
1414 .num_modes = 1,
1415 .bpc = 8,
1416 .size =
1417 {
1418 .width = 344,
1419 .height = 194,
1420 },
1421 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1422 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1423 };
1424
1425 static const struct display_timing auo_g185han01_timings = {
1426 .pixelclock = {120000000, 144000000, 175000000},
1427 .hactive = {1920, 1920, 1920},
1428 .hfront_porch = {36, 120, 148},
1429 .hback_porch = {24, 88, 108},
1430 .hsync_len = {20, 48, 64},
1431 .vactive = {1080, 1080, 1080},
1432 .vfront_porch = {6, 10, 40},
1433 .vback_porch = {2, 5, 20},
1434 .vsync_len = {2, 5, 20},
1435 };
1436
1437 static const struct panel_desc auo_g185han01 = {
1438 .timings = &auo_g185han01_timings,
1439 .num_timings = 1,
1440 .bpc = 8,
1441 .size =
1442 {
1443 .width = 409,
1444 .height = 230,
1445 },
1446 .delay =
1447 {
1448 .prepare = 50,
1449 .enable = 200,
1450 .disable = 110,
1451 .unprepare = 1000,
1452 },
1453 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1454 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1455 };
1456
1457 static const struct display_timing auo_g190ean01_timings = {
1458 .pixelclock = {90000000, 108000000, 135000000},
1459 .hactive = {1280, 1280, 1280},
1460 .hfront_porch = {126, 184, 1266},
1461 .hback_porch = {84, 122, 844},
1462 .hsync_len = {70, 102, 704},
1463 .vactive = {1024, 1024, 1024},
1464 .vfront_porch = {4, 26, 76},
1465 .vback_porch = {2, 8, 25},
1466 .vsync_len = {2, 8, 25},
1467 };
1468
1469 static const struct panel_desc auo_g190ean01 = {
1470 .timings = &auo_g190ean01_timings,
1471 .num_timings = 1,
1472 .bpc = 8,
1473 .size =
1474 {
1475 .width = 376,
1476 .height = 301,
1477 },
1478 .delay =
1479 {
1480 .prepare = 50,
1481 .enable = 200,
1482 .disable = 110,
1483 .unprepare = 1000,
1484 },
1485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1486 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1487 };
1488
1489 static const struct display_timing auo_p320hvn03_timings = {
1490 .pixelclock = {106000000, 148500000, 164000000},
1491 .hactive = {1920, 1920, 1920},
1492 .hfront_porch = {25, 50, 130},
1493 .hback_porch = {25, 50, 130},
1494 .hsync_len = {20, 40, 105},
1495 .vactive = {1080, 1080, 1080},
1496 .vfront_porch = {8, 17, 150},
1497 .vback_porch = {8, 17, 150},
1498 .vsync_len = {4, 11, 100},
1499 };
1500
1501 static const struct panel_desc auo_p320hvn03 = {
1502 .timings = &auo_p320hvn03_timings,
1503 .num_timings = 1,
1504 .bpc = 8,
1505 .size =
1506 {
1507 .width = 698,
1508 .height = 393,
1509 },
1510 .delay =
1511 {
1512 .prepare = 1,
1513 .enable = 450,
1514 .unprepare = 500,
1515 },
1516 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1517 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1518 };
1519
1520 static const struct drm_display_mode auo_t215hvn01_mode = {
1521 .clock = 148800,
1522 .hdisplay = 1920,
1523 .hsync_start = 1920 + 88,
1524 .hsync_end = 1920 + 88 + 44,
1525 .htotal = 1920 + 88 + 44 + 148,
1526 .vdisplay = 1080,
1527 .vsync_start = 1080 + 4,
1528 .vsync_end = 1080 + 4 + 5,
1529 .vtotal = 1080 + 4 + 5 + 36,
1530 };
1531
1532 static const struct panel_desc auo_t215hvn01 = {.modes = &auo_t215hvn01_mode,
1533 .num_modes = 1,
1534 .bpc = 8,
1535 .size =
1536 {
1537 .width = 430,
1538 .height = 270,
1539 },
1540 .delay = {
1541 .disable = 5,
1542 .unprepare = 1000,
1543 }};
1544
1545 static const struct drm_display_mode avic_tm070ddh03_mode = {
1546 .clock = 51200,
1547 .hdisplay = 1024,
1548 .hsync_start = 1024 + 160,
1549 .hsync_end = 1024 + 160 + 4,
1550 .htotal = 1024 + 160 + 4 + 156,
1551 .vdisplay = 600,
1552 .vsync_start = 600 + 17,
1553 .vsync_end = 600 + 17 + 1,
1554 .vtotal = 600 + 17 + 1 + 17,
1555 };
1556
1557 static const struct panel_desc avic_tm070ddh03 = {
1558 .modes = &avic_tm070ddh03_mode,
1559 .num_modes = 1,
1560 .bpc = 8,
1561 .size =
1562 {
1563 .width = 154,
1564 .height = 90,
1565 },
1566 .delay =
1567 {
1568 .prepare = 20,
1569 .enable = 200,
1570 .disable = 200,
1571 },
1572 };
1573
1574 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1575 .clock = 30000,
1576 .hdisplay = 800,
1577 .hsync_start = 800 + 40,
1578 .hsync_end = 800 + 40 + 48,
1579 .htotal = 800 + 40 + 48 + 40,
1580 .vdisplay = 480,
1581 .vsync_start = 480 + 13,
1582 .vsync_end = 480 + 13 + 3,
1583 .vtotal = 480 + 13 + 3 + 29,
1584 };
1585
1586 static const struct panel_desc bananapi_s070wv20_ct16 = {
1587 .modes = &bananapi_s070wv20_ct16_mode,
1588 .num_modes = 1,
1589 .bpc = 6,
1590 .size =
1591 {
1592 .width = 154,
1593 .height = 86,
1594 },
1595 };
1596
1597 static const struct drm_display_mode boe_hv070wsa_mode = {
1598 .clock = 42105,
1599 .hdisplay = 1024,
1600 .hsync_start = 1024 + 30,
1601 .hsync_end = 1024 + 30 + 30,
1602 .htotal = 1024 + 30 + 30 + 30,
1603 .vdisplay = 600,
1604 .vsync_start = 600 + 10,
1605 .vsync_end = 600 + 10 + 10,
1606 .vtotal = 600 + 10 + 10 + 10,
1607 };
1608
1609 static const struct panel_desc boe_hv070wsa = {
1610 .modes = &boe_hv070wsa_mode,
1611 .num_modes = 1,
1612 .bpc = 8,
1613 .size =
1614 {
1615 .width = 154,
1616 .height = 90,
1617 },
1618 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1620 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1621 };
1622
1623 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1624 {
1625 .clock = 71900,
1626 .hdisplay = 1280,
1627 .hsync_start = 1280 + 48,
1628 .hsync_end = 1280 + 48 + 32,
1629 .htotal = 1280 + 48 + 32 + 80,
1630 .vdisplay = 800,
1631 .vsync_start = 800 + 3,
1632 .vsync_end = 800 + 3 + 5,
1633 .vtotal = 800 + 3 + 5 + 24,
1634 },
1635 {
1636 .clock = 57500,
1637 .hdisplay = 1280,
1638 .hsync_start = 1280 + 48,
1639 .hsync_end = 1280 + 48 + 32,
1640 .htotal = 1280 + 48 + 32 + 80,
1641 .vdisplay = 800,
1642 .vsync_start = 800 + 3,
1643 .vsync_end = 800 + 3 + 5,
1644 .vtotal = 800 + 3 + 5 + 24,
1645 },
1646 };
1647
1648 static const struct panel_desc boe_nv101wxmn51 = {
1649 .modes = boe_nv101wxmn51_modes,
1650 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1651 .bpc = 8,
1652 .size =
1653 {
1654 .width = 217,
1655 .height = 136,
1656 },
1657 .delay =
1658 {
1659 .prepare = 210,
1660 .enable = 50,
1661 .unprepare = 160,
1662 },
1663 };
1664
1665 /* Also used for boe_nv133fhm_n62 */
1666 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1667 .clock = 147840,
1668 .hdisplay = 1920,
1669 .hsync_start = 1920 + 48,
1670 .hsync_end = 1920 + 48 + 32,
1671 .htotal = 1920 + 48 + 32 + 200,
1672 .vdisplay = 1080,
1673 .vsync_start = 1080 + 3,
1674 .vsync_end = 1080 + 3 + 6,
1675 .vtotal = 1080 + 3 + 6 + 31,
1676 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1677 };
1678
1679 /* Also used for boe_nv133fhm_n62 */
1680 static const struct panel_desc boe_nv133fhm_n61 = {
1681 .modes = &boe_nv133fhm_n61_modes,
1682 .num_modes = 1,
1683 .bpc = 6,
1684 .size =
1685 {
1686 .width = 294,
1687 .height = 165,
1688 },
1689 .delay =
1690 {
1691 /*
1692 * When power is first given to the panel there's a short
1693 * spike on the HPD line. It was explained that this spike
1694 * was until the TCON data download was complete. On
1695 * one system this was measured at 8 ms. We'll put 15 ms
1696 * in the prepare delay just to be safe and take it away
1697 * from the hpd_absent_delay (which would otherwise be 200 ms)
1698 * to handle this. That means:
1699 * - If HPD isn't hooked up you still have 200 ms delay.
1700 * - If HPD is hooked up we won't try to look at it for the
1701 * first 15 ms.
1702 */
1703 .prepare = 15,
1704 .hpd_absent_delay = 185,
1705
1706 .unprepare = 500,
1707 },
1708 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1709 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1710 .connector_type = DRM_MODE_CONNECTOR_eDP,
1711 };
1712
1713 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1714 {
1715 .clock = 148500,
1716 .hdisplay = 1920,
1717 .hsync_start = 1920 + 48,
1718 .hsync_end = 1920 + 48 + 32,
1719 .htotal = 2200,
1720 .vdisplay = 1080,
1721 .vsync_start = 1080 + 3,
1722 .vsync_end = 1080 + 3 + 5,
1723 .vtotal = 1125,
1724 },
1725 };
1726
1727 static const struct panel_desc boe_nv140fhmn49 = {
1728 .modes = boe_nv140fhmn49_modes,
1729 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1730 .bpc = 6,
1731 .size =
1732 {
1733 .width = 309,
1734 .height = 174,
1735 },
1736 .delay =
1737 {
1738 .prepare = 210,
1739 .enable = 50,
1740 .unprepare = 160,
1741 },
1742 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1743 .connector_type = DRM_MODE_CONNECTOR_eDP,
1744 };
1745
1746 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1747 .clock = 9000,
1748 .hdisplay = 480,
1749 .hsync_start = 480 + 5,
1750 .hsync_end = 480 + 5 + 5,
1751 .htotal = 480 + 5 + 5 + 40,
1752 .vdisplay = 272,
1753 .vsync_start = 272 + 8,
1754 .vsync_end = 272 + 8 + 8,
1755 .vtotal = 272 + 8 + 8 + 8,
1756 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1757 };
1758
1759 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1760 .modes = &cdtech_s043wq26h_ct7_mode,
1761 .num_modes = 1,
1762 .bpc = 8,
1763 .size =
1764 {
1765 .width = 95,
1766 .height = 54,
1767 },
1768 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1769 };
1770
1771 /* S070PWS19HP-FC21 2017/04/22 */
1772 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1773 .clock = 51200,
1774 .hdisplay = 1024,
1775 .hsync_start = 1024 + 160,
1776 .hsync_end = 1024 + 160 + 20,
1777 .htotal = 1024 + 160 + 20 + 140,
1778 .vdisplay = 600,
1779 .vsync_start = 600 + 12,
1780 .vsync_end = 600 + 12 + 3,
1781 .vtotal = 600 + 12 + 3 + 20,
1782 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1783 };
1784
1785 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1786 .modes = &cdtech_s070pws19hp_fc21_mode,
1787 .num_modes = 1,
1788 .bpc = 6,
1789 .size =
1790 {
1791 .width = 154,
1792 .height = 86,
1793 },
1794 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1795 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1796 .connector_type = DRM_MODE_CONNECTOR_DPI,
1797 };
1798
1799 /* S070SWV29HG-DC44 2017/09/21 */
1800 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1801 .clock = 33300,
1802 .hdisplay = 800,
1803 .hsync_start = 800 + 210,
1804 .hsync_end = 800 + 210 + 2,
1805 .htotal = 800 + 210 + 2 + 44,
1806 .vdisplay = 480,
1807 .vsync_start = 480 + 22,
1808 .vsync_end = 480 + 22 + 2,
1809 .vtotal = 480 + 22 + 2 + 21,
1810 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1811 };
1812
1813 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1814 .modes = &cdtech_s070swv29hg_dc44_mode,
1815 .num_modes = 1,
1816 .bpc = 6,
1817 .size =
1818 {
1819 .width = 154,
1820 .height = 86,
1821 },
1822 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1823 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1824 .connector_type = DRM_MODE_CONNECTOR_DPI,
1825 };
1826
1827 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1828 .clock = 35000,
1829 .hdisplay = 800,
1830 .hsync_start = 800 + 40,
1831 .hsync_end = 800 + 40 + 40,
1832 .htotal = 800 + 40 + 40 + 48,
1833 .vdisplay = 480,
1834 .vsync_start = 480 + 29,
1835 .vsync_end = 480 + 29 + 13,
1836 .vtotal = 480 + 29 + 13 + 3,
1837 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1838 };
1839
1840 static const struct panel_desc cdtech_s070wv95_ct16 = {
1841 .modes = &cdtech_s070wv95_ct16_mode,
1842 .num_modes = 1,
1843 .bpc = 8,
1844 .size =
1845 {
1846 .width = 154,
1847 .height = 85,
1848 },
1849 };
1850
1851 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1852 .pixelclock = {68900000, 71100000, 73400000},
1853 .hactive = {1280, 1280, 1280},
1854 .hfront_porch = {65, 80, 95},
1855 .hback_porch = {64, 79, 94},
1856 .hsync_len = {1, 1, 1},
1857 .vactive = {800, 800, 800},
1858 .vfront_porch = {7, 11, 14},
1859 .vback_porch = {7, 11, 14},
1860 .vsync_len = {1, 1, 1},
1861 .flags = DISPLAY_FLAGS_DE_HIGH,
1862 };
1863
1864 static const struct panel_desc chefree_ch101olhlwh_002 = {
1865 .timings = &chefree_ch101olhlwh_002_timing,
1866 .num_timings = 1,
1867 .bpc = 8,
1868 .size =
1869 {
1870 .width = 217,
1871 .height = 135,
1872 },
1873 .delay =
1874 {
1875 .enable = 200,
1876 .disable = 200,
1877 },
1878 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1879 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1880 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1881 };
1882
1883 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1884 .clock = 66770,
1885 .hdisplay = 800,
1886 .hsync_start = 800 + 49,
1887 .hsync_end = 800 + 49 + 33,
1888 .htotal = 800 + 49 + 33 + 17,
1889 .vdisplay = 1280,
1890 .vsync_start = 1280 + 1,
1891 .vsync_end = 1280 + 1 + 7,
1892 .vtotal = 1280 + 1 + 7 + 15,
1893 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1894 };
1895
1896 static const struct panel_desc chunghwa_claa070wp03xg = {
1897 .modes = &chunghwa_claa070wp03xg_mode,
1898 .num_modes = 1,
1899 .bpc = 6,
1900 .size =
1901 {
1902 .width = 94,
1903 .height = 150,
1904 },
1905 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1906 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1907 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1908 };
1909
1910 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1911 .clock = 72070,
1912 .hdisplay = 1366,
1913 .hsync_start = 1366 + 58,
1914 .hsync_end = 1366 + 58 + 58,
1915 .htotal = 1366 + 58 + 58 + 58,
1916 .vdisplay = 768,
1917 .vsync_start = 768 + 4,
1918 .vsync_end = 768 + 4 + 4,
1919 .vtotal = 768 + 4 + 4 + 4,
1920 };
1921
1922 static const struct panel_desc chunghwa_claa101wa01a = {
1923 .modes = &chunghwa_claa101wa01a_mode,
1924 .num_modes = 1,
1925 .bpc = 6,
1926 .size =
1927 {
1928 .width = 220,
1929 .height = 120,
1930 },
1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1932 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1933 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1934 };
1935
1936 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1937 .clock = 69300,
1938 .hdisplay = 1366,
1939 .hsync_start = 1366 + 48,
1940 .hsync_end = 1366 + 48 + 32,
1941 .htotal = 1366 + 48 + 32 + 20,
1942 .vdisplay = 768,
1943 .vsync_start = 768 + 16,
1944 .vsync_end = 768 + 16 + 8,
1945 .vtotal = 768 + 16 + 8 + 16,
1946 };
1947
1948 static const struct panel_desc chunghwa_claa101wb01 = {
1949 .modes = &chunghwa_claa101wb01_mode,
1950 .num_modes = 1,
1951 .bpc = 6,
1952 .size =
1953 {
1954 .width = 223,
1955 .height = 125,
1956 },
1957 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1958 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1959 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1960 };
1961
1962 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1963 .clock = 33260,
1964 .hdisplay = 800,
1965 .hsync_start = 800 + 40,
1966 .hsync_end = 800 + 40 + 128,
1967 .htotal = 800 + 40 + 128 + 88,
1968 .vdisplay = 480,
1969 .vsync_start = 480 + 10,
1970 .vsync_end = 480 + 10 + 2,
1971 .vtotal = 480 + 10 + 2 + 33,
1972 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1973 };
1974
1975 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1976 .modes = &dataimage_scf0700c48ggu18_mode,
1977 .num_modes = 1,
1978 .bpc = 8,
1979 .size =
1980 {
1981 .width = 152,
1982 .height = 91,
1983 },
1984 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1985 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1986 };
1987
1988 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1989 .pixelclock = {45000000, 51200000, 57000000},
1990 .hactive = {1024, 1024, 1024},
1991 .hfront_porch = {100, 106, 113},
1992 .hback_porch = {100, 106, 113},
1993 .hsync_len = {100, 108, 114},
1994 .vactive = {600, 600, 600},
1995 .vfront_porch = {8, 11, 15},
1996 .vback_porch = {8, 11, 15},
1997 .vsync_len = {9, 13, 15},
1998 .flags = DISPLAY_FLAGS_DE_HIGH,
1999 };
2000
2001 static const struct panel_desc dlc_dlc0700yzg_1 = {
2002 .timings = &dlc_dlc0700yzg_1_timing,
2003 .num_timings = 1,
2004 .bpc = 6,
2005 .size =
2006 {
2007 .width = 154,
2008 .height = 86,
2009 },
2010 .delay =
2011 {
2012 .prepare = 30,
2013 .enable = 200,
2014 .disable = 200,
2015 },
2016 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2017 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2018 };
2019
2020 static const struct display_timing dlc_dlc1010gig_timing = {
2021 .pixelclock = {68900000, 71100000, 73400000},
2022 .hactive = {1280, 1280, 1280},
2023 .hfront_porch = {43, 53, 63},
2024 .hback_porch = {43, 53, 63},
2025 .hsync_len = {44, 54, 64},
2026 .vactive = {800, 800, 800},
2027 .vfront_porch = {5, 8, 11},
2028 .vback_porch = {5, 8, 11},
2029 .vsync_len = {5, 7, 11},
2030 .flags = DISPLAY_FLAGS_DE_HIGH,
2031 };
2032
2033 static const struct panel_desc dlc_dlc1010gig = {
2034 .timings = &dlc_dlc1010gig_timing,
2035 .num_timings = 1,
2036 .bpc = 8,
2037 .size =
2038 {
2039 .width = 216,
2040 .height = 135,
2041 },
2042 .delay =
2043 {
2044 .prepare = 60,
2045 .enable = 150,
2046 .disable = 100,
2047 .unprepare = 60,
2048 },
2049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2050 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2051 };
2052
2053 static const struct drm_display_mode edt_et035012dm6_mode = {
2054 .clock = 6500,
2055 .hdisplay = 320,
2056 .hsync_start = 320 + 20,
2057 .hsync_end = 320 + 20 + 30,
2058 .htotal = 320 + 20 + 68,
2059 .vdisplay = 240,
2060 .vsync_start = 240 + 4,
2061 .vsync_end = 240 + 4 + 4,
2062 .vtotal = 240 + 4 + 4 + 14,
2063 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2064 };
2065
2066 static const struct panel_desc edt_et035012dm6 = {
2067 .modes = &edt_et035012dm6_mode,
2068 .num_modes = 1,
2069 .bpc = 8,
2070 .size =
2071 {
2072 .width = 70,
2073 .height = 52,
2074 },
2075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2076 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2077 };
2078
2079 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
2080 .clock = 10870,
2081 .hdisplay = 480,
2082 .hsync_start = 480 + 8,
2083 .hsync_end = 480 + 8 + 4,
2084 .htotal = 480 + 8 + 4 + 41,
2085
2086 /*
2087 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
2088 * fb_align
2089 */
2090
2091 .vdisplay = 288,
2092 .vsync_start = 288 + 2,
2093 .vsync_end = 288 + 2 + 4,
2094 .vtotal = 288 + 2 + 4 + 10,
2095 };
2096
2097 static const struct panel_desc edt_etm043080dh6gp = {
2098 .modes = &edt_etm043080dh6gp_mode,
2099 .num_modes = 1,
2100 .bpc = 8,
2101 .size =
2102 {
2103 .width = 100,
2104 .height = 65,
2105 },
2106 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2107 .connector_type = DRM_MODE_CONNECTOR_DPI,
2108 };
2109
2110 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
2111 .clock = 9000,
2112 .hdisplay = 480,
2113 .hsync_start = 480 + 2,
2114 .hsync_end = 480 + 2 + 41,
2115 .htotal = 480 + 2 + 41 + 2,
2116 .vdisplay = 272,
2117 .vsync_start = 272 + 2,
2118 .vsync_end = 272 + 2 + 10,
2119 .vtotal = 272 + 2 + 10 + 2,
2120 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2121 };
2122
2123 static const struct panel_desc edt_etm0430g0dh6 = {
2124 .modes = &edt_etm0430g0dh6_mode,
2125 .num_modes = 1,
2126 .bpc = 6,
2127 .size =
2128 {
2129 .width = 95,
2130 .height = 54,
2131 },
2132 };
2133
2134 static const struct drm_display_mode edt_et057090dhu_mode = {
2135 .clock = 25175,
2136 .hdisplay = 640,
2137 .hsync_start = 640 + 16,
2138 .hsync_end = 640 + 16 + 30,
2139 .htotal = 640 + 16 + 30 + 114,
2140 .vdisplay = 480,
2141 .vsync_start = 480 + 10,
2142 .vsync_end = 480 + 10 + 3,
2143 .vtotal = 480 + 10 + 3 + 32,
2144 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2145 };
2146
2147 static const struct panel_desc edt_et057090dhu = {
2148 .modes = &edt_et057090dhu_mode,
2149 .num_modes = 1,
2150 .bpc = 6,
2151 .size =
2152 {
2153 .width = 115,
2154 .height = 86,
2155 },
2156 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2157 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2158 .connector_type = DRM_MODE_CONNECTOR_DPI,
2159 };
2160
2161 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
2162 .clock = 33260,
2163 .hdisplay = 800,
2164 .hsync_start = 800 + 40,
2165 .hsync_end = 800 + 40 + 128,
2166 .htotal = 800 + 40 + 128 + 88,
2167 .vdisplay = 480,
2168 .vsync_start = 480 + 10,
2169 .vsync_end = 480 + 10 + 2,
2170 .vtotal = 480 + 10 + 2 + 33,
2171 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2172 };
2173
2174 static const struct panel_desc edt_etm0700g0dh6 = {
2175 .modes = &edt_etm0700g0dh6_mode,
2176 .num_modes = 1,
2177 .bpc = 6,
2178 .size =
2179 {
2180 .width = 152,
2181 .height = 91,
2182 },
2183 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2184 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2185 };
2186
2187 static const struct panel_desc edt_etm0700g0bdh6 = {
2188 .modes = &edt_etm0700g0dh6_mode,
2189 .num_modes = 1,
2190 .bpc = 6,
2191 .size =
2192 {
2193 .width = 152,
2194 .height = 91,
2195 },
2196 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2197 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2198 };
2199
2200 static const struct display_timing evervision_vgg804821_timing = {
2201 .pixelclock = {27600000, 33300000, 50000000},
2202 .hactive = {800, 800, 800},
2203 .hfront_porch = {40, 66, 70},
2204 .hback_porch = {40, 67, 70},
2205 .hsync_len = {40, 67, 70},
2206 .vactive = {480, 480, 480},
2207 .vfront_porch = {6, 10, 10},
2208 .vback_porch = {7, 11, 11},
2209 .vsync_len = {7, 11, 11},
2210 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | DISPLAY_FLAGS_DE_HIGH |
2211 DISPLAY_FLAGS_PIXDATA_NEGEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE,
2212 };
2213
2214 static const struct panel_desc evervision_vgg804821 = {
2215 .timings = &evervision_vgg804821_timing,
2216 .num_timings = 1,
2217 .bpc = 8,
2218 .size =
2219 {
2220 .width = 108,
2221 .height = 64,
2222 },
2223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2224 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2225 };
2226
2227 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2228 .clock = 32260,
2229 .hdisplay = 800,
2230 .hsync_start = 800 + 168,
2231 .hsync_end = 800 + 168 + 64,
2232 .htotal = 800 + 168 + 64 + 88,
2233 .vdisplay = 480,
2234 .vsync_start = 480 + 37,
2235 .vsync_end = 480 + 37 + 2,
2236 .vtotal = 480 + 37 + 2 + 8,
2237 };
2238
2239 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2240 .modes = &foxlink_fl500wvr00_a0t_mode,
2241 .num_modes = 1,
2242 .bpc = 8,
2243 .size =
2244 {
2245 .width = 108,
2246 .height = 65,
2247 },
2248 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2249 };
2250
2251 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2252 {
2253 /* 60 Hz */
2254 .clock = 6000,
2255 .hdisplay = 320,
2256 .hsync_start = 320 + 44,
2257 .hsync_end = 320 + 44 + 16,
2258 .htotal = 320 + 44 + 16 + 20,
2259 .vdisplay = 240,
2260 .vsync_start = 240 + 2,
2261 .vsync_end = 240 + 2 + 6,
2262 .vtotal = 240 + 2 + 6 + 2,
2263 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2264 },
2265 {
2266 /* 50 Hz */
2267 .clock = 5400,
2268 .hdisplay = 320,
2269 .hsync_start = 320 + 56,
2270 .hsync_end = 320 + 56 + 16,
2271 .htotal = 320 + 56 + 16 + 40,
2272 .vdisplay = 240,
2273 .vsync_start = 240 + 2,
2274 .vsync_end = 240 + 2 + 6,
2275 .vtotal = 240 + 2 + 6 + 2,
2276 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2277 },
2278 };
2279
2280 static const struct panel_desc frida_frd350h54004 = {
2281 .modes = frida_frd350h54004_modes,
2282 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2283 .bpc = 8,
2284 .size =
2285 {
2286 .width = 77,
2287 .height = 64,
2288 },
2289 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2291 .connector_type = DRM_MODE_CONNECTOR_DPI,
2292 };
2293
2294 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2295 .clock = 67185,
2296 .hdisplay = 800,
2297 .hsync_start = 800 + 20,
2298 .hsync_end = 800 + 20 + 24,
2299 .htotal = 800 + 20 + 24 + 20,
2300 .vdisplay = 1280,
2301 .vsync_start = 1280 + 4,
2302 .vsync_end = 1280 + 4 + 8,
2303 .vtotal = 1280 + 4 + 8 + 4,
2304 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2305 };
2306
2307 static const struct panel_desc friendlyarm_hd702e = {
2308 .modes = &friendlyarm_hd702e_mode,
2309 .num_modes = 1,
2310 .size =
2311 {
2312 .width = 94,
2313 .height = 151,
2314 },
2315 };
2316
2317 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2318 .clock = 9000,
2319 .hdisplay = 480,
2320 .hsync_start = 480 + 5,
2321 .hsync_end = 480 + 5 + 1,
2322 .htotal = 480 + 5 + 1 + 40,
2323 .vdisplay = 272,
2324 .vsync_start = 272 + 8,
2325 .vsync_end = 272 + 8 + 1,
2326 .vtotal = 272 + 8 + 1 + 8,
2327 };
2328
2329 static const struct panel_desc giantplus_gpg482739qs5 = {
2330 .modes = &giantplus_gpg482739qs5_mode,
2331 .num_modes = 1,
2332 .bpc = 8,
2333 .size =
2334 {
2335 .width = 95,
2336 .height = 54,
2337 },
2338 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2339 };
2340
2341 static const struct display_timing giantplus_gpm940b0_timing = {
2342 .pixelclock = {13500000, 27000000, 27500000},
2343 .hactive = {320, 320, 320},
2344 .hfront_porch = {14, 686, 718},
2345 .hback_porch = {50, 70, 255},
2346 .hsync_len = {1, 1, 1},
2347 .vactive = {240, 240, 240},
2348 .vfront_porch = {1, 1, 179},
2349 .vback_porch = {1, 21, 31},
2350 .vsync_len = {1, 1, 6},
2351 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2352 };
2353
2354 static const struct panel_desc giantplus_gpm940b0 = {
2355 .timings = &giantplus_gpm940b0_timing,
2356 .num_timings = 1,
2357 .bpc = 8,
2358 .size =
2359 {
2360 .width = 60,
2361 .height = 45,
2362 },
2363 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2364 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2365 };
2366
2367 static const struct display_timing hannstar_hsd070pww1_timing = {
2368 .pixelclock = {64300000, 71100000, 82000000},
2369 .hactive = {1280, 1280, 1280},
2370 .hfront_porch = {1, 1, 10},
2371 .hback_porch = {1, 1, 10},
2372 /*
2373 * According to the data sheet, the minimum horizontal blanking interval
2374 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2375 * minimum working horizontal blanking interval to be 60 clocks.
2376 */
2377 .hsync_len = {58, 158, 661},
2378 .vactive = {800, 800, 800},
2379 .vfront_porch = {1, 1, 10},
2380 .vback_porch = {1, 1, 10},
2381 .vsync_len = {1, 21, 203},
2382 .flags = DISPLAY_FLAGS_DE_HIGH,
2383 };
2384
2385 static const struct panel_desc hannstar_hsd070pww1 = {
2386 .timings = &hannstar_hsd070pww1_timing,
2387 .num_timings = 1,
2388 .bpc = 6,
2389 .size =
2390 {
2391 .width = 151,
2392 .height = 94,
2393 },
2394 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2395 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2396 };
2397
2398 static const struct display_timing hannstar_hsd100pxn1_timing = {
2399 .pixelclock = {55000000, 65000000, 75000000},
2400 .hactive = {1024, 1024, 1024},
2401 .hfront_porch = {40, 40, 40},
2402 .hback_porch = {220, 220, 220},
2403 .hsync_len = {20, 60, 100},
2404 .vactive = {768, 768, 768},
2405 .vfront_porch = {7, 7, 7},
2406 .vback_porch = {21, 21, 21},
2407 .vsync_len = {10, 10, 10},
2408 .flags = DISPLAY_FLAGS_DE_HIGH,
2409 };
2410
2411 static const struct panel_desc hannstar_hsd100pxn1 = {
2412 .timings = &hannstar_hsd100pxn1_timing,
2413 .num_timings = 1,
2414 .bpc = 6,
2415 .size =
2416 {
2417 .width = 203,
2418 .height = 152,
2419 },
2420 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2421 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2422 };
2423
2424 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2425 .clock = 33333,
2426 .hdisplay = 800,
2427 .hsync_start = 800 + 85,
2428 .hsync_end = 800 + 85 + 86,
2429 .htotal = 800 + 85 + 86 + 85,
2430 .vdisplay = 480,
2431 .vsync_start = 480 + 16,
2432 .vsync_end = 480 + 16 + 13,
2433 .vtotal = 480 + 16 + 13 + 16,
2434 };
2435
2436 static const struct panel_desc hitachi_tx23d38vm0caa = {
2437 .modes = &hitachi_tx23d38vm0caa_mode,
2438 .num_modes = 1,
2439 .bpc = 6,
2440 .size =
2441 {
2442 .width = 195,
2443 .height = 117,
2444 },
2445 .delay =
2446 {
2447 .enable = 160,
2448 .disable = 160,
2449 },
2450 };
2451
2452 static const struct drm_display_mode innolux_at043tn24_mode = {
2453 .clock = 9000,
2454 .hdisplay = 480,
2455 .hsync_start = 480 + 2,
2456 .hsync_end = 480 + 2 + 41,
2457 .htotal = 480 + 2 + 41 + 2,
2458 .vdisplay = 272,
2459 .vsync_start = 272 + 2,
2460 .vsync_end = 272 + 2 + 10,
2461 .vtotal = 272 + 2 + 10 + 2,
2462 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2463 };
2464
2465 static const struct panel_desc innolux_at043tn24 = {
2466 .modes = &innolux_at043tn24_mode,
2467 .num_modes = 1,
2468 .bpc = 8,
2469 .size =
2470 {
2471 .width = 95,
2472 .height = 54,
2473 },
2474 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2475 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2476 };
2477
2478 static const struct drm_display_mode innolux_at070tn92_mode = {
2479 .clock = 33333,
2480 .hdisplay = 800,
2481 .hsync_start = 800 + 210,
2482 .hsync_end = 800 + 210 + 20,
2483 .htotal = 800 + 210 + 20 + 46,
2484 .vdisplay = 480,
2485 .vsync_start = 480 + 22,
2486 .vsync_end = 480 + 22 + 10,
2487 .vtotal = 480 + 22 + 23 + 10,
2488 };
2489
2490 static const struct panel_desc innolux_at070tn92 = {
2491 .modes = &innolux_at070tn92_mode,
2492 .num_modes = 1,
2493 .size =
2494 {
2495 .width = 154,
2496 .height = 86,
2497 },
2498 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2499 };
2500
2501 static const struct display_timing innolux_g070y2_l01_timing = {
2502 .pixelclock = {28000000, 29500000, 32000000},
2503 .hactive = {800, 800, 800},
2504 .hfront_porch = {61, 91, 141},
2505 .hback_porch = {60, 90, 140},
2506 .hsync_len = {12, 12, 12},
2507 .vactive = {480, 480, 480},
2508 .vfront_porch = {4, 9, 30},
2509 .vback_porch = {4, 8, 28},
2510 .vsync_len = {2, 2, 2},
2511 .flags = DISPLAY_FLAGS_DE_HIGH,
2512 };
2513
2514 static const struct panel_desc innolux_g070y2_l01 = {
2515 .timings = &innolux_g070y2_l01_timing,
2516 .num_timings = 1,
2517 .bpc = 8,
2518 .size =
2519 {
2520 .width = 152,
2521 .height = 91,
2522 },
2523 .delay =
2524 {
2525 .prepare = 10,
2526 .enable = 100,
2527 .disable = 100,
2528 .unprepare = 800,
2529 },
2530 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2531 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2532 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2533 };
2534
2535 static const struct display_timing innolux_g101ice_l01_timing = {
2536 .pixelclock = {60400000, 71100000, 74700000},
2537 .hactive = {1280, 1280, 1280},
2538 .hfront_porch = {41, 80, 100},
2539 .hback_porch = {40, 79, 99},
2540 .hsync_len = {1, 1, 1},
2541 .vactive = {800, 800, 800},
2542 .vfront_porch = {5, 11, 14},
2543 .vback_porch = {4, 11, 14},
2544 .vsync_len = {1, 1, 1},
2545 .flags = DISPLAY_FLAGS_DE_HIGH,
2546 };
2547
2548 static const struct panel_desc innolux_g101ice_l01 = {
2549 .timings = &innolux_g101ice_l01_timing,
2550 .num_timings = 1,
2551 .bpc = 8,
2552 .size =
2553 {
2554 .width = 217,
2555 .height = 135,
2556 },
2557 .delay =
2558 {
2559 .enable = 200,
2560 .disable = 200,
2561 },
2562 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2563 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2564 };
2565
2566 static const struct display_timing innolux_g121i1_l01_timing = {
2567 .pixelclock = {67450000, 71000000, 74550000},
2568 .hactive = {1280, 1280, 1280},
2569 .hfront_porch = {40, 80, 160},
2570 .hback_porch = {39, 79, 159},
2571 .hsync_len = {1, 1, 1},
2572 .vactive = {800, 800, 800},
2573 .vfront_porch = {5, 11, 100},
2574 .vback_porch = {4, 11, 99},
2575 .vsync_len = {1, 1, 1},
2576 };
2577
2578 static const struct panel_desc innolux_g121i1_l01 = {
2579 .timings = &innolux_g121i1_l01_timing,
2580 .num_timings = 1,
2581 .bpc = 6,
2582 .size =
2583 {
2584 .width = 261,
2585 .height = 163,
2586 },
2587 .delay =
2588 {
2589 .enable = 200,
2590 .disable = 20,
2591 },
2592 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2593 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2594 };
2595
2596 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2597 .clock = 65000,
2598 .hdisplay = 1024,
2599 .hsync_start = 1024 + 0,
2600 .hsync_end = 1024 + 1,
2601 .htotal = 1024 + 0 + 1 + 320,
2602 .vdisplay = 768,
2603 .vsync_start = 768 + 38,
2604 .vsync_end = 768 + 38 + 1,
2605 .vtotal = 768 + 38 + 1 + 0,
2606 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2607 };
2608
2609 static const struct panel_desc innolux_g121x1_l03 = {
2610 .modes = &innolux_g121x1_l03_mode,
2611 .num_modes = 1,
2612 .bpc = 6,
2613 .size =
2614 {
2615 .width = 246,
2616 .height = 185,
2617 },
2618 .delay =
2619 {
2620 .enable = 200,
2621 .unprepare = 200,
2622 .disable = 400,
2623 },
2624 };
2625
2626 /*
2627 * Datasheet specifies that at 60 Hz refresh rate:
2628 * - total horizontal time: { 1506, 1592, 1716 }
2629 * - total vertical time: { 788, 800, 868 }
2630 *
2631 * ...but doesn't go into exactly how that should be split into a front
2632 * porch, back porch, or sync length. For now we'll leave a single setting
2633 * here which allows a bit of tweaking of the pixel clock at the expense of
2634 * refresh rate.
2635 */
2636 static const struct display_timing innolux_n116bge_timing = {
2637 .pixelclock = {72600000, 76420000, 80240000},
2638 .hactive = {1366, 1366, 1366},
2639 .hfront_porch = {136, 136, 136},
2640 .hback_porch = {60, 60, 60},
2641 .hsync_len = {30, 30, 30},
2642 .vactive = {768, 768, 768},
2643 .vfront_porch = {8, 8, 8},
2644 .vback_porch = {12, 12, 12},
2645 .vsync_len = {12, 12, 12},
2646 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2647 };
2648
2649 static const struct panel_desc innolux_n116bge = {
2650 .timings = &innolux_n116bge_timing,
2651 .num_timings = 1,
2652 .bpc = 6,
2653 .size =
2654 {
2655 .width = 256,
2656 .height = 144,
2657 },
2658 };
2659
2660 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2661 .clock = 69300,
2662 .hdisplay = 1366,
2663 .hsync_start = 1366 + 16,
2664 .hsync_end = 1366 + 16 + 34,
2665 .htotal = 1366 + 16 + 34 + 50,
2666 .vdisplay = 768,
2667 .vsync_start = 768 + 2,
2668 .vsync_end = 768 + 2 + 6,
2669 .vtotal = 768 + 2 + 6 + 12,
2670 };
2671
2672 static const struct panel_desc innolux_n156bge_l21 = {
2673 .modes = &innolux_n156bge_l21_mode,
2674 .num_modes = 1,
2675 .bpc = 6,
2676 .size =
2677 {
2678 .width = 344,
2679 .height = 193,
2680 },
2681 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2682 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2683 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2684 };
2685
2686 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2687 .clock = 206016,
2688 .hdisplay = 2160,
2689 .hsync_start = 2160 + 48,
2690 .hsync_end = 2160 + 48 + 32,
2691 .htotal = 2160 + 48 + 32 + 80,
2692 .vdisplay = 1440,
2693 .vsync_start = 1440 + 3,
2694 .vsync_end = 1440 + 3 + 10,
2695 .vtotal = 1440 + 3 + 10 + 27,
2696 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2697 };
2698
2699 static const struct panel_desc innolux_p120zdg_bf1 = {
2700 .modes = &innolux_p120zdg_bf1_mode,
2701 .num_modes = 1,
2702 .bpc = 8,
2703 .size =
2704 {
2705 .width = 254,
2706 .height = 169,
2707 },
2708 .delay =
2709 {
2710 .hpd_absent_delay = 200,
2711 .unprepare = 500,
2712 },
2713 };
2714
2715 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2716 .clock = 51501,
2717 .hdisplay = 1024,
2718 .hsync_start = 1024 + 128,
2719 .hsync_end = 1024 + 128 + 64,
2720 .htotal = 1024 + 128 + 64 + 128,
2721 .vdisplay = 600,
2722 .vsync_start = 600 + 16,
2723 .vsync_end = 600 + 16 + 4,
2724 .vtotal = 600 + 16 + 4 + 16,
2725 };
2726
2727 static const struct panel_desc innolux_zj070na_01p = {
2728 .modes = &innolux_zj070na_01p_mode,
2729 .num_modes = 1,
2730 .bpc = 6,
2731 .size =
2732 {
2733 .width = 154,
2734 .height = 90,
2735 },
2736 };
2737
2738 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2739 .clock = 138778,
2740 .hdisplay = 1920,
2741 .hsync_start = 1920 + 24,
2742 .hsync_end = 1920 + 24 + 48,
2743 .htotal = 1920 + 24 + 48 + 88,
2744 .vdisplay = 1080,
2745 .vsync_start = 1080 + 3,
2746 .vsync_end = 1080 + 3 + 12,
2747 .vtotal = 1080 + 3 + 12 + 17,
2748 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2749 };
2750
2751 static const struct panel_desc ivo_m133nwf4_r0 = {
2752 .modes = &ivo_m133nwf4_r0_mode,
2753 .num_modes = 1,
2754 .bpc = 8,
2755 .size =
2756 {
2757 .width = 294,
2758 .height = 165,
2759 },
2760 .delay =
2761 {
2762 .hpd_absent_delay = 200,
2763 .unprepare = 500,
2764 },
2765 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2766 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2767 .connector_type = DRM_MODE_CONNECTOR_eDP,
2768 };
2769
2770 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2771 .clock = 81000,
2772 .hdisplay = 1366,
2773 .hsync_start = 1366 + 40,
2774 .hsync_end = 1366 + 40 + 32,
2775 .htotal = 1366 + 40 + 32 + 62,
2776 .vdisplay = 768,
2777 .vsync_start = 768 + 5,
2778 .vsync_end = 768 + 5 + 5,
2779 .vtotal = 768 + 5 + 5 + 122,
2780 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2781 };
2782
2783 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2784 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2785 .num_modes = 1,
2786 .bpc = 6,
2787 .size =
2788 {
2789 .width = 256,
2790 .height = 144,
2791 },
2792 .delay =
2793 {
2794 .hpd_absent_delay = 200,
2795 },
2796 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2797 .connector_type = DRM_MODE_CONNECTOR_eDP,
2798 };
2799
2800 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2801 .pixelclock = {5580000, 5850000, 6200000},
2802 .hactive = {320, 320, 320},
2803 .hfront_porch = {30, 30, 30},
2804 .hback_porch = {30, 30, 30},
2805 .hsync_len = {1, 5, 17},
2806 .vactive = {240, 240, 240},
2807 .vfront_porch = {6, 6, 6},
2808 .vback_porch = {5, 5, 5},
2809 .vsync_len = {1, 2, 11},
2810 .flags = DISPLAY_FLAGS_DE_HIGH,
2811 };
2812
2813 static const struct panel_desc koe_tx14d24vm1bpa = {
2814 .timings = &koe_tx14d24vm1bpa_timing,
2815 .num_timings = 1,
2816 .bpc = 6,
2817 .size =
2818 {
2819 .width = 115,
2820 .height = 86,
2821 },
2822 };
2823
2824 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2825 .pixelclock = {151820000, 156720000, 159780000},
2826 .hactive = {1920, 1920, 1920},
2827 .hfront_porch = {105, 130, 142},
2828 .hback_porch = {45, 70, 82},
2829 .hsync_len = {30, 30, 30},
2830 .vactive = {1200, 1200, 1200},
2831 .vfront_porch = {3, 5, 10},
2832 .vback_porch = {2, 5, 10},
2833 .vsync_len = {5, 5, 5},
2834 };
2835
2836 static const struct panel_desc koe_tx26d202vm0bwa = {
2837 .timings = &koe_tx26d202vm0bwa_timing,
2838 .num_timings = 1,
2839 .bpc = 8,
2840 .size =
2841 {
2842 .width = 217,
2843 .height = 136,
2844 },
2845 .delay =
2846 {
2847 .prepare = 1000,
2848 .enable = 1000,
2849 .unprepare = 1000,
2850 .disable = 1000,
2851 },
2852 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2853 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2854 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2855 };
2856
2857 static const struct display_timing koe_tx31d200vm0baa_timing = {
2858 .pixelclock = {39600000, 43200000, 48000000},
2859 .hactive = {1280, 1280, 1280},
2860 .hfront_porch = {16, 36, 56},
2861 .hback_porch = {16, 36, 56},
2862 .hsync_len = {8, 8, 8},
2863 .vactive = {480, 480, 480},
2864 .vfront_porch = {6, 21, 33},
2865 .vback_porch = {6, 21, 33},
2866 .vsync_len = {8, 8, 8},
2867 .flags = DISPLAY_FLAGS_DE_HIGH,
2868 };
2869
2870 static const struct panel_desc koe_tx31d200vm0baa = {
2871 .timings = &koe_tx31d200vm0baa_timing,
2872 .num_timings = 1,
2873 .bpc = 6,
2874 .size =
2875 {
2876 .width = 292,
2877 .height = 109,
2878 },
2879 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2880 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2881 };
2882
2883 static const struct display_timing kyo_tcg121xglp_timing = {
2884 .pixelclock = {52000000, 65000000, 71000000},
2885 .hactive = {1024, 1024, 1024},
2886 .hfront_porch = {2, 2, 2},
2887 .hback_porch = {2, 2, 2},
2888 .hsync_len = {86, 124, 244},
2889 .vactive = {768, 768, 768},
2890 .vfront_porch = {2, 2, 2},
2891 .vback_porch = {2, 2, 2},
2892 .vsync_len = {6, 34, 73},
2893 .flags = DISPLAY_FLAGS_DE_HIGH,
2894 };
2895
2896 static const struct panel_desc kyo_tcg121xglp = {
2897 .timings = &kyo_tcg121xglp_timing,
2898 .num_timings = 1,
2899 .bpc = 8,
2900 .size =
2901 {
2902 .width = 246,
2903 .height = 184,
2904 },
2905 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2906 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2907 };
2908
2909 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2910 .clock = 7000,
2911 .hdisplay = 320,
2912 .hsync_start = 320 + 20,
2913 .hsync_end = 320 + 20 + 30,
2914 .htotal = 320 + 20 + 30 + 38,
2915 .vdisplay = 240,
2916 .vsync_start = 240 + 4,
2917 .vsync_end = 240 + 4 + 3,
2918 .vtotal = 240 + 4 + 3 + 15,
2919 };
2920
2921 static const struct panel_desc lemaker_bl035_rgb_002 = {
2922 .modes = &lemaker_bl035_rgb_002_mode,
2923 .num_modes = 1,
2924 .size =
2925 {
2926 .width = 70,
2927 .height = 52,
2928 },
2929 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2930 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2931 };
2932
2933 static const struct drm_display_mode lg_lb070wv8_mode = {
2934 .clock = 33246,
2935 .hdisplay = 800,
2936 .hsync_start = 800 + 88,
2937 .hsync_end = 800 + 88 + 80,
2938 .htotal = 800 + 88 + 80 + 88,
2939 .vdisplay = 480,
2940 .vsync_start = 480 + 10,
2941 .vsync_end = 480 + 10 + 25,
2942 .vtotal = 480 + 10 + 25 + 10,
2943 };
2944
2945 static const struct panel_desc lg_lb070wv8 = {
2946 .modes = &lg_lb070wv8_mode,
2947 .num_modes = 1,
2948 .bpc = 8,
2949 .size =
2950 {
2951 .width = 151,
2952 .height = 91,
2953 },
2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2955 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2956 };
2957
2958 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2959 .clock = 200000,
2960 .hdisplay = 1536,
2961 .hsync_start = 1536 + 12,
2962 .hsync_end = 1536 + 12 + 16,
2963 .htotal = 1536 + 12 + 16 + 48,
2964 .vdisplay = 2048,
2965 .vsync_start = 2048 + 8,
2966 .vsync_end = 2048 + 8 + 4,
2967 .vtotal = 2048 + 8 + 4 + 8,
2968 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2969 };
2970
2971 static const struct panel_desc lg_lp079qx1_sp0v = {
2972 .modes = &lg_lp079qx1_sp0v_mode,
2973 .num_modes = 1,
2974 .size =
2975 {
2976 .width = 129,
2977 .height = 171,
2978 },
2979 };
2980
2981 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2982 .clock = 205210,
2983 .hdisplay = 2048,
2984 .hsync_start = 2048 + 150,
2985 .hsync_end = 2048 + 150 + 5,
2986 .htotal = 2048 + 150 + 5 + 5,
2987 .vdisplay = 1536,
2988 .vsync_start = 1536 + 3,
2989 .vsync_end = 1536 + 3 + 1,
2990 .vtotal = 1536 + 3 + 1 + 9,
2991 };
2992
2993 static const struct panel_desc lg_lp097qx1_spa1 = {
2994 .modes = &lg_lp097qx1_spa1_mode,
2995 .num_modes = 1,
2996 .size =
2997 {
2998 .width = 208,
2999 .height = 147,
3000 },
3001 };
3002
3003 static const struct drm_display_mode lg_lp120up1_mode = {
3004 .clock = 162300,
3005 .hdisplay = 1920,
3006 .hsync_start = 1920 + 40,
3007 .hsync_end = 1920 + 40 + 40,
3008 .htotal = 1920 + 40 + 40 + 80,
3009 .vdisplay = 1280,
3010 .vsync_start = 1280 + 4,
3011 .vsync_end = 1280 + 4 + 4,
3012 .vtotal = 1280 + 4 + 4 + 12,
3013 };
3014
3015 static const struct panel_desc lg_lp120up1 = {
3016 .modes = &lg_lp120up1_mode,
3017 .num_modes = 1,
3018 .bpc = 8,
3019 .size =
3020 {
3021 .width = 267,
3022 .height = 183,
3023 },
3024 .connector_type = DRM_MODE_CONNECTOR_eDP,
3025 };
3026
3027 static const struct drm_display_mode lg_lp129qe_mode = {
3028 .clock = 285250,
3029 .hdisplay = 2560,
3030 .hsync_start = 2560 + 48,
3031 .hsync_end = 2560 + 48 + 32,
3032 .htotal = 2560 + 48 + 32 + 80,
3033 .vdisplay = 1700,
3034 .vsync_start = 1700 + 3,
3035 .vsync_end = 1700 + 3 + 10,
3036 .vtotal = 1700 + 3 + 10 + 36,
3037 };
3038
3039 static const struct panel_desc lg_lp129qe = {
3040 .modes = &lg_lp129qe_mode,
3041 .num_modes = 1,
3042 .bpc = 8,
3043 .size =
3044 {
3045 .width = 272,
3046 .height = 181,
3047 },
3048 };
3049
3050 static const struct display_timing logictechno_lt161010_2nh_timing = {
3051 .pixelclock = {26400000, 33300000, 46800000},
3052 .hactive = {800, 800, 800},
3053 .hfront_porch = {16, 210, 354},
3054 .hback_porch = {46, 46, 46},
3055 .hsync_len = {1, 20, 40},
3056 .vactive = {480, 480, 480},
3057 .vfront_porch = {7, 22, 147},
3058 .vback_porch = {23, 23, 23},
3059 .vsync_len = {1, 10, 20},
3060 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3061 DISPLAY_FLAGS_SYNC_POSEDGE,
3062 };
3063
3064 static const struct panel_desc logictechno_lt161010_2nh = {
3065 .timings = &logictechno_lt161010_2nh_timing,
3066 .num_timings = 1,
3067 .size =
3068 {
3069 .width = 154,
3070 .height = 86,
3071 },
3072 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3073 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3074 .connector_type = DRM_MODE_CONNECTOR_DPI,
3075 };
3076
3077 static const struct display_timing logictechno_lt170410_2whc_timing = {
3078 .pixelclock = {68900000, 71100000, 73400000},
3079 .hactive = {1280, 1280, 1280},
3080 .hfront_porch = {23, 60, 71},
3081 .hback_porch = {23, 60, 71},
3082 .hsync_len = {15, 40, 47},
3083 .vactive = {800, 800, 800},
3084 .vfront_porch = {5, 7, 10},
3085 .vback_porch = {5, 7, 10},
3086 .vsync_len = {6, 9, 12},
3087 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3088 DISPLAY_FLAGS_SYNC_POSEDGE,
3089 };
3090
3091 static const struct panel_desc logictechno_lt170410_2whc = {
3092 .timings = &logictechno_lt170410_2whc_timing,
3093 .num_timings = 1,
3094 .size =
3095 {
3096 .width = 217,
3097 .height = 136,
3098 },
3099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3100 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3101 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3102 };
3103
3104 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3105 .clock = 30400,
3106 .hdisplay = 800,
3107 .hsync_start = 800 + 0,
3108 .hsync_end = 800 + 1,
3109 .htotal = 800 + 0 + 1 + 160,
3110 .vdisplay = 480,
3111 .vsync_start = 480 + 0,
3112 .vsync_end = 480 + 48 + 1,
3113 .vtotal = 480 + 48 + 1 + 0,
3114 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3115 };
3116
3117 static const struct drm_display_mode logicpd_type_28_mode = {
3118 .clock = 9107,
3119 .hdisplay = 480,
3120 .hsync_start = 480 + 3,
3121 .hsync_end = 480 + 3 + 42,
3122 .htotal = 480 + 3 + 42 + 2,
3123
3124 .vdisplay = 272,
3125 .vsync_start = 272 + 2,
3126 .vsync_end = 272 + 2 + 11,
3127 .vtotal = 272 + 2 + 11 + 3,
3128 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3129 };
3130
3131 static const struct panel_desc logicpd_type_28 = {
3132 .modes = &logicpd_type_28_mode,
3133 .num_modes = 1,
3134 .bpc = 8,
3135 .size =
3136 {
3137 .width = 105,
3138 .height = 67,
3139 },
3140 .delay =
3141 {
3142 .prepare = 200,
3143 .enable = 200,
3144 .unprepare = 200,
3145 .disable = 200,
3146 },
3147 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3148 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
3149 .connector_type = DRM_MODE_CONNECTOR_DPI,
3150 };
3151
3152 static const struct panel_desc mitsubishi_aa070mc01 = {
3153 .modes = &mitsubishi_aa070mc01_mode,
3154 .num_modes = 1,
3155 .bpc = 8,
3156 .size =
3157 {
3158 .width = 152,
3159 .height = 91,
3160 },
3161
3162 .delay =
3163 {
3164 .enable = 200,
3165 .unprepare = 200,
3166 .disable = 400,
3167 },
3168 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3169 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3170 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3171 };
3172
3173 static const struct display_timing nec_nl12880bc20_05_timing = {
3174 .pixelclock = {67000000, 71000000, 75000000},
3175 .hactive = {1280, 1280, 1280},
3176 .hfront_porch = {2, 30, 30},
3177 .hback_porch = {6, 100, 100},
3178 .hsync_len = {2, 30, 30},
3179 .vactive = {800, 800, 800},
3180 .vfront_porch = {5, 5, 5},
3181 .vback_porch = {11, 11, 11},
3182 .vsync_len = {7, 7, 7},
3183 };
3184
3185 static const struct panel_desc nec_nl12880bc20_05 = {
3186 .timings = &nec_nl12880bc20_05_timing,
3187 .num_timings = 1,
3188 .bpc = 8,
3189 .size =
3190 {
3191 .width = 261,
3192 .height = 163,
3193 },
3194 .delay =
3195 {
3196 .enable = 50,
3197 .disable = 50,
3198 },
3199 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3200 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3201 };
3202
3203 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3204 .clock = 10870,
3205 .hdisplay = 480,
3206 .hsync_start = 480 + 2,
3207 .hsync_end = 480 + 2 + 41,
3208 .htotal = 480 + 2 + 41 + 2,
3209 .vdisplay = 272,
3210 .vsync_start = 272 + 2,
3211 .vsync_end = 272 + 2 + 4,
3212 .vtotal = 272 + 2 + 4 + 2,
3213 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3214 };
3215
3216 static const struct panel_desc nec_nl4827hc19_05b = {
3217 .modes = &nec_nl4827hc19_05b_mode,
3218 .num_modes = 1,
3219 .bpc = 8,
3220 .size =
3221 {
3222 .width = 95,
3223 .height = 54,
3224 },
3225 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3226 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3227 };
3228
3229 static const struct drm_display_mode netron_dy_e231732_mode = {
3230 .clock = 66000,
3231 .hdisplay = 1024,
3232 .hsync_start = 1024 + 160,
3233 .hsync_end = 1024 + 160 + 70,
3234 .htotal = 1024 + 160 + 70 + 90,
3235 .vdisplay = 600,
3236 .vsync_start = 600 + 127,
3237 .vsync_end = 600 + 127 + 20,
3238 .vtotal = 600 + 127 + 20 + 3,
3239 };
3240
3241 static const struct panel_desc netron_dy_e231732 = {
3242 .modes = &netron_dy_e231732_mode,
3243 .num_modes = 1,
3244 .size =
3245 {
3246 .width = 154,
3247 .height = 87,
3248 },
3249 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3250 };
3251
3252 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
3253 {
3254 .clock = 138500,
3255 .hdisplay = 1920,
3256 .hsync_start = 1920 + 48,
3257 .hsync_end = 1920 + 48 + 32,
3258 .htotal = 1920 + 48 + 32 + 80,
3259 .vdisplay = 1080,
3260 .vsync_start = 1080 + 3,
3261 .vsync_end = 1080 + 3 + 5,
3262 .vtotal = 1080 + 3 + 5 + 23,
3263 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3264 },
3265 {
3266 .clock = 110920,
3267 .hdisplay = 1920,
3268 .hsync_start = 1920 + 48,
3269 .hsync_end = 1920 + 48 + 32,
3270 .htotal = 1920 + 48 + 32 + 80,
3271 .vdisplay = 1080,
3272 .vsync_start = 1080 + 3,
3273 .vsync_end = 1080 + 3 + 5,
3274 .vtotal = 1080 + 3 + 5 + 23,
3275 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3276 }};
3277
3278 static const struct panel_desc neweast_wjfh116008a = {
3279 .modes = neweast_wjfh116008a_modes,
3280 .num_modes = 2,
3281 .bpc = 6,
3282 .size =
3283 {
3284 .width = 260,
3285 .height = 150,
3286 },
3287 .delay =
3288 {
3289 .prepare = 110,
3290 .enable = 20,
3291 .unprepare = 500,
3292 },
3293 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3294 .connector_type = DRM_MODE_CONNECTOR_eDP,
3295 };
3296
3297 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3298 .clock = 9000,
3299 .hdisplay = 480,
3300 .hsync_start = 480 + 2,
3301 .hsync_end = 480 + 2 + 41,
3302 .htotal = 480 + 2 + 41 + 2,
3303 .vdisplay = 272,
3304 .vsync_start = 272 + 2,
3305 .vsync_end = 272 + 2 + 10,
3306 .vtotal = 272 + 2 + 10 + 2,
3307 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3308 };
3309
3310 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3311 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3312 .num_modes = 1,
3313 .bpc = 8,
3314 .size =
3315 {
3316 .width = 95,
3317 .height = 54,
3318 },
3319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3320 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3321 .connector_type = DRM_MODE_CONNECTOR_DPI,
3322 };
3323
3324 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3325 .pixelclock = {130000000, 148350000, 163000000},
3326 .hactive = {1920, 1920, 1920},
3327 .hfront_porch = {80, 100, 100},
3328 .hback_porch = {100, 120, 120},
3329 .hsync_len = {50, 60, 60},
3330 .vactive = {1080, 1080, 1080},
3331 .vfront_porch = {12, 30, 30},
3332 .vback_porch = {4, 10, 10},
3333 .vsync_len = {4, 5, 5},
3334 };
3335
3336 static const struct panel_desc nlt_nl192108ac18_02d = {
3337 .timings = &nlt_nl192108ac18_02d_timing,
3338 .num_timings = 1,
3339 .bpc = 8,
3340 .size =
3341 {
3342 .width = 344,
3343 .height = 194,
3344 },
3345 .delay =
3346 {
3347 .unprepare = 500,
3348 },
3349 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3350 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3351 };
3352
3353 static const struct drm_display_mode nvd_9128_mode = {
3354 .clock = 29500,
3355 .hdisplay = 800,
3356 .hsync_start = 800 + 130,
3357 .hsync_end = 800 + 130 + 98,
3358 .htotal = 800 + 0 + 130 + 98,
3359 .vdisplay = 480,
3360 .vsync_start = 480 + 10,
3361 .vsync_end = 480 + 10 + 50,
3362 .vtotal = 480 + 0 + 10 + 50,
3363 };
3364
3365 static const struct panel_desc nvd_9128 = {
3366 .modes = &nvd_9128_mode,
3367 .num_modes = 1,
3368 .bpc = 8,
3369 .size =
3370 {
3371 .width = 156,
3372 .height = 88,
3373 },
3374 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3375 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3376 };
3377
3378 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3379 .pixelclock = {30000000, 30000000, 40000000},
3380 .hactive = {800, 800, 800},
3381 .hfront_porch = {40, 40, 40},
3382 .hback_porch = {40, 40, 40},
3383 .hsync_len = {1, 48, 48},
3384 .vactive = {480, 480, 480},
3385 .vfront_porch = {13, 13, 13},
3386 .vback_porch = {29, 29, 29},
3387 .vsync_len = {3, 3, 3},
3388 .flags = DISPLAY_FLAGS_DE_HIGH,
3389 };
3390
3391 static const struct panel_desc okaya_rs800480t_7x0gp = {
3392 .timings = &okaya_rs800480t_7x0gp_timing,
3393 .num_timings = 1,
3394 .bpc = 6,
3395 .size =
3396 {
3397 .width = 154,
3398 .height = 87,
3399 },
3400 .delay =
3401 {
3402 .prepare = 41,
3403 .enable = 50,
3404 .unprepare = 41,
3405 .disable = 50,
3406 },
3407 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3408 };
3409
3410 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3411 .clock = 9000,
3412 .hdisplay = 480,
3413 .hsync_start = 480 + 5,
3414 .hsync_end = 480 + 5 + 30,
3415 .htotal = 480 + 5 + 30 + 10,
3416 .vdisplay = 272,
3417 .vsync_start = 272 + 8,
3418 .vsync_end = 272 + 8 + 5,
3419 .vtotal = 272 + 8 + 5 + 3,
3420 };
3421
3422 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3423 .modes = &olimex_lcd_olinuxino_43ts_mode,
3424 .num_modes = 1,
3425 .size =
3426 {
3427 .width = 95,
3428 .height = 54,
3429 },
3430 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3431 };
3432
3433 /*
3434 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3435 * pixel clocks, but this is the timing that was being used in the Adafruit
3436 * installation instructions.
3437 */
3438 static const struct drm_display_mode ontat_yx700wv03_mode = {
3439 .clock = 29500,
3440 .hdisplay = 800,
3441 .hsync_start = 824,
3442 .hsync_end = 896,
3443 .htotal = 992,
3444 .vdisplay = 480,
3445 .vsync_start = 483,
3446 .vsync_end = 493,
3447 .vtotal = 500,
3448 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3449 };
3450
3451 /*
3452 * Specification at:
3453 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3454 */
3455 static const struct panel_desc ontat_yx700wv03 = {
3456 .modes = &ontat_yx700wv03_mode,
3457 .num_modes = 1,
3458 .bpc = 8,
3459 .size =
3460 {
3461 .width = 154,
3462 .height = 83,
3463 },
3464 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3465 };
3466
3467 static const struct drm_display_mode ortustech_com37h3m_mode = {
3468 .clock = 22230,
3469 .hdisplay = 480,
3470 .hsync_start = 480 + 40,
3471 .hsync_end = 480 + 40 + 10,
3472 .htotal = 480 + 40 + 10 + 40,
3473 .vdisplay = 640,
3474 .vsync_start = 640 + 4,
3475 .vsync_end = 640 + 4 + 2,
3476 .vtotal = 640 + 4 + 2 + 4,
3477 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3478 };
3479
3480 static const struct panel_desc ortustech_com37h3m = {
3481 .modes = &ortustech_com37h3m_mode,
3482 .num_modes = 1,
3483 .bpc = 8,
3484 .size =
3485 {
3486 .width = 56, /* 56.16mm */
3487 .height = 75, /* 74.88mm */
3488 },
3489 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3491 };
3492
3493 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3494 .clock = 25000,
3495 .hdisplay = 480,
3496 .hsync_start = 480 + 10,
3497 .hsync_end = 480 + 10 + 10,
3498 .htotal = 480 + 10 + 10 + 15,
3499 .vdisplay = 800,
3500 .vsync_start = 800 + 3,
3501 .vsync_end = 800 + 3 + 3,
3502 .vtotal = 800 + 3 + 3 + 3,
3503 };
3504
3505 static const struct panel_desc ortustech_com43h4m85ulc = {
3506 .modes = &ortustech_com43h4m85ulc_mode,
3507 .num_modes = 1,
3508 .bpc = 6,
3509 .size =
3510 {
3511 .width = 56,
3512 .height = 93,
3513 },
3514 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3515 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3516 .connector_type = DRM_MODE_CONNECTOR_DPI,
3517 };
3518
3519 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3520 .clock = 33000,
3521 .hdisplay = 800,
3522 .hsync_start = 800 + 210,
3523 .hsync_end = 800 + 210 + 30,
3524 .htotal = 800 + 210 + 30 + 16,
3525 .vdisplay = 480,
3526 .vsync_start = 480 + 22,
3527 .vsync_end = 480 + 22 + 13,
3528 .vtotal = 480 + 22 + 13 + 10,
3529 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3530 };
3531
3532 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3533 .modes = &osddisplays_osd070t1718_19ts_mode,
3534 .num_modes = 1,
3535 .bpc = 8,
3536 .size =
3537 {
3538 .width = 152,
3539 .height = 91,
3540 },
3541 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3542 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3543 .connector_type = DRM_MODE_CONNECTOR_DPI,
3544 };
3545
3546 static const struct drm_display_mode pda_91_00156_a0_mode = {
3547 .clock = 33300,
3548 .hdisplay = 800,
3549 .hsync_start = 800 + 1,
3550 .hsync_end = 800 + 1 + 64,
3551 .htotal = 800 + 1 + 64 + 64,
3552 .vdisplay = 480,
3553 .vsync_start = 480 + 1,
3554 .vsync_end = 480 + 1 + 23,
3555 .vtotal = 480 + 1 + 23 + 22,
3556 };
3557
3558 static const struct panel_desc pda_91_00156_a0 = {
3559 .modes = &pda_91_00156_a0_mode,
3560 .num_modes = 1,
3561 .size =
3562 {
3563 .width = 152,
3564 .height = 91,
3565 },
3566 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3567 };
3568
3569 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3570 .clock = 24750,
3571 .hdisplay = 800,
3572 .hsync_start = 800 + 54,
3573 .hsync_end = 800 + 54 + 2,
3574 .htotal = 800 + 54 + 2 + 44,
3575 .vdisplay = 480,
3576 .vsync_start = 480 + 49,
3577 .vsync_end = 480 + 49 + 2,
3578 .vtotal = 480 + 49 + 2 + 22,
3579 };
3580
3581 static const struct panel_desc powertip_ph800480t013_idf02 = {
3582 .modes = &powertip_ph800480t013_idf02_mode,
3583 .num_modes = 1,
3584 .size =
3585 {
3586 .width = 152,
3587 .height = 91,
3588 },
3589 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3590 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3591 .connector_type = DRM_MODE_CONNECTOR_DPI,
3592 };
3593
3594 static const struct drm_display_mode qd43003c0_40_mode = {
3595 .clock = 9000,
3596 .hdisplay = 480,
3597 .hsync_start = 480 + 8,
3598 .hsync_end = 480 + 8 + 4,
3599 .htotal = 480 + 8 + 4 + 39,
3600 .vdisplay = 272,
3601 .vsync_start = 272 + 4,
3602 .vsync_end = 272 + 4 + 10,
3603 .vtotal = 272 + 4 + 10 + 2,
3604 };
3605
3606 static const struct panel_desc qd43003c0_40 = {
3607 .modes = &qd43003c0_40_mode,
3608 .num_modes = 1,
3609 .bpc = 8,
3610 .size =
3611 {
3612 .width = 95,
3613 .height = 53,
3614 },
3615 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3616 };
3617
3618 static const struct display_timing rocktech_rk070er9427_timing = {
3619 .pixelclock = {26400000, 33300000, 46800000},
3620 .hactive = {800, 800, 800},
3621 .hfront_porch = {16, 210, 354},
3622 .hback_porch = {46, 46, 46},
3623 .hsync_len = {1, 1, 1},
3624 .vactive = {480, 480, 480},
3625 .vfront_porch = {7, 22, 147},
3626 .vback_porch = {23, 23, 23},
3627 .vsync_len = {1, 1, 1},
3628 .flags = DISPLAY_FLAGS_DE_HIGH,
3629 };
3630
3631 static const struct panel_desc rocktech_rk070er9427 = {
3632 .timings = &rocktech_rk070er9427_timing,
3633 .num_timings = 1,
3634 .bpc = 6,
3635 .size =
3636 {
3637 .width = 154,
3638 .height = 86,
3639 },
3640 .delay =
3641 {
3642 .prepare = 41,
3643 .enable = 50,
3644 .unprepare = 41,
3645 .disable = 50,
3646 },
3647 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3648 };
3649
3650 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3651 .clock = 71100,
3652 .hdisplay = 1280,
3653 .hsync_start = 1280 + 48,
3654 .hsync_end = 1280 + 48 + 32,
3655 .htotal = 1280 + 48 + 32 + 80,
3656 .vdisplay = 800,
3657 .vsync_start = 800 + 2,
3658 .vsync_end = 800 + 2 + 5,
3659 .vtotal = 800 + 2 + 5 + 16,
3660 };
3661
3662 static const struct panel_desc rocktech_rk101ii01d_ct = {
3663 .modes = &rocktech_rk101ii01d_ct_mode,
3664 .num_modes = 1,
3665 .size =
3666 {
3667 .width = 217,
3668 .height = 136,
3669 },
3670 .delay =
3671 {
3672 .prepare = 50,
3673 .disable = 50,
3674 },
3675 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3676 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3677 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3678 };
3679
3680 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3681 .clock = 271560,
3682 .hdisplay = 2560,
3683 .hsync_start = 2560 + 48,
3684 .hsync_end = 2560 + 48 + 32,
3685 .htotal = 2560 + 48 + 32 + 80,
3686 .vdisplay = 1600,
3687 .vsync_start = 1600 + 2,
3688 .vsync_end = 1600 + 2 + 5,
3689 .vtotal = 1600 + 2 + 5 + 57,
3690 };
3691
3692 static const struct panel_desc samsung_lsn122dl01_c01 = {
3693 .modes = &samsung_lsn122dl01_c01_mode,
3694 .num_modes = 1,
3695 .size =
3696 {
3697 .width = 263,
3698 .height = 164,
3699 },
3700 };
3701
3702 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3703 .clock = 54030,
3704 .hdisplay = 1024,
3705 .hsync_start = 1024 + 24,
3706 .hsync_end = 1024 + 24 + 136,
3707 .htotal = 1024 + 24 + 136 + 160,
3708 .vdisplay = 600,
3709 .vsync_start = 600 + 3,
3710 .vsync_end = 600 + 3 + 6,
3711 .vtotal = 600 + 3 + 6 + 61,
3712 };
3713
3714 static const struct panel_desc samsung_ltn101nt05 = {
3715 .modes = &samsung_ltn101nt05_mode,
3716 .num_modes = 1,
3717 .bpc = 6,
3718 .size =
3719 {
3720 .width = 223,
3721 .height = 125,
3722 },
3723 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3724 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3725 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3726 };
3727
3728 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3729 .clock = 76300,
3730 .hdisplay = 1366,
3731 .hsync_start = 1366 + 64,
3732 .hsync_end = 1366 + 64 + 48,
3733 .htotal = 1366 + 64 + 48 + 128,
3734 .vdisplay = 768,
3735 .vsync_start = 768 + 2,
3736 .vsync_end = 768 + 2 + 5,
3737 .vtotal = 768 + 2 + 5 + 17,
3738 };
3739
3740 static const struct panel_desc samsung_ltn140at29_301 = {
3741 .modes = &samsung_ltn140at29_301_mode,
3742 .num_modes = 1,
3743 .bpc = 6,
3744 .size =
3745 {
3746 .width = 320,
3747 .height = 187,
3748 },
3749 };
3750
3751 static const struct display_timing satoz_sat050at40h12r2_timing = {
3752 .pixelclock = {33300000, 33300000, 50000000},
3753 .hactive = {800, 800, 800},
3754 .hfront_porch = {16, 210, 354},
3755 .hback_porch = {46, 46, 46},
3756 .hsync_len = {1, 1, 40},
3757 .vactive = {480, 480, 480},
3758 .vfront_porch = {7, 22, 147},
3759 .vback_porch = {23, 23, 23},
3760 .vsync_len = {1, 1, 20},
3761 };
3762
3763 static const struct panel_desc satoz_sat050at40h12r2 = {
3764 .timings = &satoz_sat050at40h12r2_timing,
3765 .num_timings = 1,
3766 .bpc = 8,
3767 .size =
3768 {
3769 .width = 108,
3770 .height = 65,
3771 },
3772 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3773 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3774 };
3775
3776 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3777 .clock = 168480,
3778 .hdisplay = 1920,
3779 .hsync_start = 1920 + 48,
3780 .hsync_end = 1920 + 48 + 32,
3781 .htotal = 1920 + 48 + 32 + 80,
3782 .vdisplay = 1280,
3783 .vsync_start = 1280 + 3,
3784 .vsync_end = 1280 + 3 + 10,
3785 .vtotal = 1280 + 3 + 10 + 57,
3786 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3787 };
3788
3789 static const struct panel_desc sharp_ld_d5116z01b = {
3790 .modes = &sharp_ld_d5116z01b_mode,
3791 .num_modes = 1,
3792 .bpc = 8,
3793 .size =
3794 {
3795 .width = 260,
3796 .height = 120,
3797 },
3798 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3799 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3800 };
3801
3802 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3803 .clock = 33260,
3804 .hdisplay = 800,
3805 .hsync_start = 800 + 64,
3806 .hsync_end = 800 + 64 + 128,
3807 .htotal = 800 + 64 + 128 + 64,
3808 .vdisplay = 480,
3809 .vsync_start = 480 + 8,
3810 .vsync_end = 480 + 8 + 2,
3811 .vtotal = 480 + 8 + 2 + 35,
3812 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3813 };
3814
3815 static const struct panel_desc sharp_lq070y3dg3b = {
3816 .modes = &sharp_lq070y3dg3b_mode,
3817 .num_modes = 1,
3818 .bpc = 8,
3819 .size =
3820 {
3821 .width = 152, /* 152.4mm */
3822 .height = 91, /* 91.4mm */
3823 },
3824 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3825 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3826 };
3827
3828 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3829 .clock = 5500,
3830 .hdisplay = 240,
3831 .hsync_start = 240 + 16,
3832 .hsync_end = 240 + 16 + 7,
3833 .htotal = 240 + 16 + 7 + 5,
3834 .vdisplay = 320,
3835 .vsync_start = 320 + 9,
3836 .vsync_end = 320 + 9 + 1,
3837 .vtotal = 320 + 9 + 1 + 7,
3838 };
3839
3840 static const struct panel_desc sharp_lq035q7db03 = {
3841 .modes = &sharp_lq035q7db03_mode,
3842 .num_modes = 1,
3843 .bpc = 6,
3844 .size =
3845 {
3846 .width = 54,
3847 .height = 72,
3848 },
3849 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3850 };
3851
3852 static const struct display_timing sharp_lq101k1ly04_timing = {
3853 .pixelclock = {60000000, 65000000, 80000000},
3854 .hactive = {1280, 1280, 1280},
3855 .hfront_porch = {20, 20, 20},
3856 .hback_porch = {20, 20, 20},
3857 .hsync_len = {10, 10, 10},
3858 .vactive = {800, 800, 800},
3859 .vfront_porch = {4, 4, 4},
3860 .vback_porch = {4, 4, 4},
3861 .vsync_len = {4, 4, 4},
3862 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3863 };
3864
3865 static const struct panel_desc sharp_lq101k1ly04 = {
3866 .timings = &sharp_lq101k1ly04_timing,
3867 .num_timings = 1,
3868 .bpc = 8,
3869 .size =
3870 {
3871 .width = 217,
3872 .height = 136,
3873 },
3874 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3875 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3876 };
3877
3878 static const struct display_timing sharp_lq123p1jx31_timing = {
3879 .pixelclock = {252750000, 252750000, 266604720},
3880 .hactive = {2400, 2400, 2400},
3881 .hfront_porch = {48, 48, 48},
3882 .hback_porch = {80, 80, 84},
3883 .hsync_len = {32, 32, 32},
3884 .vactive = {1600, 1600, 1600},
3885 .vfront_porch = {3, 3, 3},
3886 .vback_porch = {33, 33, 120},
3887 .vsync_len = {10, 10, 10},
3888 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3889 };
3890
3891 static const struct panel_desc sharp_lq123p1jx31 = {
3892 .timings = &sharp_lq123p1jx31_timing,
3893 .num_timings = 1,
3894 .bpc = 8,
3895 .size =
3896 {
3897 .width = 259,
3898 .height = 173,
3899 },
3900 .delay =
3901 {
3902 .prepare = 110,
3903 .enable = 50,
3904 .unprepare = 550,
3905 },
3906 };
3907
3908 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3909 {
3910 /* 50 Hz */
3911 .clock = 3000,
3912 .hdisplay = 240,
3913 .hsync_start = 240 + 58,
3914 .hsync_end = 240 + 58 + 1,
3915 .htotal = 240 + 58 + 1 + 1,
3916 .vdisplay = 160,
3917 .vsync_start = 160 + 24,
3918 .vsync_end = 160 + 24 + 10,
3919 .vtotal = 160 + 24 + 10 + 6,
3920 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3921 },
3922 {
3923 /* 60 Hz */
3924 .clock = 3000,
3925 .hdisplay = 240,
3926 .hsync_start = 240 + 8,
3927 .hsync_end = 240 + 8 + 1,
3928 .htotal = 240 + 8 + 1 + 1,
3929 .vdisplay = 160,
3930 .vsync_start = 160 + 24,
3931 .vsync_end = 160 + 24 + 10,
3932 .vtotal = 160 + 24 + 10 + 6,
3933 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3934 },
3935 };
3936
3937 static const struct panel_desc sharp_ls020b1dd01d = {
3938 .modes = sharp_ls020b1dd01d_modes,
3939 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3940 .bpc = 6,
3941 .size =
3942 {
3943 .width = 42,
3944 .height = 28,
3945 },
3946 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3947 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | DRM_BUS_FLAG_SHARP_SIGNALS,
3948 };
3949
3950 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3951 .clock = 33300,
3952 .hdisplay = 800,
3953 .hsync_start = 800 + 1,
3954 .hsync_end = 800 + 1 + 64,
3955 .htotal = 800 + 1 + 64 + 64,
3956 .vdisplay = 480,
3957 .vsync_start = 480 + 1,
3958 .vsync_end = 480 + 1 + 23,
3959 .vtotal = 480 + 1 + 23 + 22,
3960 };
3961
3962 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3963 .modes = &shelly_sca07010_bfn_lnn_mode,
3964 .num_modes = 1,
3965 .size =
3966 {
3967 .width = 152,
3968 .height = 91,
3969 },
3970 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3971 };
3972
3973 static const struct drm_display_mode starry_kr070pe2t_mode = {
3974 .clock = 33000,
3975 .hdisplay = 800,
3976 .hsync_start = 800 + 209,
3977 .hsync_end = 800 + 209 + 1,
3978 .htotal = 800 + 209 + 1 + 45,
3979 .vdisplay = 480,
3980 .vsync_start = 480 + 22,
3981 .vsync_end = 480 + 22 + 1,
3982 .vtotal = 480 + 22 + 1 + 22,
3983 };
3984
3985 static const struct panel_desc starry_kr070pe2t = {
3986 .modes = &starry_kr070pe2t_mode,
3987 .num_modes = 1,
3988 .bpc = 8,
3989 .size =
3990 {
3991 .width = 152,
3992 .height = 86,
3993 },
3994 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3995 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3996 .connector_type = DRM_MODE_CONNECTOR_DPI,
3997 };
3998
3999 static const struct drm_display_mode starry_kr122ea0sra_mode = {
4000 .clock = 147000,
4001 .hdisplay = 1920,
4002 .hsync_start = 1920 + 16,
4003 .hsync_end = 1920 + 16 + 16,
4004 .htotal = 1920 + 16 + 16 + 32,
4005 .vdisplay = 1200,
4006 .vsync_start = 1200 + 15,
4007 .vsync_end = 1200 + 15 + 2,
4008 .vtotal = 1200 + 15 + 2 + 18,
4009 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4010 };
4011
4012 static const struct panel_desc starry_kr122ea0sra = {
4013 .modes = &starry_kr122ea0sra_mode,
4014 .num_modes = 1,
4015 .size =
4016 {
4017 .width = 263,
4018 .height = 164,
4019 },
4020 .delay =
4021 {
4022 .prepare = 10 + 200,
4023 .enable = 50,
4024 .unprepare = 10 + 500,
4025 },
4026 };
4027
4028 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4029 .clock = 30000,
4030 .hdisplay = 800,
4031 .hsync_start = 800 + 39,
4032 .hsync_end = 800 + 39 + 47,
4033 .htotal = 800 + 39 + 47 + 39,
4034 .vdisplay = 480,
4035 .vsync_start = 480 + 13,
4036 .vsync_end = 480 + 13 + 2,
4037 .vtotal = 480 + 13 + 2 + 29,
4038 };
4039
4040 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4041 .modes = &tfc_s9700rtwv43tr_01b_mode,
4042 .num_modes = 1,
4043 .bpc = 8,
4044 .size =
4045 {
4046 .width = 155,
4047 .height = 90,
4048 },
4049 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4050 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4051 };
4052
4053 static const struct display_timing tianma_tm070jdhg30_timing = {
4054 .pixelclock = {62600000, 68200000, 78100000},
4055 .hactive = {1280, 1280, 1280},
4056 .hfront_porch = {15, 64, 159},
4057 .hback_porch = {5, 5, 5},
4058 .hsync_len = {1, 1, 256},
4059 .vactive = {800, 800, 800},
4060 .vfront_porch = {3, 40, 99},
4061 .vback_porch = {2, 2, 2},
4062 .vsync_len = {1, 1, 128},
4063 .flags = DISPLAY_FLAGS_DE_HIGH,
4064 };
4065
4066 static const struct panel_desc tianma_tm070jdhg30 = {
4067 .timings = &tianma_tm070jdhg30_timing,
4068 .num_timings = 1,
4069 .bpc = 8,
4070 .size =
4071 {
4072 .width = 151,
4073 .height = 95,
4074 },
4075 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4076 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4077 };
4078
4079 static const struct panel_desc tianma_tm070jvhg33 = {
4080 .timings = &tianma_tm070jdhg30_timing,
4081 .num_timings = 1,
4082 .bpc = 8,
4083 .size =
4084 {
4085 .width = 150,
4086 .height = 94,
4087 },
4088 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4089 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4090 };
4091
4092 static const struct display_timing tianma_tm070rvhg71_timing = {
4093 .pixelclock = {27700000, 29200000, 39600000},
4094 .hactive = {800, 800, 800},
4095 .hfront_porch = {12, 40, 212},
4096 .hback_porch = {88, 88, 88},
4097 .hsync_len = {1, 1, 40},
4098 .vactive = {480, 480, 480},
4099 .vfront_porch = {1, 13, 88},
4100 .vback_porch = {32, 32, 32},
4101 .vsync_len = {1, 1, 3},
4102 .flags = DISPLAY_FLAGS_DE_HIGH,
4103 };
4104
4105 static const struct panel_desc tianma_tm070rvhg71 = {
4106 .timings = &tianma_tm070rvhg71_timing,
4107 .num_timings = 1,
4108 .bpc = 8,
4109 .size =
4110 {
4111 .width = 154,
4112 .height = 86,
4113 },
4114 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4115 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4116 };
4117
4118 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4119 {
4120 .clock = 10000,
4121 .hdisplay = 320,
4122 .hsync_start = 320 + 50,
4123 .hsync_end = 320 + 50 + 6,
4124 .htotal = 320 + 50 + 6 + 38,
4125 .vdisplay = 240,
4126 .vsync_start = 240 + 3,
4127 .vsync_end = 240 + 3 + 1,
4128 .vtotal = 240 + 3 + 1 + 17,
4129 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4130 },
4131 };
4132
4133 static const struct panel_desc ti_nspire_cx_lcd_panel = {
4134 .modes = ti_nspire_cx_lcd_mode,
4135 .num_modes = 1,
4136 .bpc = 8,
4137 .size =
4138 {
4139 .width = 65,
4140 .height = 49,
4141 },
4142 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4143 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4144 };
4145
4146 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4147 {
4148 .clock = 10000,
4149 .hdisplay = 320,
4150 .hsync_start = 320 + 6,
4151 .hsync_end = 320 + 6 + 6,
4152 .htotal = 320 + 6 + 6 + 6,
4153 .vdisplay = 240,
4154 .vsync_start = 240 + 0,
4155 .vsync_end = 240 + 0 + 1,
4156 .vtotal = 240 + 0 + 1 + 0,
4157 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4158 },
4159 };
4160
4161 static const struct panel_desc ti_nspire_classic_lcd_panel = {
4162 .modes = ti_nspire_classic_lcd_mode,
4163 .num_modes = 1,
4164 /* The grayscale panel has 8 bit for the color .. Y (black) */
4165 .bpc = 8,
4166 .size =
4167 {
4168 .width = 71,
4169 .height = 53,
4170 },
4171 /* This is the grayscale bus format */
4172 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4173 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4174 };
4175
4176 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4177 .clock = 79500,
4178 .hdisplay = 1280,
4179 .hsync_start = 1280 + 192,
4180 .hsync_end = 1280 + 192 + 128,
4181 .htotal = 1280 + 192 + 128 + 64,
4182 .vdisplay = 768,
4183 .vsync_start = 768 + 20,
4184 .vsync_end = 768 + 20 + 7,
4185 .vtotal = 768 + 20 + 7 + 3,
4186 };
4187
4188 static const struct panel_desc toshiba_lt089ac29000 = {
4189 .modes = &toshiba_lt089ac29000_mode,
4190 .num_modes = 1,
4191 .size =
4192 {
4193 .width = 194,
4194 .height = 116,
4195 },
4196 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4197 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4198 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4199 };
4200
4201 static const struct drm_display_mode tpk_f07a_0102_mode = {
4202 .clock = 33260,
4203 .hdisplay = 800,
4204 .hsync_start = 800 + 40,
4205 .hsync_end = 800 + 40 + 128,
4206 .htotal = 800 + 40 + 128 + 88,
4207 .vdisplay = 480,
4208 .vsync_start = 480 + 10,
4209 .vsync_end = 480 + 10 + 2,
4210 .vtotal = 480 + 10 + 2 + 33,
4211 };
4212
4213 static const struct panel_desc tpk_f07a_0102 = {
4214 .modes = &tpk_f07a_0102_mode,
4215 .num_modes = 1,
4216 .size =
4217 {
4218 .width = 152,
4219 .height = 91,
4220 },
4221 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4222 };
4223
4224 static const struct drm_display_mode tpk_f10a_0102_mode = {
4225 .clock = 45000,
4226 .hdisplay = 1024,
4227 .hsync_start = 1024 + 176,
4228 .hsync_end = 1024 + 176 + 5,
4229 .htotal = 1024 + 176 + 5 + 88,
4230 .vdisplay = 600,
4231 .vsync_start = 600 + 20,
4232 .vsync_end = 600 + 20 + 5,
4233 .vtotal = 600 + 20 + 5 + 25,
4234 };
4235
4236 static const struct panel_desc tpk_f10a_0102 = {
4237 .modes = &tpk_f10a_0102_mode,
4238 .num_modes = 1,
4239 .size =
4240 {
4241 .width = 223,
4242 .height = 125,
4243 },
4244 };
4245
4246 static const struct display_timing urt_umsh_8596md_timing = {
4247 .pixelclock = {33260000, 33260000, 33260000},
4248 .hactive = {800, 800, 800},
4249 .hfront_porch = {41, 41, 41},
4250 .hback_porch = {216 - 128, 216 - 128, 216 - 128},
4251 .hsync_len = {71, 128, 128},
4252 .vactive = {480, 480, 480},
4253 .vfront_porch = {10, 10, 10},
4254 .vback_porch = {35 - 2, 35 - 2, 35 - 2},
4255 .vsync_len = {2, 2, 2},
4256 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4257 };
4258
4259 static const struct panel_desc urt_umsh_8596md_lvds = {
4260 .timings = &urt_umsh_8596md_timing,
4261 .num_timings = 1,
4262 .bpc = 6,
4263 .size =
4264 {
4265 .width = 152,
4266 .height = 91,
4267 },
4268 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4269 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4270 };
4271
4272 static const struct panel_desc urt_umsh_8596md_parallel = {
4273 .timings = &urt_umsh_8596md_timing,
4274 .num_timings = 1,
4275 .bpc = 6,
4276 .size =
4277 {
4278 .width = 152,
4279 .height = 91,
4280 },
4281 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4282 };
4283
4284 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4285 .clock = 33333,
4286 .hdisplay = 800,
4287 .hsync_start = 800 + 210,
4288 .hsync_end = 800 + 210 + 20,
4289 .htotal = 800 + 210 + 20 + 46,
4290 .vdisplay = 480,
4291 .vsync_start = 480 + 22,
4292 .vsync_end = 480 + 22 + 10,
4293 .vtotal = 480 + 22 + 10 + 23,
4294 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4295 };
4296
4297 static const struct panel_desc vl050_8048nt_c01 = {
4298 .modes = &vl050_8048nt_c01_mode,
4299 .num_modes = 1,
4300 .bpc = 8,
4301 .size =
4302 {
4303 .width = 120,
4304 .height = 76,
4305 },
4306 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4307 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4308 };
4309
4310 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4311 .clock = 6410,
4312 .hdisplay = 320,
4313 .hsync_start = 320 + 20,
4314 .hsync_end = 320 + 20 + 30,
4315 .htotal = 320 + 20 + 30 + 38,
4316 .vdisplay = 240,
4317 .vsync_start = 240 + 4,
4318 .vsync_end = 240 + 4 + 3,
4319 .vtotal = 240 + 4 + 3 + 15,
4320 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4321 };
4322
4323 static const struct panel_desc winstar_wf35ltiacd = {
4324 .modes = &winstar_wf35ltiacd_mode,
4325 .num_modes = 1,
4326 .bpc = 8,
4327 .size =
4328 {
4329 .width = 70,
4330 .height = 53,
4331 },
4332 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4333 };
4334
4335 static const struct drm_display_mode arm_rtsm_mode[] = {
4336 {
4337 .clock = 65000,
4338 .hdisplay = 1024,
4339 .hsync_start = 1024 + 24,
4340 .hsync_end = 1024 + 24 + 136,
4341 .htotal = 1024 + 24 + 136 + 160,
4342 .vdisplay = 768,
4343 .vsync_start = 768 + 3,
4344 .vsync_end = 768 + 3 + 6,
4345 .vtotal = 768 + 3 + 6 + 29,
4346 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4347 },
4348 };
4349
4350 static const struct panel_desc arm_rtsm = {
4351 .modes = arm_rtsm_mode,
4352 .num_modes = 1,
4353 .bpc = 8,
4354 .size =
4355 {
4356 .width = 400,
4357 .height = 300,
4358 },
4359 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4360 };
4361
4362 static const struct of_device_id platform_of_match[] = {
4363 {
4364 .compatible = "simple-panel",
4365 .data = NULL,
4366 },
4367 {
4368 .compatible = "ampire,am-1280800n3tzqw-t00h",
4369 .data = &ire_am_1280800n3tzqw_t00h,
4370 },
4371 {
4372 .compatible = "ampire,am-480272h3tmqw-t01h",
4373 .data = &ire_am_480272h3tmqw_t01h,
4374 },
4375 {
4376 .compatible = "ampire,am800480r3tmqwa1h",
4377 .data = &ire_am800480r3tmqwa1h,
4378 },
4379 {
4380 .compatible = "arm,rtsm-display",
4381 .data = &arm_rtsm,
4382 },
4383 {
4384 .compatible = "armadeus,st0700-adapt",
4385 .data = &armadeus_st0700_adapt,
4386 },
4387 {
4388 .compatible = "auo,b101aw03",
4389 .data = &auo_b101aw03,
4390 },
4391 {
4392 .compatible = "auo,b101ean01",
4393 .data = &auo_b101ean01,
4394 },
4395 {
4396 .compatible = "auo,b101xtn01",
4397 .data = &auo_b101xtn01,
4398 },
4399 {
4400 .compatible = "auo,b116xa01",
4401 .data = &auo_b116xak01,
4402 },
4403 {
4404 .compatible = "auo,b116xw03",
4405 .data = &auo_b116xw03,
4406 },
4407 {
4408 .compatible = "auo,b133htn01",
4409 .data = &auo_b133htn01,
4410 },
4411 {
4412 .compatible = "auo,b133xtn01",
4413 .data = &auo_b133xtn01,
4414 },
4415 {
4416 .compatible = "auo,g070vvn01",
4417 .data = &auo_g070vvn01,
4418 },
4419 {
4420 .compatible = "auo,g101evn010",
4421 .data = &auo_g101evn010,
4422 },
4423 {
4424 .compatible = "auo,g104sn02",
4425 .data = &auo_g104sn02,
4426 },
4427 {
4428 .compatible = "auo,g121ean01",
4429 .data = &auo_g121ean01,
4430 },
4431 {
4432 .compatible = "auo,g133han01",
4433 .data = &auo_g133han01,
4434 },
4435 {
4436 .compatible = "auo,g156xtn01",
4437 .data = &auo_g156xtn01,
4438 },
4439 {
4440 .compatible = "auo,g185han01",
4441 .data = &auo_g185han01,
4442 },
4443 {
4444 .compatible = "auo,g190ean01",
4445 .data = &auo_g190ean01,
4446 },
4447 {
4448 .compatible = "auo,p320hvn03",
4449 .data = &auo_p320hvn03,
4450 },
4451 {
4452 .compatible = "auo,t215hvn01",
4453 .data = &auo_t215hvn01,
4454 },
4455 {
4456 .compatible = "avic,tm070ddh03",
4457 .data = &avic_tm070ddh03,
4458 },
4459 {
4460 .compatible = "bananapi,s070wv20-ct16",
4461 .data = &bananapi_s070wv20_ct16,
4462 },
4463 {.compatible = "boe,hv070wsa-100", .data = &boe_hv070wsa},
4464 {
4465 .compatible = "boe,nv101wxmn51",
4466 .data = &boe_nv101wxmn51,
4467 },
4468 {
4469 .compatible = "boe,nv133fhm-n61",
4470 .data = &boe_nv133fhm_n61,
4471 },
4472 {
4473 .compatible = "boe,nv133fhm-n62",
4474 .data = &boe_nv133fhm_n61,
4475 },
4476 {
4477 .compatible = "boe,nv140fhmn49",
4478 .data = &boe_nv140fhmn49,
4479 },
4480 {
4481 .compatible = "cdtech,s043wq26h-ct7",
4482 .data = &cdtech_s043wq26h_ct7,
4483 },
4484 {
4485 .compatible = "cdtech,s070pws19hp-fc21",
4486 .data = &cdtech_s070pws19hp_fc21,
4487 },
4488 {
4489 .compatible = "cdtech,s070swv29hg-dc44",
4490 .data = &cdtech_s070swv29hg_dc44,
4491 },
4492 {
4493 .compatible = "cdtech,s070wv95-ct16",
4494 .data = &cdtech_s070wv95_ct16,
4495 },
4496 {
4497 .compatible = "chefree,ch101olhlwh-002",
4498 .data = &chefree_ch101olhlwh_002,
4499 },
4500 {
4501 .compatible = "chunghwa,claa070wp03xg",
4502 .data = &chunghwa_claa070wp03xg,
4503 },
4504 {.compatible = "chunghwa,claa101wa01a", .data = &chunghwa_claa101wa01a},
4505 {.compatible = "chunghwa,claa101wb01", .data = &chunghwa_claa101wb01},
4506 {
4507 .compatible = "dataimage,scf0700c48ggu18",
4508 .data = &dataimage_scf0700c48ggu18,
4509 },
4510 {
4511 .compatible = "dlc,dlc0700yzg-1",
4512 .data = &dlc_dlc0700yzg_1,
4513 },
4514 {
4515 .compatible = "dlc,dlc1010gig",
4516 .data = &dlc_dlc1010gig,
4517 },
4518 {
4519 .compatible = "edt,et035012dm6",
4520 .data = &edt_et035012dm6,
4521 },
4522 {
4523 .compatible = "edt,etm043080dh6gp",
4524 .data = &edt_etm043080dh6gp,
4525 },
4526 {
4527 .compatible = "edt,etm0430g0dh6",
4528 .data = &edt_etm0430g0dh6,
4529 },
4530 {
4531 .compatible = "edt,et057090dhu",
4532 .data = &edt_et057090dhu,
4533 },
4534 {
4535 .compatible = "edt,et070080dh6",
4536 .data = &edt_etm0700g0dh6,
4537 },
4538 {
4539 .compatible = "edt,etm0700g0dh6",
4540 .data = &edt_etm0700g0dh6,
4541 },
4542 {
4543 .compatible = "edt,etm0700g0bdh6",
4544 .data = &edt_etm0700g0bdh6,
4545 },
4546 {
4547 .compatible = "edt,etm0700g0edh6",
4548 .data = &edt_etm0700g0bdh6,
4549 },
4550 {
4551 .compatible = "evervision,vgg804821",
4552 .data = &evervision_vgg804821,
4553 },
4554 {
4555 .compatible = "foxlink,fl500wvr00-a0t",
4556 .data = &foxlink_fl500wvr00_a0t,
4557 },
4558 {
4559 .compatible = "frida,frd350h54004",
4560 .data = &frida_frd350h54004,
4561 },
4562 {
4563 .compatible = "friendlyarm,hd702e",
4564 .data = &friendlyarm_hd702e,
4565 },
4566 {.compatible = "giantplus,gpg482739qs5", .data = &giantplus_gpg482739qs5},
4567 {
4568 .compatible = "giantplus,gpm940b0",
4569 .data = &giantplus_gpm940b0,
4570 },
4571 {
4572 .compatible = "hannstar,hsd070pww1",
4573 .data = &hannstar_hsd070pww1,
4574 },
4575 {
4576 .compatible = "hannstar,hsd100pxn1",
4577 .data = &hannstar_hsd100pxn1,
4578 },
4579 {.compatible = "hit,tx23d38vm0caa", .data = &hitachi_tx23d38vm0caa},
4580 {
4581 .compatible = "innolux,at043tn24",
4582 .data = &innolux_at043tn24,
4583 },
4584 {
4585 .compatible = "innolux,at070tn92",
4586 .data = &innolux_at070tn92,
4587 },
4588 {
4589 .compatible = "innolux,g070y2-l01",
4590 .data = &innolux_g070y2_l01,
4591 },
4592 {.compatible = "innolux,g101ice-l01", .data = &innolux_g101ice_l01},
4593 {.compatible = "innolux,g121i1-l01", .data = &innolux_g121i1_l01},
4594 {
4595 .compatible = "innolux,g121x1-l03",
4596 .data = &innolux_g121x1_l03,
4597 },
4598 {
4599 .compatible = "innolux,n116bge",
4600 .data = &innolux_n116bge,
4601 },
4602 {
4603 .compatible = "innolux,n156bge-l21",
4604 .data = &innolux_n156bge_l21,
4605 },
4606 {
4607 .compatible = "innolux,p120zdg-bf1",
4608 .data = &innolux_p120zdg_bf1,
4609 },
4610 {
4611 .compatible = "innolux,zj070na-01p",
4612 .data = &innolux_zj070na_01p,
4613 },
4614 {
4615 .compatible = "ivo,m133nwf4-r0",
4616 .data = &ivo_m133nwf4_r0,
4617 },
4618 {
4619 .compatible = "kingdisplay,kd116n21-30nv-a010",
4620 .data = &kingdisplay_kd116n21_30nv_a010,
4621 },
4622 {
4623 .compatible = "koe,tx14d24vm1bpa",
4624 .data = &koe_tx14d24vm1bpa,
4625 },
4626 {
4627 .compatible = "koe,tx26d202vm0bwa",
4628 .data = &koe_tx26d202vm0bwa,
4629 },
4630 {
4631 .compatible = "koe,tx31d200vm0baa",
4632 .data = &koe_tx31d200vm0baa,
4633 },
4634 {
4635 .compatible = "kyo,tcg121xglp",
4636 .data = &kyo_tcg121xglp,
4637 },
4638 {
4639 .compatible = "lemaker,bl035-rgb-002",
4640 .data = &lemaker_bl035_rgb_002,
4641 },
4642 {
4643 .compatible = "lg,lb070wv8",
4644 .data = &lg_lb070wv8,
4645 },
4646 {
4647 .compatible = "lg,lp079qx1-sp0v",
4648 .data = &lg_lp079qx1_sp0v,
4649 },
4650 {
4651 .compatible = "lg,lp097qx1-spa1",
4652 .data = &lg_lp097qx1_spa1,
4653 },
4654 {
4655 .compatible = "lg,lp120up1",
4656 .data = &lg_lp120up1,
4657 },
4658 {
4659 .compatible = "lg,lp129qe",
4660 .data = &lg_lp129qe,
4661 },
4662 {
4663 .compatible = "logicpd,type28",
4664 .data = &logicpd_type_28,
4665 },
4666 {
4667 .compatible = "logictechno,lt161010-2nhc",
4668 .data = &logictechno_lt161010_2nh,
4669 },
4670 {
4671 .compatible = "logictechno,lt161010-2nhr",
4672 .data = &logictechno_lt161010_2nh,
4673 },
4674 {
4675 .compatible = "logictechno,lt170410-2whc",
4676 .data = &logictechno_lt170410_2whc,
4677 },
4678 {
4679 .compatible = "mitsubishi,aa070mc01-ca1",
4680 .data = &mitsubishi_aa070mc01,
4681 },
4682 {
4683 .compatible = "nec,nl12880bc20-05",
4684 .data = &nec_nl12880bc20_05,
4685 },
4686 {
4687 .compatible = "nec,nl4827hc19-05b",
4688 .data = &nec_nl4827hc19_05b,
4689 },
4690 {
4691 .compatible = "netron-dy,e231732",
4692 .data = &netron_dy_e231732,
4693 },
4694 {
4695 .compatible = "neweast,wjfh116008a",
4696 .data = &neweast_wjfh116008a,
4697 },
4698 {
4699 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4700 .data = &newhaven_nhd_43_480272ef_atxl,
4701 },
4702 {
4703 .compatible = "nlt,nl192108ac18-02d",
4704 .data = &nlt_nl192108ac18_02d,
4705 },
4706 {
4707 .compatible = "nvd,9128",
4708 .data = &nvd_9128,
4709 },
4710 {
4711 .compatible = "okaya,rs800480t-7x0gp",
4712 .data = &okaya_rs800480t_7x0gp,
4713 },
4714 {
4715 .compatible = "olimex,lcd-olinuxino-43-ts",
4716 .data = &olimex_lcd_olinuxino_43ts,
4717 },
4718 {
4719 .compatible = "ontat,yx700wv03",
4720 .data = &ontat_yx700wv03,
4721 },
4722 {
4723 .compatible = "ortustech,com37h3m05dtc",
4724 .data = &ortustech_com37h3m,
4725 },
4726 {
4727 .compatible = "ortustech,com37h3m99dtc",
4728 .data = &ortustech_com37h3m,
4729 },
4730 {
4731 .compatible = "ortustech,com43h4m85ulc",
4732 .data = &ortustech_com43h4m85ulc,
4733 },
4734 {
4735 .compatible = "osddisplays,osd070t1718-19ts",
4736 .data = &osddisplays_osd070t1718_19ts,
4737 },
4738 {
4739 .compatible = "pda,91-00156-a0",
4740 .data = &pda_91_00156_a0,
4741 },
4742 {
4743 .compatible = "powertip,ph800480t013-idf02",
4744 .data = &powertip_ph800480t013_idf02,
4745 },
4746 {
4747 .compatible = "qiaodian,qd43003c0-40",
4748 .data = &qd43003c0_40,
4749 },
4750 {
4751 .compatible = "rocktech,rk070er9427",
4752 .data = &rocktech_rk070er9427,
4753 },
4754 {
4755 .compatible = "rocktech,rk101ii01d-ct",
4756 .data = &rocktech_rk101ii01d_ct,
4757 },
4758 {
4759 .compatible = "samsung,lsn122dl01-c01",
4760 .data = &samsung_lsn122dl01_c01,
4761 },
4762 {
4763 .compatible = "samsung,ltn101nt05",
4764 .data = &samsung_ltn101nt05,
4765 },
4766 {
4767 .compatible = "samsung,ltn140at29-301",
4768 .data = &samsung_ltn140at29_301,
4769 },
4770 {
4771 .compatible = "satoz,sat050at40h12r2",
4772 .data = &satoz_sat050at40h12r2,
4773 },
4774 {
4775 .compatible = "sharp,ld-d5116z01b",
4776 .data = &sharp_ld_d5116z01b,
4777 },
4778 {
4779 .compatible = "sharp,lq035q7db03",
4780 .data = &sharp_lq035q7db03,
4781 },
4782 {
4783 .compatible = "sharp,lq070y3dg3b",
4784 .data = &sharp_lq070y3dg3b,
4785 },
4786 {
4787 .compatible = "sharp,lq101k1ly04",
4788 .data = &sharp_lq101k1ly04,
4789 },
4790 {
4791 .compatible = "sharp,lq123p1jx31",
4792 .data = &sharp_lq123p1jx31,
4793 },
4794 {
4795 .compatible = "sharp,ls020b1dd01d",
4796 .data = &sharp_ls020b1dd01d,
4797 },
4798 {
4799 .compatible = "shelly,sca07010-bfn-lnn",
4800 .data = &shelly_sca07010_bfn_lnn,
4801 },
4802 {
4803 .compatible = "starry,kr070pe2t",
4804 .data = &starry_kr070pe2t,
4805 },
4806 {
4807 .compatible = "starry,kr122ea0sra",
4808 .data = &starry_kr122ea0sra,
4809 },
4810 {
4811 .compatible = "tfc,s9700rtwv43tr-01b",
4812 .data = &tfc_s9700rtwv43tr_01b,
4813 },
4814 {
4815 .compatible = "tianma,tm070jdhg30",
4816 .data = &tianma_tm070jdhg30,
4817 },
4818 {
4819 .compatible = "tianma,tm070jvhg33",
4820 .data = &tianma_tm070jvhg33,
4821 },
4822 {
4823 .compatible = "tianma,tm070rvhg71",
4824 .data = &tianma_tm070rvhg71,
4825 },
4826 {
4827 .compatible = "ti,nspire-cx-lcd-panel",
4828 .data = &ti_nspire_cx_lcd_panel,
4829 },
4830 {
4831 .compatible = "ti,nspire-classic-lcd-panel",
4832 .data = &ti_nspire_classic_lcd_panel,
4833 },
4834 {
4835 .compatible = "toshiba,lt089ac29000",
4836 .data = &toshiba_lt089ac29000,
4837 },
4838 {
4839 .compatible = "tpk,f07a-0102",
4840 .data = &tpk_f07a_0102,
4841 },
4842 {
4843 .compatible = "tpk,f10a-0102",
4844 .data = &tpk_f10a_0102,
4845 },
4846 {
4847 .compatible = "urt,umsh-8596md-t",
4848 .data = &urt_umsh_8596md_parallel,
4849 },
4850 {
4851 .compatible = "urt,umsh-8596md-1t",
4852 .data = &urt_umsh_8596md_parallel,
4853 },
4854 {
4855 .compatible = "urt,umsh-8596md-7t",
4856 .data = &urt_umsh_8596md_parallel,
4857 },
4858 {
4859 .compatible = "urt,umsh-8596md-11t",
4860 .data = &urt_umsh_8596md_lvds,
4861 },
4862 {
4863 .compatible = "urt,umsh-8596md-19t",
4864 .data = &urt_umsh_8596md_lvds,
4865 },
4866 {
4867 .compatible = "urt,umsh-8596md-20t",
4868 .data = &urt_umsh_8596md_parallel,
4869 },
4870 {
4871 .compatible = "vxt,vl050-8048nt-c01",
4872 .data = &vl050_8048nt_c01,
4873 },
4874 {
4875 .compatible = "winstar,wf35ltiacd",
4876 .data = &winstar_wf35ltiacd,
4877 },
4878 {
4879 /* Must be the last entry */
4880 .compatible = "panel-dpi",
4881 .data = &panel_dpi,
4882 },
4883 {
4884 /* sentinel */
4885 }};
4886 MODULE_DEVICE_TABLE(of, platform_of_match);
4887
of_child_node_is_present(const struct device_node *node, const char *name)4888 static bool of_child_node_is_present(const struct device_node *node, const char *name)
4889 {
4890 struct device_node *child;
4891
4892 child = of_get_child_by_name(node, name);
4893 of_node_put(child);
4894
4895 return !!child;
4896 }
4897
panel_simple_of_get_desc_data(struct device *dev, struct panel_desc *desc)4898 static int panel_simple_of_get_desc_data(struct device *dev, struct panel_desc *desc)
4899 {
4900 struct device_node *np = dev->of_node;
4901 u32 bus_flags;
4902 const void *data;
4903 int len;
4904 int err;
4905
4906 if (of_child_node_is_present(np, "display-timings")) {
4907 struct drm_display_mode *mode;
4908
4909 mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
4910 if (!mode) {
4911 return -ENOMEM;
4912 }
4913
4914 if (!of_get_drm_display_mode(np, mode, &bus_flags, OF_USE_NATIVE_MODE)) {
4915 desc->modes = mode;
4916 desc->num_modes = 1;
4917 desc->bus_flags = bus_flags;
4918 }
4919 } else if (of_child_node_is_present(np, "panel-timing")) {
4920 struct display_timing *timing;
4921 struct videomode vm;
4922
4923 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
4924 if (!timing) {
4925 return -ENOMEM;
4926 }
4927
4928 if (!of_get_display_timing(np, "panel-timing", timing)) {
4929 desc->timings = timing;
4930 desc->num_timings = 1;
4931
4932 bus_flags = 0;
4933 vm.flags = timing->flags;
4934 drm_bus_flags_from_videomode(&vm, &bus_flags);
4935 desc->bus_flags = bus_flags;
4936 }
4937 }
4938
4939 if (desc->num_modes || desc->num_timings) {
4940 of_property_read_u32(np, "bpc", &desc->bpc);
4941 of_property_read_u32(np, "bus-format", &desc->bus_format);
4942 of_property_read_u32(np, "width-mm", &desc->size.width);
4943 of_property_read_u32(np, "height-mm", &desc->size.height);
4944 }
4945
4946 of_property_read_u32(np, "prepare-delay-ms", &desc->delay.prepare);
4947 of_property_read_u32(np, "enable-delay-ms", &desc->delay.enable);
4948 of_property_read_u32(np, "disable-delay-ms", &desc->delay.disable);
4949 of_property_read_u32(np, "unprepare-delay-ms", &desc->delay.unprepare);
4950 of_property_read_u32(np, "reset-delay-ms", &desc->delay.reset);
4951 of_property_read_u32(np, "init-delay-ms", &desc->delay.init);
4952
4953 data = of_get_property(np, "panel-init-sequence", &len);
4954 if (data) {
4955 desc->init_seq = devm_kzalloc(dev, sizeof(*desc->init_seq), GFP_KERNEL);
4956 if (!desc->init_seq) {
4957 return -ENOMEM;
4958 }
4959
4960 err = panel_simple_parse_cmd_seq(dev, data, len, desc->init_seq);
4961 if (err) {
4962 dev_err(dev, "failed to parse init sequence\n");
4963 return err;
4964 }
4965 }
4966
4967 data = of_get_property(np, "panel-exit-sequence", &len);
4968 if (data) {
4969 desc->exit_seq = devm_kzalloc(dev, sizeof(*desc->exit_seq), GFP_KERNEL);
4970 if (!desc->exit_seq) {
4971 return -ENOMEM;
4972 }
4973
4974 err = panel_simple_parse_cmd_seq(dev, data, len, desc->exit_seq);
4975 if (err) {
4976 dev_err(dev, "failed to parse exit sequence\n");
4977 return err;
4978 }
4979 }
4980
4981 return 0;
4982 }
4983
panel_simple_platform_probe(struct platform_device *pdev)4984 static int panel_simple_platform_probe(struct platform_device *pdev)
4985 {
4986 struct device *dev = &pdev->dev;
4987 const struct of_device_id *id;
4988 const struct panel_desc *desc;
4989 struct panel_desc *d;
4990 int err;
4991
4992 id = of_match_node(platform_of_match, pdev->dev.of_node);
4993 if (!id) {
4994 return -ENODEV;
4995 }
4996
4997 if (!id->data) {
4998 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
4999 if (!d) {
5000 return -ENOMEM;
5001 }
5002
5003 err = panel_simple_of_get_desc_data(dev, d);
5004 if (err) {
5005 dev_err(dev, "failed to get desc data: %d\n", err);
5006 return err;
5007 }
5008 }
5009
5010 desc = id->data ? id->data : d;
5011
5012 return panel_simple_probe(&pdev->dev, desc);
5013 }
5014
panel_simple_platform_remove(struct platform_device *pdev)5015 static int panel_simple_platform_remove(struct platform_device *pdev)
5016 {
5017 return panel_simple_remove(&pdev->dev);
5018 }
5019
panel_simple_platform_shutdown(struct platform_device *pdev)5020 static void panel_simple_platform_shutdown(struct platform_device *pdev)
5021 {
5022 panel_simple_shutdown(&pdev->dev);
5023 }
5024
5025 static struct platform_driver panel_simple_platform_driver = {
5026 .driver =
5027 {
5028 .name = "panel-simple",
5029 .of_match_table = platform_of_match,
5030 },
5031 .probe = panel_simple_platform_probe,
5032 .remove = panel_simple_platform_remove,
5033 .shutdown = panel_simple_platform_shutdown,
5034 };
5035
5036 struct panel_desc_dsi {
5037 struct panel_desc desc;
5038
5039 unsigned long flags;
5040 enum mipi_dsi_pixel_format format;
5041 unsigned int lanes;
5042 };
5043
5044 static const struct drm_display_mode auo_b080uan01_mode = {
5045 .clock = 154500,
5046 .hdisplay = 1200,
5047 .hsync_start = 1200 + 62,
5048 .hsync_end = 1200 + 62 + 4,
5049 .htotal = 1200 + 62 + 4 + 62,
5050 .vdisplay = 1920,
5051 .vsync_start = 1920 + 9,
5052 .vsync_end = 1920 + 9 + 2,
5053 .vtotal = 1920 + 9 + 2 + 8,
5054 };
5055
5056 static const struct panel_desc_dsi auo_b080uan01 = {
5057 .desc =
5058 {
5059 .modes = &auo_b080uan01_mode,
5060 .num_modes = 1,
5061 .bpc = 8,
5062 .size =
5063 {
5064 .width = 108,
5065 .height = 272,
5066 },
5067 .connector_type = DRM_MODE_CONNECTOR_DSI,
5068 },
5069 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5070 .format = MIPI_DSI_FMT_RGB888,
5071 .lanes = 4,
5072 };
5073
5074 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
5075 .clock = 160000,
5076 .hdisplay = 1200,
5077 .hsync_start = 1200 + 120,
5078 .hsync_end = 1200 + 120 + 20,
5079 .htotal = 1200 + 120 + 20 + 21,
5080 .vdisplay = 1920,
5081 .vsync_start = 1920 + 21,
5082 .vsync_end = 1920 + 21 + 3,
5083 .vtotal = 1920 + 21 + 3 + 18,
5084 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
5085 };
5086
5087 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
5088 .desc =
5089 {
5090 .modes = &boe_tv080wum_nl0_mode,
5091 .num_modes = 1,
5092 .size =
5093 {
5094 .width = 107,
5095 .height = 172,
5096 },
5097 .connector_type = DRM_MODE_CONNECTOR_DSI,
5098 },
5099 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
5100 .format = MIPI_DSI_FMT_RGB888,
5101 .lanes = 4,
5102 };
5103
5104 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
5105 .clock = 71000,
5106 .hdisplay = 800,
5107 .hsync_start = 800 + 32,
5108 .hsync_end = 800 + 32 + 1,
5109 .htotal = 800 + 32 + 1 + 57,
5110 .vdisplay = 1280,
5111 .vsync_start = 1280 + 28,
5112 .vsync_end = 1280 + 28 + 1,
5113 .vtotal = 1280 + 28 + 1 + 14,
5114 };
5115
5116 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
5117 .desc =
5118 {
5119 .modes = &lg_ld070wx3_sl01_mode,
5120 .num_modes = 1,
5121 .bpc = 8,
5122 .size =
5123 {
5124 .width = 94,
5125 .height = 151,
5126 },
5127 .connector_type = DRM_MODE_CONNECTOR_DSI,
5128 },
5129 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5130 .format = MIPI_DSI_FMT_RGB888,
5131 .lanes = 4,
5132 };
5133
5134 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
5135 .clock = 67000,
5136 .hdisplay = 720,
5137 .hsync_start = 720 + 12,
5138 .hsync_end = 720 + 12 + 4,
5139 .htotal = 720 + 12 + 4 + 112,
5140 .vdisplay = 1280,
5141 .vsync_start = 1280 + 8,
5142 .vsync_end = 1280 + 8 + 4,
5143 .vtotal = 1280 + 8 + 4 + 12,
5144 };
5145
5146 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
5147 .desc =
5148 {
5149 .modes = &lg_lh500wx1_sd03_mode,
5150 .num_modes = 1,
5151 .bpc = 8,
5152 .size =
5153 {
5154 .width = 62,
5155 .height = 110,
5156 },
5157 .connector_type = DRM_MODE_CONNECTOR_DSI,
5158 },
5159 .flags = MIPI_DSI_MODE_VIDEO,
5160 .format = MIPI_DSI_FMT_RGB888,
5161 .lanes = 4,
5162 };
5163
5164 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5165 .clock = 157200,
5166 .hdisplay = 1920,
5167 .hsync_start = 1920 + 154,
5168 .hsync_end = 1920 + 154 + 16,
5169 .htotal = 1920 + 154 + 16 + 32,
5170 .vdisplay = 1200,
5171 .vsync_start = 1200 + 17,
5172 .vsync_end = 1200 + 17 + 2,
5173 .vtotal = 1200 + 17 + 2 + 16,
5174 };
5175
5176 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5177 .desc =
5178 {
5179 .modes = &panasonic_vvx10f004b00_mode,
5180 .num_modes = 1,
5181 .bpc = 8,
5182 .size =
5183 {
5184 .width = 217,
5185 .height = 136,
5186 },
5187 .connector_type = DRM_MODE_CONNECTOR_DSI,
5188 },
5189 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5190 .format = MIPI_DSI_FMT_RGB888,
5191 .lanes = 4,
5192 };
5193
5194 static const struct drm_display_mode lg_acx467akm_7_mode = {
5195 .clock = 150000,
5196 .hdisplay = 1080,
5197 .hsync_start = 1080 + 2,
5198 .hsync_end = 1080 + 2 + 2,
5199 .htotal = 1080 + 2 + 2 + 2,
5200 .vdisplay = 1920,
5201 .vsync_start = 1920 + 2,
5202 .vsync_end = 1920 + 2 + 2,
5203 .vtotal = 1920 + 2 + 2 + 2,
5204 };
5205
5206 static const struct panel_desc_dsi lg_acx467akm_7 = {
5207 .desc =
5208 {
5209 .modes = &lg_acx467akm_7_mode,
5210 .num_modes = 1,
5211 .bpc = 8,
5212 .size =
5213 {
5214 .width = 62,
5215 .height = 110,
5216 },
5217 .connector_type = DRM_MODE_CONNECTOR_DSI,
5218 },
5219 .flags = 0,
5220 .format = MIPI_DSI_FMT_RGB888,
5221 .lanes = 4,
5222 };
5223
5224 static const struct drm_display_mode osd101t2045_53ts_mode = {
5225 .clock = 154500,
5226 .hdisplay = 1920,
5227 .hsync_start = 1920 + 112,
5228 .hsync_end = 1920 + 112 + 16,
5229 .htotal = 1920 + 112 + 16 + 32,
5230 .vdisplay = 1200,
5231 .vsync_start = 1200 + 16,
5232 .vsync_end = 1200 + 16 + 2,
5233 .vtotal = 1200 + 16 + 2 + 16,
5234 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5235 };
5236
5237 static const struct panel_desc_dsi osd101t2045_53ts = {
5238 .desc =
5239 {
5240 .modes = &osd101t2045_53ts_mode,
5241 .num_modes = 1,
5242 .bpc = 8,
5243 .size =
5244 {
5245 .width = 217,
5246 .height = 136,
5247 },
5248 .connector_type = DRM_MODE_CONNECTOR_DSI,
5249 },
5250 .flags =
5251 MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_EOT_PACKET,
5252 .format = MIPI_DSI_FMT_RGB888,
5253 .lanes = 4,
5254 };
5255
5256 static const struct of_device_id dsi_of_match[] = {
5257 {
5258 .compatible = "simple-panel-dsi",
5259 .data = NULL,
5260 },
5261 {.compatible = "auo,b080uan01", .data = &auo_b080uan01},
5262 {.compatible = "boe,tv080wum-nl0", .data = &boe_tv080wum_nl0},
5263 {.compatible = "lg,ld070wx3-sl01", .data = &lg_ld070wx3_sl01},
5264 {.compatible = "lg,lh500wx1-sd03", .data = &lg_lh500wx1_sd03},
5265 {.compatible = "panasonic,vvx10f004b00", .data = &panasonic_vvx10f004b00},
5266 {.compatible = "lg,acx467akm-7", .data = &lg_acx467akm_7},
5267 {.compatible = "osddisplays,osd101t2045-53ts", .data = &osd101t2045_53ts},
5268 {
5269 /* sentinel */
5270 }};
5271 MODULE_DEVICE_TABLE(of, dsi_of_match);
5272
panel_simple_dsi_of_get_desc_data(struct device *dev, struct panel_desc_dsi *desc)5273 static int panel_simple_dsi_of_get_desc_data(struct device *dev, struct panel_desc_dsi *desc)
5274 {
5275 struct device_node *np = dev->of_node;
5276 u32 val;
5277 int err;
5278
5279 err = panel_simple_of_get_desc_data(dev, &desc->desc);
5280 if (err) {
5281 return err;
5282 }
5283
5284 if (!of_property_read_u32(np, "dsi,flags", &val)) {
5285 desc->flags = val;
5286 }
5287 if (!of_property_read_u32(np, "dsi,format", &val)) {
5288 desc->format = val;
5289 }
5290 if (!of_property_read_u32(np, "dsi,lanes", &val)) {
5291 desc->lanes = val;
5292 }
5293
5294 return 0;
5295 }
5296
panel_simple_dsi_probe(struct mipi_dsi_device *dsi)5297 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5298 {
5299 struct panel_simple *panel;
5300 struct device *dev = &dsi->dev;
5301 const struct panel_desc_dsi *desc;
5302 struct panel_desc_dsi *d;
5303 const struct of_device_id *id;
5304 int err;
5305
5306 id = of_match_node(dsi_of_match, dsi->dev.of_node);
5307 if (!id) {
5308 return -ENODEV;
5309 }
5310
5311 if (!id->data) {
5312 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
5313 if (!d) {
5314 return -ENOMEM;
5315 }
5316
5317 err = panel_simple_dsi_of_get_desc_data(dev, d);
5318 if (err) {
5319 dev_err(dev, "failed to get desc data: %d\n", err);
5320 return err;
5321 }
5322 }
5323
5324 desc = id->data ? id->data : d;
5325
5326 err = panel_simple_probe(&dsi->dev, &desc->desc);
5327 if (err < 0) {
5328 return err;
5329 }
5330
5331 panel = dev_get_drvdata(dev);
5332 panel->dsi = dsi;
5333
5334 if (!panel->base.backlight) {
5335 struct backlight_properties props;
5336
5337 memset(&props, 0, sizeof(props));
5338 props.type = BACKLIGHT_RAW;
5339 props.brightness = 0xff;
5340 props.max_brightness = 0xff;
5341
5342 panel->base.backlight = devm_backlight_device_register(dev, "dcs-backlight", dev, panel, &dcs_bl_ops, &props);
5343 if (IS_ERR(panel->base.backlight)) {
5344 err = PTR_ERR(panel->base.backlight);
5345 dev_err(dev, "failed to register dcs backlight: %d\n", err);
5346 return err;
5347 }
5348 }
5349
5350 dsi->mode_flags = desc->flags;
5351 dsi->format = desc->format;
5352 dsi->lanes = desc->lanes;
5353
5354 err = mipi_dsi_attach(dsi);
5355 if (err) {
5356 struct panel_simple *panel_ex = dev_get_drvdata(&dsi->dev);
5357
5358 drm_panel_remove(&panel_ex->base);
5359 }
5360
5361 return err;
5362 }
5363
panel_simple_dsi_remove(struct mipi_dsi_device *dsi)5364 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5365 {
5366 int err;
5367
5368 err = mipi_dsi_detach(dsi);
5369 if (err < 0) {
5370 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5371 }
5372
5373 return panel_simple_remove(&dsi->dev);
5374 }
5375
panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)5376 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5377 {
5378 panel_simple_shutdown(&dsi->dev);
5379 }
5380
5381 static struct mipi_dsi_driver panel_simple_dsi_driver = {
5382 .driver =
5383 {
5384 .name = "panel-simple-dsi",
5385 .of_match_table = dsi_of_match,
5386 },
5387 .probe = panel_simple_dsi_probe,
5388 .remove = panel_simple_dsi_remove,
5389 .shutdown = panel_simple_dsi_shutdown,
5390 };
5391
panel_simple_init(void)5392 static int __init panel_simple_init(void)
5393 {
5394 int err;
5395
5396 err = platform_driver_register(&panel_simple_platform_driver);
5397 if (err < 0) {
5398 return err;
5399 }
5400
5401 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5402 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5403 if (err < 0) {
5404 return err;
5405 }
5406 }
5407
5408 return 0;
5409 }
5410 module_init(panel_simple_init);
5411
panel_simple_exit(void)5412 static void __exit panel_simple_exit(void)
5413 {
5414 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5415 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5416 }
5417
5418 platform_driver_unregister(&panel_simple_platform_driver);
5419 }
5420 module_exit(panel_simple_exit);
5421
5422 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5423 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5424 MODULE_LICENSE("GPL and additional rights");
5425