1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 *
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/extcon.h>
13 #include <linux/extcon-provider.h>
14 #include <linux/hdmi.h>
15 #include <linux/irq.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/of_device.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/regmap.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spinlock.h>
23 #include <linux/pinctrl/consumer.h>
24
25 #include <media/cec-notifier.h>
26
27 #include <uapi/linux/media-bus-format.h>
28 #include <uapi/linux/videodev2.h>
29
30 #include <drm/bridge/dw_hdmi.h>
31 #include <drm/drm_atomic.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_bridge.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_of.h>
36 #include <drm/drm_print.h>
37 #include <drm/drm_probe_helper.h>
38 #include <drm/drm_scdc_helper.h>
39
40 #include "dw-hdmi-audio.h"
41 #include "dw-hdmi-cec.h"
42 #include "dw-hdmi-hdcp.h"
43 #include "dw-hdmi.h"
44
45 #define DDC_CI_ADDR 0x37
46 #define DDC_SEGMENT_ADDR 0x30
47
48 #define HDMI_EDID_LEN 512
49
50 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
51 #define SCDC_MIN_SOURCE_VERSION 0x1
52
53 #define HDMI14_MAX_TMDSCLK 340000000
54
55 static const unsigned int dw_hdmi_cable[] = {
56 EXTCON_DISP_HDMI,
57 EXTCON_NONE,
58 };
59
60 enum hdmi_datamap {
61 RGB444_8B = 0x01,
62 RGB444_10B = 0x03,
63 RGB444_12B = 0x05,
64 RGB444_16B = 0x07,
65 YCbCr444_8B = 0x09,
66 YCbCr444_10B = 0x0B,
67 YCbCr444_12B = 0x0D,
68 YCbCr444_16B = 0x0F,
69 YCbCr422_8B = 0x16,
70 YCbCr422_10B = 0x14,
71 YCbCr422_12B = 0x12,
72 };
73
74 /*
75 * Unless otherwise noted, entries in this table are 100% optimization.
76 * Values can be obtained from hdmi_compute_n() but that function is
77 * slow so we pre-compute values we expect to see.
78 *
79 * All 32k and 48k values are expected to be the same (due to the way
80 * the math works) for any rate that's an exact kHz.
81 */
82 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
83 {
84 .tmds = 25175000,
85 .n_32k = 4096,
86 .n_44k1 = 12854,
87 .n_48k = 6144,
88 },
89 {
90 .tmds = 25200000,
91 .n_32k = 4096,
92 .n_44k1 = 5656,
93 .n_48k = 6144,
94 },
95 {
96 .tmds = 27000000,
97 .n_32k = 4096,
98 .n_44k1 = 5488,
99 .n_48k = 6144,
100 },
101 {
102 .tmds = 28320000,
103 .n_32k = 4096,
104 .n_44k1 = 5586,
105 .n_48k = 6144,
106 },
107 {
108 .tmds = 30240000,
109 .n_32k = 4096,
110 .n_44k1 = 5642,
111 .n_48k = 6144,
112 },
113 {
114 .tmds = 31500000,
115 .n_32k = 4096,
116 .n_44k1 = 5600,
117 .n_48k = 6144,
118 },
119 {
120 .tmds = 32000000,
121 .n_32k = 4096,
122 .n_44k1 = 5733,
123 .n_48k = 6144,
124 },
125 {
126 .tmds = 33750000,
127 .n_32k = 4096,
128 .n_44k1 = 6272,
129 .n_48k = 6144,
130 },
131 {
132 .tmds = 36000000,
133 .n_32k = 4096,
134 .n_44k1 = 5684,
135 .n_48k = 6144,
136 },
137 {
138 .tmds = 40000000,
139 .n_32k = 4096,
140 .n_44k1 = 5733,
141 .n_48k = 6144,
142 },
143 {
144 .tmds = 49500000,
145 .n_32k = 4096,
146 .n_44k1 = 5488,
147 .n_48k = 6144,
148 },
149 {
150 .tmds = 50000000,
151 .n_32k = 4096,
152 .n_44k1 = 5292,
153 .n_48k = 6144,
154 },
155 {
156 .tmds = 54000000,
157 .n_32k = 4096,
158 .n_44k1 = 5684,
159 .n_48k = 6144,
160 },
161 {
162 .tmds = 65000000,
163 .n_32k = 4096,
164 .n_44k1 = 7056,
165 .n_48k = 6144,
166 },
167 {
168 .tmds = 68250000,
169 .n_32k = 4096,
170 .n_44k1 = 5376,
171 .n_48k = 6144,
172 },
173 {
174 .tmds = 71000000,
175 .n_32k = 4096,
176 .n_44k1 = 7056,
177 .n_48k = 6144,
178 },
179 {
180 .tmds = 72000000,
181 .n_32k = 4096,
182 .n_44k1 = 5635,
183 .n_48k = 6144,
184 },
185 {
186 .tmds = 73250000,
187 .n_32k = 4096,
188 .n_44k1 = 14112,
189 .n_48k = 6144,
190 },
191 {
192 .tmds = 74250000,
193 .n_32k = 4096,
194 .n_44k1 = 6272,
195 .n_48k = 6144,
196 },
197 {
198 .tmds = 75000000,
199 .n_32k = 4096,
200 .n_44k1 = 5880,
201 .n_48k = 6144,
202 },
203 {
204 .tmds = 78750000,
205 .n_32k = 4096,
206 .n_44k1 = 5600,
207 .n_48k = 6144,
208 },
209 {
210 .tmds = 78800000,
211 .n_32k = 4096,
212 .n_44k1 = 5292,
213 .n_48k = 6144,
214 },
215 {
216 .tmds = 79500000,
217 .n_32k = 4096,
218 .n_44k1 = 4704,
219 .n_48k = 6144,
220 },
221 {
222 .tmds = 83500000,
223 .n_32k = 4096,
224 .n_44k1 = 7056,
225 .n_48k = 6144,
226 },
227 {
228 .tmds = 85500000,
229 .n_32k = 4096,
230 .n_44k1 = 5488,
231 .n_48k = 6144,
232 },
233 {
234 .tmds = 88750000,
235 .n_32k = 4096,
236 .n_44k1 = 14112,
237 .n_48k = 6144,
238 },
239 {
240 .tmds = 97750000,
241 .n_32k = 4096,
242 .n_44k1 = 14112,
243 .n_48k = 6144,
244 },
245 {
246 .tmds = 101000000,
247 .n_32k = 4096,
248 .n_44k1 = 7056,
249 .n_48k = 6144,
250 },
251 {
252 .tmds = 106500000,
253 .n_32k = 4096,
254 .n_44k1 = 4704,
255 .n_48k = 6144,
256 },
257 {
258 .tmds = 108000000,
259 .n_32k = 4096,
260 .n_44k1 = 5684,
261 .n_48k = 6144,
262 },
263 {
264 .tmds = 115500000,
265 .n_32k = 4096,
266 .n_44k1 = 5712,
267 .n_48k = 6144,
268 },
269 {
270 .tmds = 119000000,
271 .n_32k = 4096,
272 .n_44k1 = 5544,
273 .n_48k = 6144,
274 },
275 {
276 .tmds = 135000000,
277 .n_32k = 4096,
278 .n_44k1 = 5488,
279 .n_48k = 6144,
280 },
281 {
282 .tmds = 146250000,
283 .n_32k = 4096,
284 .n_44k1 = 6272,
285 .n_48k = 6144,
286 },
287 {
288 .tmds = 148500000,
289 .n_32k = 4096,
290 .n_44k1 = 5488,
291 .n_48k = 6144,
292 },
293 {
294 .tmds = 154000000,
295 .n_32k = 4096,
296 .n_44k1 = 5544,
297 .n_48k = 6144,
298 },
299 {
300 .tmds = 162000000,
301 .n_32k = 4096,
302 .n_44k1 = 5684,
303 .n_48k = 6144,
304 },
305
306 /* For 297 MHz+ HDMI spec have some other rule for setting N */
307 {
308 .tmds = 297000000,
309 .n_32k = 3073,
310 .n_44k1 = 4704,
311 .n_48k = 5120,
312 },
313 {
314 .tmds = 594000000,
315 .n_32k = 3073,
316 .n_44k1 = 9408,
317 .n_48k = 10240,
318 },
319
320 /* End of table */
321 {
322 .tmds = 0,
323 .n_32k = 0,
324 .n_44k1 = 0,
325 .n_48k = 0,
326 },
327 };
328
329 static const u16 csc_coeff_default[3][4] = {
330 {0x2000, 0x0000, 0x0000, 0x0000}, {0x0000, 0x2000, 0x0000, 0x0000}, {0x0000, 0x0000, 0x2000, 0x0000}};
331
332 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
333 {0x2000, 0x6926, 0x74fd, 0x010e}, {0x2000, 0x2cdd, 0x0000, 0x7e9a}, {0x2000, 0x0000, 0x38b4, 0x7e3b}};
334
335 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
336 {0x2000, 0x7106, 0x7a02, 0x00a7}, {0x2000, 0x3264, 0x0000, 0x7e6d}, {0x2000, 0x0000, 0x3b61, 0x7e25}};
337
338 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
339 {0x2591, 0x1322, 0x074b, 0x0000}, {0x6535, 0x2000, 0x7acc, 0x0200}, {0x6acd, 0x7534, 0x2000, 0x0200}};
340
341 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
342 {0x2dc5, 0x0d9b, 0x049e, 0x0000}, {0x62f0, 0x2000, 0x7d11, 0x0200}, {0x6756, 0x78ab, 0x2000, 0x0200}};
343
344 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
345 {0x1b7c, 0x0000, 0x0000, 0x0020}, {0x0000, 0x1b7c, 0x0000, 0x0020}, {0x0000, 0x0000, 0x1b7c, 0x0020}};
346
347 static const struct drm_display_mode dw_hdmi_default_modes[] = {
348 /* 4 - 1280x720@60Hz 16:9 */
349 {
350 DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
353 },
354 /* 16 - 1920x1080@60Hz 16:9 */
355 {
356 DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
359 },
360 /* 31 - 1920x1080@50Hz 16:9 */
361 {
362 DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
365 },
366 /* 19 - 1280x720@50Hz 16:9 */
367 {
368 DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
371 },
372 /* 17 - 720x576@50Hz 4:3 */
373 {
374 DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
377 },
378 /* 2 - 720x480@60Hz 4:3 */
379 {
380 DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
382 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
383 },
384 };
385
386 struct hdmi_vmode {
387 bool mdataenablepolarity;
388
389 unsigned int previous_pixelclock;
390 unsigned int mpixelclock;
391 unsigned int mpixelrepetitioninput;
392 unsigned int mpixelrepetitionoutput;
393 unsigned int previous_tmdsclock;
394 unsigned int mtmdsclock;
395 };
396
397 struct hdmi_data_info {
398 unsigned int enc_in_bus_format;
399 unsigned int enc_out_bus_format;
400 unsigned int enc_in_encoding;
401 unsigned int enc_out_encoding;
402 unsigned int quant_range;
403 unsigned int pix_repet_factor;
404 struct hdmi_vmode video_mode;
405 bool rgb_limited_range;
406 };
407
408 struct dw_hdmi_i2c {
409 struct i2c_adapter adap;
410
411 struct mutex lock; /* used to serialize data transfers */
412 struct completion cmp;
413 u8 stat;
414
415 u8 slave_reg;
416 bool is_regaddr;
417 bool is_segment;
418
419 unsigned int scl_high_ns;
420 unsigned int scl_low_ns;
421 };
422
423 struct dw_hdmi_phy_data {
424 enum dw_hdmi_phy_type type;
425 const char *name;
426 unsigned int gen;
427 bool has_svsret;
428 int (*configure)(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata, unsigned long mpixelclock);
429 };
430
431 struct dw_hdmi {
432 struct drm_connector connector;
433 struct drm_bridge bridge;
434 struct drm_bridge *next_bridge;
435 struct platform_device *hdcp_dev;
436
437 unsigned int version;
438
439 struct platform_device *audio;
440 struct platform_device *cec;
441 struct device *dev;
442 struct clk *isfr_clk;
443 struct clk *iahb_clk;
444 struct clk *cec_clk;
445 struct dw_hdmi_i2c *i2c;
446
447 struct hdmi_data_info hdmi_data;
448 const struct dw_hdmi_plat_data *plat_data;
449 struct dw_hdcp *hdcp;
450
451 int vic;
452 int irq;
453
454 u8 edid[HDMI_EDID_LEN];
455
456 struct {
457 const struct dw_hdmi_phy_ops *ops;
458 const char *name;
459 void *data;
460 bool enabled;
461 } phy;
462
463 struct drm_display_mode previous_mode;
464
465 struct i2c_adapter *ddc;
466 void __iomem *regs;
467 bool sink_is_hdmi;
468 bool sink_has_audio;
469 bool hpd_state;
470 bool support_hdmi;
471 bool force_logo;
472 int force_output;
473
474 struct delayed_work work;
475 struct workqueue_struct *workqueue;
476
477 struct pinctrl *pinctrl;
478 struct pinctrl_state *default_state;
479 struct pinctrl_state *unwedge_state;
480
481 struct mutex mutex; /* for state below and previous_mode */
482 enum drm_connector_force force; /* mutex-protected force state */
483 struct drm_connector *curr_conn; /* current connector (only valid when !disabled) */
484 bool disabled; /* DRM has disabled our bridge */
485 bool bridge_is_on; /* indicates the bridge is on */
486 bool rxsense; /* rxsense state */
487 u8 phy_mask; /* desired phy int mask settings */
488 u8 mc_clkdis; /* clock disable register */
489
490 spinlock_t audio_lock;
491 struct mutex audio_mutex;
492 struct dentry *debugfs_dir;
493 unsigned int sample_rate;
494 unsigned int audio_cts;
495 unsigned int audio_n;
496 bool audio_enable;
497 bool scramble_low_rates;
498
499 struct extcon_dev *extcon;
500
501 unsigned int reg_shift;
502 struct regmap *regm;
503 void (*enable_audio)(struct dw_hdmi *hdmi);
504 void (*disable_audio)(struct dw_hdmi *hdmi);
505
506 struct mutex cec_notifier_mutex;
507 struct cec_notifier *cec_notifier;
508 struct cec_adapter *cec_adap;
509
510 hdmi_codec_plugged_cb plugged_cb;
511 struct device *codec_dev;
512 enum drm_connector_status last_connector_result;
513 bool initialized; /* hdmi is enabled before bind */
514 };
515
516 #define HDMI_IH_PHY_STAT0_RX_SENSE \
517 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | HDMI_IH_PHY_STAT0_RX_SENSE2 | \
518 HDMI_IH_PHY_STAT0_RX_SENSE3)
519
520 #define HDMI_PHY_RX_SENSE (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
521
hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)522 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
523 {
524 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
525 }
526
hdmi_readb(struct dw_hdmi *hdmi, int offset)527 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
528 {
529 unsigned int val = 0;
530
531 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
532
533 return val;
534 }
535
handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)536 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
537 {
538 if (hdmi->plugged_cb && hdmi->codec_dev) {
539 hdmi->plugged_cb(hdmi->codec_dev, plugged);
540 }
541 }
542
dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, struct device *codec_dev)543 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, struct device *codec_dev)
544 {
545 bool plugged;
546
547 mutex_lock(&hdmi->mutex);
548 hdmi->plugged_cb = fn;
549 hdmi->codec_dev = codec_dev;
550 plugged = hdmi->last_connector_result == connector_status_connected;
551 handle_plugged_change(hdmi, plugged);
552 mutex_unlock(&hdmi->mutex);
553
554 return 0;
555 }
556 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
557
hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)558 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
559 {
560 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
561 }
562
hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, u8 shift, u8 mask)563 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, u8 shift, u8 mask)
564 {
565 hdmi_modb(hdmi, data << shift, mask, reg);
566 }
567
dw_hdmi_check_output_type_changed(struct dw_hdmi *hdmi)568 static bool dw_hdmi_check_output_type_changed(struct dw_hdmi *hdmi)
569 {
570 bool sink_hdmi;
571
572 sink_hdmi = hdmi->sink_is_hdmi;
573
574 if (hdmi->force_output == 1) {
575 hdmi->sink_is_hdmi = true;
576 } else if (hdmi->force_output == 0x2) {
577 hdmi->sink_is_hdmi = false;
578 } else {
579 hdmi->sink_is_hdmi = hdmi->support_hdmi;
580 }
581
582 if (sink_hdmi != hdmi->sink_is_hdmi) {
583 return true;
584 }
585
586 return false;
587 }
588
repo_hpd_event(struct work_struct *p_work)589 static void repo_hpd_event(struct work_struct *p_work)
590 {
591 struct dw_hdmi *hdmi = container_of(p_work, struct dw_hdmi, work.work);
592 enum drm_connector_status status = hdmi->hpd_state ? connector_status_connected : connector_status_disconnected;
593 u8 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
594
595 mutex_lock(&hdmi->mutex);
596 if (!(phy_stat & HDMI_PHY_RX_SENSE)) {
597 hdmi->rxsense = false;
598 }
599 if (phy_stat & HDMI_PHY_HPD) {
600 hdmi->rxsense = true;
601 }
602 mutex_unlock(&hdmi->mutex);
603
604 if (hdmi->bridge.dev) {
605 bool change;
606
607 change = drm_helper_hpd_irq_event(hdmi->bridge.dev);
608 if (change && hdmi->cec_adap && hdmi->cec_adap->devnode.registered) {
609 cec_queue_pin_hpd_event(hdmi->cec_adap, hdmi->hpd_state, ktime_get());
610 }
611 drm_bridge_hpd_notify(&hdmi->bridge, status);
612 }
613 }
614
check_hdmi_irq(struct dw_hdmi *hdmi, int intr_stat, int phy_int_pol)615 static bool check_hdmi_irq(struct dw_hdmi *hdmi, int intr_stat, int phy_int_pol)
616 {
617 int msecs;
618
619 /* To determine whether interrupt type is HPD */
620 if (!(intr_stat & HDMI_IH_PHY_STAT0_HPD)) {
621 return false;
622 }
623
624 if (phy_int_pol & HDMI_PHY_HPD) {
625 dev_dbg(hdmi->dev, "dw hdmi plug in\n");
626 msecs = 150;
627 hdmi->hpd_state = true;
628 } else {
629 dev_dbg(hdmi->dev, "dw hdmi plug out\n");
630 msecs = 20;
631 hdmi->hpd_state = false;
632 }
633 mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(msecs));
634
635 return true;
636 }
637
init_hpd_work(struct dw_hdmi *hdmi)638 static void init_hpd_work(struct dw_hdmi *hdmi)
639 {
640 hdmi->workqueue = create_workqueue("hpd_queue");
641 INIT_DELAYED_WORK(&hdmi->work, repo_hpd_event);
642 }
643
dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)644 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)
645 {
646 unsigned long clk_rate_khz;
647 unsigned long low_ns, high_ns;
648 unsigned long div_low, div_high;
649
650 /* Standard-mode */
651 if (hdmi->i2c->scl_high_ns < 4000) {
652 high_ns = 4708;
653 } else {
654 high_ns = hdmi->i2c->scl_high_ns;
655 }
656
657 if (hdmi->i2c->scl_low_ns < 4700) {
658 low_ns = 4916;
659 } else {
660 low_ns = hdmi->i2c->scl_low_ns;
661 }
662
663 /* Adjust to avoid overflow */
664 clk_rate_khz = DIV_ROUND_UP(clk_get_rate(hdmi->isfr_clk), 1000);
665
666 div_low = (clk_rate_khz * low_ns) / 1000000;
667 if ((clk_rate_khz * low_ns) % 1000000) {
668 div_low++;
669 }
670
671 div_high = (clk_rate_khz * high_ns) / 1000000;
672 if ((clk_rate_khz * high_ns) % 1000000) {
673 div_high++;
674 }
675
676 /* Maximum divider supported by hw is 0xffff */
677 if (div_low > 0xffff) {
678 div_low = 0xffff;
679 }
680
681 if (div_high > 0xffff) {
682 div_high = 0xffff;
683 }
684
685 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
686 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
687 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
688 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
689 }
690
dw_hdmi_i2c_init(struct dw_hdmi *hdmi)691 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
692 {
693 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, HDMI_PHY_I2CM_INT_ADDR);
694
695 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
696 HDMI_PHY_I2CM_CTLINT_ADDR);
697
698 /* Software reset */
699 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
700
701 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
702 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
703
704 /* Set done, not acknowledged and arbitration interrupt polarities */
705 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
706 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, HDMI_I2CM_CTLINT);
707
708 /* Clear DONE and ERROR interrupts */
709 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, HDMI_IH_I2CM_STAT0);
710
711 /* Mute DONE and ERROR interrupts */
712 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, HDMI_IH_MUTE_I2CM_STAT0);
713
714 /* set SDA high level holding time */
715 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
716
717 dw_hdmi_i2c_set_divs(hdmi);
718 }
719
dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)720 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
721 {
722 /* If no unwedge state then give up */
723 if (!hdmi->unwedge_state) {
724 return false;
725 }
726
727 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
728
729 /*
730 * This is a huge hack to workaround a problem where the dw_hdmi i2c
731 * bus could sometimes get wedged. Once wedged there doesn't appear
732 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
733 * other than pulsing the SDA line.
734 *
735 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
736 * by:
737 * 1. Remux the pin as a GPIO output, driven low.
738 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
739 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
740 *
741 * At the moment of remuxing, the line will still be low due to its
742 * recent stint as an output, but then it will be pulled high by the
743 * (presumed) external pullup. dw_hdmi seems to see this as a rising
744 * edge and that seems to get it out of its jam.
745 *
746 * This wedging was only ever seen on one TV, and only on one of
747 * its HDMI ports. It happened when the TV was powered on while the
748 * device was plugged in. A scope trace shows the TV bringing both SDA
749 * and SCL low, then bringing them both back up at roughly the same
750 * time. Presumably this confuses dw_hdmi because it saw activity but
751 * no real STOP (maybe it thinks there's another master on the bus?).
752 * Giving it a clean rising edge of SDA while SCL is already high
753 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
754 * of its stupor.
755 *
756 * Note that after coming back alive, transfers seem to immediately
757 * resume, so if we unwedge due to a timeout we should wait a little
758 * longer for our transfer to finish, since it might have just started
759 * now.
760 */
761 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
762 msleep(10);
763 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
764
765 return true;
766 }
767
dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)768 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
769 {
770 struct dw_hdmi_i2c *i2c = hdmi->i2c;
771 int stat;
772
773 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
774 if (!stat) {
775 /* If we can't unwedge, return timeout */
776 if (!dw_hdmi_i2c_unwedge(hdmi)) {
777 return -EAGAIN;
778 }
779
780 /* We tried to unwedge; give it another chance */
781 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
782 if (!stat) {
783 return -EAGAIN;
784 }
785 }
786
787 /* Check for error condition on the bus */
788 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) {
789 return -EIO;
790 }
791
792 return 0;
793 }
794
dw_hdmi_i2c_read(struct dw_hdmi *hdmi, unsigned char *buf, unsigned int length)795 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, unsigned char *buf, unsigned int length)
796 {
797 struct dw_hdmi_i2c *i2c = hdmi->i2c;
798 int ret;
799
800 if (!i2c->is_regaddr) {
801 dev_dbg(hdmi->dev, "set read register address to 0\n");
802 i2c->slave_reg = 0x00;
803 i2c->is_regaddr = true;
804 }
805
806 while (length--) {
807 reinit_completion(&i2c->cmp);
808
809 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
810 if (i2c->is_segment) {
811 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, HDMI_I2CM_OPERATION);
812 } else {
813 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, HDMI_I2CM_OPERATION);
814 }
815
816 ret = dw_hdmi_i2c_wait(hdmi);
817 if (ret) {
818 return ret;
819 }
820
821 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
822 }
823 i2c->is_segment = false;
824
825 return 0;
826 }
827
dw_hdmi_i2c_write(struct dw_hdmi *hdmi, unsigned char *buf, unsigned int length)828 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, unsigned char *buf, unsigned int length)
829 {
830 struct dw_hdmi_i2c *i2c = hdmi->i2c;
831 int ret;
832
833 if (!i2c->is_regaddr) {
834 /* Use the first write byte as register address */
835 i2c->slave_reg = buf[0];
836 length--;
837 buf++;
838 i2c->is_regaddr = true;
839 }
840
841 while (length--) {
842 reinit_completion(&i2c->cmp);
843
844 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
845 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
846 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, HDMI_I2CM_OPERATION);
847
848 ret = dw_hdmi_i2c_wait(hdmi);
849 if (ret) {
850 return ret;
851 }
852 }
853
854 return 0;
855 }
856
dw_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)857 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
858 {
859 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
860 struct dw_hdmi_i2c *i2c = hdmi->i2c;
861 u8 addr = msgs[0].addr;
862 int i, ret = 0;
863
864 if (addr == DDC_CI_ADDR) {
865 /*
866 * The internal I2C controller does not support the multi-byte
867 * read and write operations needed for DDC/CI.
868 * TOFIX: Blacklist the DDC/CI address until we filter out
869 * unsupported I2C operations.
870 */
871 return -EOPNOTSUPP;
872 }
873
874 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
875
876 for (i = 0; i < num; i++) {
877 if (msgs[i].len == 0) {
878 dev_dbg(hdmi->dev, "unsupported transfer %d/%d, no data\n", i + 1, num);
879 return -EOPNOTSUPP;
880 }
881 }
882
883 mutex_lock(&i2c->lock);
884
885 /* Unmute DONE and ERROR interrupts */
886 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
887
888 /* Set slave device address taken from the first I2C message */
889 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) {
890 addr = DDC_ADDR;
891 }
892 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
893
894 /* Set slave device register address on transfer */
895 i2c->is_regaddr = false;
896
897 /* Set segment pointer for I2C extended read mode operation */
898 i2c->is_segment = false;
899
900 for (i = 0; i < num; i++) {
901 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", i + 1, num, msgs[i].len, msgs[i].flags);
902 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
903 i2c->is_segment = true;
904 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
905 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
906 } else {
907 if (msgs[i].flags & I2C_M_RD) {
908 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
909 } else {
910 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
911 }
912 }
913 if (ret < 0) {
914 break;
915 }
916 }
917
918 if (!ret) {
919 ret = num;
920 }
921
922 /* Mute DONE and ERROR interrupts */
923 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, HDMI_IH_MUTE_I2CM_STAT0);
924
925 mutex_unlock(&i2c->lock);
926
927 return ret;
928 }
929
dw_hdmi_i2c_func(struct i2c_adapter *adapter)930 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
931 {
932 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
933 }
934
935 static const struct i2c_algorithm dw_hdmi_algorithm = {
936 .master_xfer = dw_hdmi_i2c_xfer,
937 .functionality = dw_hdmi_i2c_func,
938 };
939
dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)940 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
941 {
942 struct i2c_adapter *adap;
943 struct dw_hdmi_i2c *i2c;
944 int ret;
945
946 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
947 if (!i2c) {
948 return ERR_PTR(-ENOMEM);
949 }
950
951 mutex_init(&i2c->lock);
952 init_completion(&i2c->cmp);
953
954 adap = &i2c->adap;
955 adap->class = I2C_CLASS_DDC;
956 adap->owner = THIS_MODULE;
957 adap->dev.parent = hdmi->dev;
958 adap->algo = &dw_hdmi_algorithm;
959 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
960 i2c_set_adapdata(adap, hdmi);
961
962 ret = i2c_add_adapter(adap);
963 if (ret) {
964 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
965 devm_kfree(hdmi->dev, i2c);
966 return ERR_PTR(ret);
967 }
968
969 hdmi->i2c = i2c;
970
971 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
972
973 return adap;
974 }
975
hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, unsigned int n)976 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, unsigned int n)
977 {
978 /* Must be set/cleared first */
979 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
980
981 /* nshift factor = 0 */
982 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
983
984 /* Use automatic CTS generation mode when CTS is not set */
985 if (cts) {
986 hdmi_writeb(hdmi, ((cts >> 0x10) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
987 } else {
988 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
989 }
990 hdmi_writeb(hdmi, (cts >> 0x8) & 0xff, HDMI_AUD_CTS2);
991 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
992
993 hdmi_writeb(hdmi, (n >> 0x10) & 0x0f, HDMI_AUD_N3);
994 hdmi_writeb(hdmi, (n >> 0x8) & 0xff, HDMI_AUD_N2);
995 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
996 }
997
hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned long freq)998 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned long freq)
999 {
1000 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
1001 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
1002 int i;
1003
1004 if (plat_data->tmds_n_table) {
1005 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
1006 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
1007 tmds_n = &plat_data->tmds_n_table[i];
1008 break;
1009 }
1010 }
1011 }
1012
1013 if (tmds_n == NULL) {
1014 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
1015 if (pixel_clk == common_tmds_n_table[i].tmds) {
1016 tmds_n = &common_tmds_n_table[i];
1017 break;
1018 }
1019 }
1020 }
1021
1022 if (tmds_n == NULL) {
1023 return -ENOENT;
1024 }
1025
1026 switch (freq) {
1027 case 0x7d00:
1028 return tmds_n->n_32k;
1029 case 0xac44:
1030 case 0x15888:
1031 case 0x2b110:
1032 return (freq / 0xac44) * tmds_n->n_44k1;
1033 case 0xbb80:
1034 case 0x17700:
1035 case 0x2ee00:
1036 return (freq / 0xbb80) * tmds_n->n_48k;
1037 default:
1038 return -ENOENT;
1039 }
1040 }
1041
hdmi_audio_math_diff(unsigned int freq, unsigned int n, unsigned int pixel_clk)1042 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, unsigned int pixel_clk)
1043 {
1044 u64 final, diff;
1045 u64 cts;
1046
1047 final = (u64)pixel_clk * n;
1048
1049 cts = final;
1050 do_div(cts, 0x80 * freq);
1051
1052 diff = final - (u64)cts * (0x80 * freq);
1053
1054 return diff;
1055 }
1056
hdmi_compute_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned long freq)1057 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned long freq)
1058 {
1059 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
1060 unsigned int max_n = (128 * freq) / 300;
1061 unsigned int ideal_n = (128 * freq) / 1000;
1062 unsigned int best_n_distance = ideal_n;
1063 unsigned int best_n = 0;
1064 u64 best_diff = U64_MAX;
1065 int n;
1066
1067 /* If the ideal N could satisfy the audio math, then just take it */
1068 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) {
1069 return ideal_n;
1070 }
1071
1072 for (n = min_n; n <= max_n; n++) {
1073 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
1074 if (diff < best_diff || (diff == best_diff && abs(n - ideal_n) < best_n_distance)) {
1075 best_n = n;
1076 best_diff = diff;
1077 best_n_distance = abs(best_n - ideal_n);
1078 }
1079
1080 /*
1081 * The best N already satisfy the audio math, and also be
1082 * the closest value to ideal N, so just cut the loop.
1083 */
1084 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) {
1085 break;
1086 }
1087 }
1088
1089 return best_n;
1090 }
1091
hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned long sample_rate)1092 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned long sample_rate)
1093 {
1094 int n;
1095
1096 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
1097 if (n > 0) {
1098 return n;
1099 }
1100
1101 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", pixel_clk);
1102
1103 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
1104 }
1105
1106 /*
1107 * When transmitting IEC60958 linear PCM audio, these registers allow to
1108 * configure the channel status information of all the channel status
1109 * bits in the IEC60958 frame. For the moment this configuration is only
1110 * used when the I2S audio interface, General Purpose Audio (GPA),
1111 * or AHB audio DMA (AHBAUDDMA) interface is active
1112 * (for S/PDIF interface this information comes from the stream).
1113 */
dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status)1114 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status)
1115 {
1116 /*
1117 * Set channel status register for frequency and word length.
1118 * Use default values for other registers.
1119 */
1120 hdmi_writeb(hdmi, channel_status[0x3], HDMI_FC_AUDSCHNLS7);
1121 hdmi_writeb(hdmi, channel_status[0x4], HDMI_FC_AUDSCHNLS8);
1122 }
1123 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
1124
hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate)1125 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate)
1126 {
1127 unsigned long ftdms = pixel_clk;
1128 unsigned int n, cts;
1129 u8 config3;
1130 u64 tmp;
1131
1132 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
1133
1134 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
1135 /* Only compute CTS when using internal AHB audio */
1136 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
1137 /*
1138 * Compute the CTS value from the N value. Note that CTS and N
1139 * can be up to 20 bits in total, so we need 64-bit math. Also
1140 * note that our TDMS clock is not fully accurate; it is
1141 * accurate to kHz. This can introduce an unnecessary remainder
1142 * in the calculation below, so we don't try to warn about that.
1143 */
1144 tmp = (u64)ftdms * n;
1145 do_div(tmp, 0x80 * sample_rate);
1146 cts = tmp;
1147
1148 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, sample_rate, ftdms / 0xf4240,
1149 (ftdms / 0x3e8) % 0x3e8, n, cts);
1150 } else {
1151 cts = 0;
1152 }
1153
1154 spin_lock_irq(&hdmi->audio_lock);
1155 hdmi->audio_n = n;
1156 hdmi->audio_cts = cts;
1157 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
1158 spin_unlock_irq(&hdmi->audio_lock);
1159 }
1160
hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)1161 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
1162 {
1163 mutex_lock(&hdmi->audio_mutex);
1164 hdmi_set_clk_regenerator(hdmi, 0x46cf710, hdmi->sample_rate);
1165 mutex_unlock(&hdmi->audio_mutex);
1166 }
1167
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)1168 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
1169 {
1170 mutex_lock(&hdmi->audio_mutex);
1171 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, hdmi->sample_rate);
1172 mutex_unlock(&hdmi->audio_mutex);
1173 }
1174
dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)1175 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
1176 {
1177 mutex_lock(&hdmi->audio_mutex);
1178 hdmi->sample_rate = rate;
1179 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, hdmi->sample_rate);
1180 mutex_unlock(&hdmi->audio_mutex);
1181 }
1182 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
1183
dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)1184 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
1185 {
1186 u8 layout;
1187
1188 mutex_lock(&hdmi->audio_mutex);
1189
1190 /*
1191 * For >2 channel PCM audio, we need to select layout 1
1192 * and set an appropriate channel map.
1193 */
1194 if (cnt > 0x2) {
1195 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
1196 } else {
1197 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
1198 }
1199
1200 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, HDMI_FC_AUDSCONF);
1201
1202 /* Set the audio infoframes channel count */
1203 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
1204
1205 mutex_unlock(&hdmi->audio_mutex);
1206 }
1207 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
1208
dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)1209 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
1210 {
1211 mutex_lock(&hdmi->audio_mutex);
1212
1213 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
1214
1215 mutex_unlock(&hdmi->audio_mutex);
1216 }
1217 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
1218
hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)1219 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
1220 {
1221 if (enable) {
1222 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
1223 } else {
1224 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
1225 }
1226 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1227 }
1228
hdmi_audio_get_eld(struct dw_hdmi *hdmi)1229 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
1230 {
1231 if (!hdmi->curr_conn)
1232 return NULL;
1233 return hdmi->curr_conn->eld;
1234 }
1235
dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)1236 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
1237 {
1238 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
1239 }
1240
dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)1241 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
1242 {
1243 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
1244 }
1245
dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)1246 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
1247 {
1248 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
1249 hdmi_enable_audio_clk(hdmi, true);
1250 }
1251
dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)1252 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
1253 {
1254 hdmi_enable_audio_clk(hdmi, false);
1255 }
1256
dw_hdmi_audio_enable(struct dw_hdmi *hdmi)1257 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
1258 {
1259 unsigned long flags;
1260
1261 spin_lock_irqsave(&hdmi->audio_lock, flags);
1262 hdmi->audio_enable = true;
1263 if (hdmi->enable_audio) {
1264 hdmi->enable_audio(hdmi);
1265 }
1266 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
1267 }
1268 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
1269
dw_hdmi_audio_disable(struct dw_hdmi *hdmi)1270 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
1271 {
1272 unsigned long flags;
1273
1274 spin_lock_irqsave(&hdmi->audio_lock, flags);
1275 hdmi->audio_enable = false;
1276 if (hdmi->disable_audio) {
1277 hdmi->disable_audio(hdmi);
1278 }
1279 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
1280 }
1281 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
1282
hdmi_bus_fmt_is_rgb(unsigned int bus_format)1283 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
1284 {
1285 switch (bus_format) {
1286 case MEDIA_BUS_FMT_RGB888_1X24:
1287 case MEDIA_BUS_FMT_RGB101010_1X30:
1288 case MEDIA_BUS_FMT_RGB121212_1X36:
1289 case MEDIA_BUS_FMT_RGB161616_1X48:
1290 return true;
1291
1292 default:
1293 return false;
1294 }
1295 }
1296
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)1297 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
1298 {
1299 switch (bus_format) {
1300 case MEDIA_BUS_FMT_YUV8_1X24:
1301 case MEDIA_BUS_FMT_YUV10_1X30:
1302 case MEDIA_BUS_FMT_YUV12_1X36:
1303 case MEDIA_BUS_FMT_YUV16_1X48:
1304 return true;
1305
1306 default:
1307 return false;
1308 }
1309 }
1310
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)1311 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
1312 {
1313 switch (bus_format) {
1314 case MEDIA_BUS_FMT_UYVY8_1X16:
1315 case MEDIA_BUS_FMT_UYVY10_1X20:
1316 case MEDIA_BUS_FMT_UYVY12_1X24:
1317 return true;
1318
1319 default:
1320 return false;
1321 }
1322 }
1323
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)1324 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
1325 {
1326 switch (bus_format) {
1327 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1328 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1329 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
1330 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
1331 return true;
1332
1333 default:
1334 return false;
1335 }
1336 }
1337
hdmi_bus_fmt_color_depth(unsigned int bus_format)1338 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
1339 {
1340 switch (bus_format) {
1341 case MEDIA_BUS_FMT_RGB888_1X24:
1342 case MEDIA_BUS_FMT_YUV8_1X24:
1343 case MEDIA_BUS_FMT_UYVY8_1X16:
1344 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1345 return 0x8;
1346
1347 case MEDIA_BUS_FMT_RGB101010_1X30:
1348 case MEDIA_BUS_FMT_YUV10_1X30:
1349 case MEDIA_BUS_FMT_UYVY10_1X20:
1350 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1351 return 0xa;
1352
1353 case MEDIA_BUS_FMT_RGB121212_1X36:
1354 case MEDIA_BUS_FMT_YUV12_1X36:
1355 case MEDIA_BUS_FMT_UYVY12_1X24:
1356 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
1357 return 0xc;
1358
1359 case MEDIA_BUS_FMT_RGB161616_1X48:
1360 case MEDIA_BUS_FMT_YUV16_1X48:
1361 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
1362 return 0x10;
1363
1364 default:
1365 return 0;
1366 }
1367 }
1368
1369 /*
1370 * this submodule is responsible for the video data synchronization.
1371 * for example, for RGB 4:4:4 input, the data map is defined as
1372 * pin{47~40} <==> R[7:0]
1373 * pin{31~24} <==> G[7:0]
1374 * pin{15~8} <==> B[7:0]
1375 */
hdmi_video_sample(struct dw_hdmi *hdmi)1376 static void hdmi_video_sample(struct dw_hdmi *hdmi)
1377 {
1378 int color_format = 0;
1379 u8 val;
1380
1381 switch (hdmi->hdmi_data.enc_in_bus_format) {
1382 case MEDIA_BUS_FMT_RGB888_1X24:
1383 color_format = 0x01;
1384 break;
1385 case MEDIA_BUS_FMT_RGB101010_1X30:
1386 color_format = 0x03;
1387 break;
1388 case MEDIA_BUS_FMT_RGB121212_1X36:
1389 color_format = 0x05;
1390 break;
1391 case MEDIA_BUS_FMT_RGB161616_1X48:
1392 color_format = 0x07;
1393 break;
1394
1395 case MEDIA_BUS_FMT_YUV8_1X24:
1396 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1397 color_format = 0x09;
1398 break;
1399 case MEDIA_BUS_FMT_YUV10_1X30:
1400 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1401 color_format = 0x0B;
1402 break;
1403 case MEDIA_BUS_FMT_YUV12_1X36:
1404 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
1405 color_format = 0x0D;
1406 break;
1407 case MEDIA_BUS_FMT_YUV16_1X48:
1408 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
1409 color_format = 0x0F;
1410 break;
1411
1412 case MEDIA_BUS_FMT_UYVY8_1X16:
1413 color_format = 0x16;
1414 break;
1415 case MEDIA_BUS_FMT_UYVY10_1X20:
1416 color_format = 0x14;
1417 break;
1418 case MEDIA_BUS_FMT_UYVY12_1X24:
1419 color_format = 0x12;
1420 break;
1421
1422 default:
1423 return;
1424 }
1425
1426 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
1427 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
1428 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
1429
1430 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
1431 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
1432 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
1433 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
1434 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
1435 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
1436 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
1437 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
1438 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
1439 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
1440 }
1441
is_color_space_conversion(struct dw_hdmi *hdmi)1442 static int is_color_space_conversion(struct dw_hdmi *hdmi)
1443 {
1444 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1445 bool is_input_rgb, is_output_rgb;
1446
1447 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
1448 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
1449
1450 return (is_input_rgb != is_output_rgb) || (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
1451 }
1452
is_color_space_decimation(struct dw_hdmi *hdmi)1453 static int is_color_space_decimation(struct dw_hdmi *hdmi)
1454 {
1455 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1456 return 0;
1457 }
1458
1459 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
1460 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) {
1461 return 1;
1462 }
1463
1464 return 0;
1465 }
1466
is_color_space_interpolation(struct dw_hdmi *hdmi)1467 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
1468 {
1469 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) {
1470 return 0;
1471 }
1472
1473 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1474 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
1475 return 1;
1476 }
1477
1478 return 0;
1479 }
1480
is_csc_needed(struct dw_hdmi *hdmi)1481 static bool is_csc_needed(struct dw_hdmi *hdmi)
1482 {
1483 return is_color_space_conversion(hdmi) || is_color_space_decimation(hdmi) || is_color_space_interpolation(hdmi);
1484 }
1485
is_rgb_full_to_limited_needed(struct dw_hdmi *hdmi)1486 static bool is_rgb_full_to_limited_needed(struct dw_hdmi *hdmi)
1487 {
1488 if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED ||
1489 (!hdmi->hdmi_data.quant_range && hdmi->hdmi_data.rgb_limited_range)) {
1490 return true;
1491 }
1492
1493 return false;
1494 }
1495
dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)1496 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1497 {
1498 const u16(*csc_coeff)[3][4] = &csc_coeff_default;
1499 bool is_input_rgb, is_output_rgb;
1500 unsigned i;
1501 u32 csc_scale = 1;
1502
1503 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1504 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1505 if (!is_input_rgb && is_output_rgb) {
1506 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) {
1507 csc_coeff = &csc_coeff_rgb_out_eitu601;
1508 } else {
1509 csc_coeff = &csc_coeff_rgb_out_eitu709;
1510 }
1511 } else if (is_input_rgb && !is_output_rgb) {
1512 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) {
1513 csc_coeff = &csc_coeff_rgb_in_eitu601;
1514 } else {
1515 csc_coeff = &csc_coeff_rgb_in_eitu709;
1516 }
1517 csc_scale = 0;
1518 } else if (is_input_rgb && is_output_rgb && is_rgb_full_to_limited_needed(hdmi)) {
1519 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1520 }
1521
1522 /* The CSC registers are sequential, alternating MSB then LSB */
1523 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1524 u16 coeff_a = (*csc_coeff)[0x0][i];
1525 u16 coeff_b = (*csc_coeff)[0x1][i];
1526 u16 coeff_c = (*csc_coeff)[0x2][i];
1527
1528 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 0x2);
1529 hdmi_writeb(hdmi, coeff_a >> 0x8, HDMI_CSC_COEF_A1_MSB + i * 0x2);
1530 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 0x2);
1531 hdmi_writeb(hdmi, coeff_b >> 0x8, HDMI_CSC_COEF_B1_MSB + i * 0x2);
1532 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 0x2);
1533 hdmi_writeb(hdmi, coeff_c >> 0x8, HDMI_CSC_COEF_C1_MSB + i * 0x2);
1534 }
1535
1536 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, HDMI_CSC_SCALE);
1537 }
1538
hdmi_video_csc(struct dw_hdmi *hdmi)1539 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1540 {
1541 int color_depth = 0;
1542 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1543 int decimation = 0;
1544
1545 /* YCC422 interpolation to 444 mode */
1546 if (is_color_space_interpolation(hdmi)) {
1547 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1548 } else if (is_color_space_decimation(hdmi)) {
1549 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1;
1550 }
1551
1552 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1553 case 0x8:
1554 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1555 break;
1556 case 0xa:
1557 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1558 break;
1559 case 0xc:
1560 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1561 break;
1562 case 0x10:
1563 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1564 break;
1565
1566 default:
1567 return;
1568 }
1569
1570 /* Configure the CSC registers */
1571 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1572 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, HDMI_CSC_SCALE);
1573
1574 dw_hdmi_update_csc_coeffs(hdmi);
1575 }
1576
1577 /*
1578 * HDMI video packetizer is used to packetize the data.
1579 * for example, if input is YCC422 mode or repeater is used,
1580 * data should be repacked this module can be bypassed.
1581 */
hdmi_video_packetize(struct dw_hdmi *hdmi)1582 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1583 {
1584 unsigned int color_depth = 0;
1585 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1586 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1587 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1588 u8 val, vp_conf;
1589
1590 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1591 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1592 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1593 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1594 case 0x8:
1595 color_depth = 0;
1596 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1597 break;
1598 case 0xa:
1599 color_depth = 0x5;
1600 break;
1601 case 0xc:
1602 color_depth = 0x6;
1603 break;
1604 case 0x10:
1605 color_depth = 0x7;
1606 break;
1607 default:
1608 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1609 }
1610 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1611 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1612 case 0x0:
1613 case 0x8:
1614 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1615 break;
1616 case 0xa:
1617 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1618 break;
1619 case 0xc:
1620 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1621 break;
1622
1623 default:
1624 return;
1625 }
1626 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1627 } else {
1628 return;
1629 }
1630
1631 /* set the packetizer registers */
1632 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & HDMI_VP_PR_CD_COLOR_DEPTH_MASK;
1633 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1634
1635 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1636
1637 /* Data from pixel repeater block */
1638 if (hdmi_data->pix_repet_factor > 0) {
1639 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1640 } else { /* data from packetizer block */
1641 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1642 }
1643
1644 hdmi_modb(hdmi, vp_conf, HDMI_VP_CONF_PR_EN_MASK | HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1645
1646 if ((color_depth == 0x5 && hdmi->previous_mode.htotal % 0x4) ||
1647 (color_depth == 0x6 && hdmi->previous_mode.htotal % 0x2)) {
1648 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1649 } else {
1650 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1651 }
1652
1653 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1654
1655 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1656 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | HDMI_VP_CONF_PP_EN_ENABLE | HDMI_VP_CONF_YCC422_EN_DISABLE;
1657 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1658 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_ENABLE;
1659 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1660 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_DISABLE;
1661 } else {
1662 return;
1663 }
1664
1665 hdmi_modb(hdmi, vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
1666 HDMI_VP_CONF);
1667
1668 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1669 HDMI_VP_STUFF_PP_STUFFING_MASK | HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1670
1671 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, HDMI_VP_CONF);
1672 }
1673
1674 /* -----------------------------------------------------------------------------
1675 * Synopsys PHY Handling
1676 */
1677
hdmi_phy_test_clear(struct dw_hdmi *hdmi, unsigned char bit)1678 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, unsigned char bit)
1679 {
1680 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1681 }
1682
hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)1683 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1684 {
1685 u32 val;
1686
1687 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1688 if (msec-- == 0) {
1689 return false;
1690 }
1691 udelay(0x3e8);
1692 }
1693 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1694
1695 return true;
1696 }
1697
dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, unsigned char addr)1698 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, unsigned char addr)
1699 {
1700 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1701 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1702 hdmi_writeb(hdmi, (unsigned char)(data >> 0x8), HDMI_PHY_I2CM_DATAO_1_ADDR);
1703 hdmi_writeb(hdmi, (unsigned char)(data >> 0x0), HDMI_PHY_I2CM_DATAO_0_ADDR);
1704 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, HDMI_PHY_I2CM_OPERATION_ADDR);
1705 hdmi_phy_wait_i2c_done(hdmi, 0x3e8);
1706 }
1707 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1708
1709 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
dw_hdmi_support_scdc(struct dw_hdmi *hdmi, const struct drm_display_info *display)1710 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, const struct drm_display_info *display)
1711 {
1712 /* Completely disable SCDC support for older controllers */
1713 if (hdmi->version < 0x200a) {
1714 return false;
1715 }
1716
1717 /* Disable if no DDC bus */
1718 if (!hdmi->ddc) {
1719 return false;
1720 }
1721
1722 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1723 if (!display->hdmi.scdc.supported || !display->hdmi.scdc.scrambling.supported) {
1724 return false;
1725 }
1726
1727 /*
1728 * Disable if display only support low TMDS rates and scrambling
1729 * for low rates is not supported either
1730 */
1731 if (!display->hdmi.scdc.scrambling.low_rates && display->max_tmds_clock <= 0x53020) {
1732 return false;
1733 }
1734
1735 return true;
1736 }
1737
hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)1738 static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1739 {
1740 int val;
1741
1742 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1743 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1744 hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1745 hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1746 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ, HDMI_PHY_I2CM_OPERATION_ADDR);
1747 hdmi_phy_wait_i2c_done(hdmi, 0x3e8);
1748 val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1749 val = (val & 0xff) << 0x8;
1750 val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1751 return val;
1752 }
1753
1754 /*
1755 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1756 * - The Source shall suspend transmission of the TMDS clock and data
1757 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1758 * from a 0 to a 1 or from a 1 to a 0
1759 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1760 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1761 * transmission of TMDS clock and data
1762 *
1763 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1764 * helper should called right before enabling the TMDS Clock and Data in
1765 * the PHY configuration callback.
1766 */
dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, const struct drm_display_info *display)1767 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, const struct drm_display_info *display)
1768 {
1769 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1770
1771 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1772 if (dw_hdmi_support_scdc(hdmi, display)) {
1773 if (mtmdsclock > HDMI14_MAX_TMDSCLK) {
1774 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1775 } else {
1776 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1777 }
1778 }
1779 }
1780 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1781
dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)1782 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1783 {
1784 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_OFFSET, HDMI_PHY_CONF0_PDZ_MASK);
1785 }
1786
dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)1787 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1788 {
1789 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_OFFSET, HDMI_PHY_CONF0_ENTMDS_MASK);
1790 }
1791
dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)1792 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1793 {
1794 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SVSRET_OFFSET, HDMI_PHY_CONF0_SVSRET_MASK);
1795 }
1796
dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)1797 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1798 {
1799 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1800 }
1801 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1802
dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)1803 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1804 {
1805 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1806 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1807 }
1808 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1809
dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)1810 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1811 {
1812 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1813 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1814 }
1815
dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)1816 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1817 {
1818 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_OFFSET, HDMI_PHY_CONF0_SELDIPIF_MASK);
1819 }
1820
dw_hdmi_phy_reset(struct dw_hdmi *hdmi)1821 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1822 {
1823 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1824 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1825 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1826 }
1827 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1828
dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)1829 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1830 {
1831 hdmi_phy_test_clear(hdmi, 1);
1832 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1833 hdmi_phy_test_clear(hdmi, 0);
1834 }
1835 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1836
dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)1837 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1838 {
1839 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1840 unsigned int i;
1841 u16 val;
1842
1843 if (phy->gen == 1) {
1844 dw_hdmi_phy_enable_tmds(hdmi, 0);
1845 dw_hdmi_phy_enable_powerdown(hdmi, true);
1846 return;
1847 }
1848
1849 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1850
1851 /*
1852 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1853 * to low power mode.
1854 */
1855 for (i = 0; i < 0x5; ++i) {
1856 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1857 if (!(val & HDMI_PHY_TX_PHY_LOCK)) {
1858 break;
1859 }
1860
1861 usleep_range(0x3e8, 0x7d0);
1862 }
1863
1864 if (val & HDMI_PHY_TX_PHY_LOCK) {
1865 dev_warn(hdmi->dev, "PHY failed to power down\n");
1866 } else {
1867 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1868 }
1869
1870 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1871 }
1872
dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)1873 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1874 {
1875 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1876 unsigned int i;
1877 u8 val;
1878
1879 if (phy->gen == 1) {
1880 dw_hdmi_phy_enable_powerdown(hdmi, false);
1881
1882 /* Toggle TMDS enable. */
1883 dw_hdmi_phy_enable_tmds(hdmi, 0);
1884 dw_hdmi_phy_enable_tmds(hdmi, 1);
1885 return 0;
1886 }
1887
1888 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1889 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1890
1891 /* Wait for PHY PLL lock */
1892 for (i = 0; i < 0x5; ++i) {
1893 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1894 if (val) {
1895 break;
1896 }
1897
1898 usleep_range(0x3e8, 0x7d0);
1899 }
1900
1901 if (!val) {
1902 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1903 return -ETIMEDOUT;
1904 }
1905
1906 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1907 return 0;
1908 }
1909
1910 /*
1911 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1912 * information the DWC MHL PHY has the same register layout and is thus also
1913 * supported by this function.
1914 */
hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata, unsigned long mpixelclock)1915 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata,
1916 unsigned long mpixelclock)
1917 {
1918 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1919 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1920 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1921 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1922 unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
1923
1924 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && pdata->mpll_cfg_420) {
1925 mpll_config = pdata->mpll_cfg_420;
1926 }
1927
1928 /* TOFIX Will need 420 specific PHY configuration tables */
1929
1930 /* PLL/MPLL Cfg - always match on final entry */
1931 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) {
1932 if (mpixelclock <= mpll_config->mpixelclock) {
1933 break;
1934 }
1935 }
1936
1937 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) {
1938 if (tmdsclock <= curr_ctrl->mpixelclock) {
1939 break;
1940 }
1941 }
1942
1943 for (; phy_config->mpixelclock != ~0UL; phy_config++) {
1944 if (tmdsclock <= phy_config->mpixelclock) {
1945 break;
1946 }
1947 }
1948
1949 if (mpll_config->mpixelclock == ~0UL || curr_ctrl->mpixelclock == ~0UL || phy_config->mpixelclock == ~0UL) {
1950 return -EINVAL;
1951 }
1952
1953 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1954 depth = fls(depth - 0x8);
1955 } else {
1956 depth = 0;
1957 }
1958 if (depth) {
1959 depth--;
1960 }
1961
1962 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, HDMI_3D_TX_PHY_CPCE_CTRL);
1963 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, HDMI_3D_TX_PHY_GMPCTRL);
1964 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], HDMI_3D_TX_PHY_CURRCTRL);
1965
1966 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1967 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, HDMI_3D_TX_PHY_MSM_CTRL);
1968
1969 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1970 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, HDMI_3D_TX_PHY_CKSYMTXCTRL);
1971 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, HDMI_3D_TX_PHY_VLEVCTRL);
1972
1973 return 0;
1974 }
1975
hdmi_phy_configure(struct dw_hdmi *hdmi, const struct drm_display_info *display)1976 static int hdmi_phy_configure(struct dw_hdmi *hdmi, const struct drm_display_info *display)
1977 {
1978 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1979 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1980 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1981 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1982 int ret;
1983
1984 dw_hdmi_phy_power_off(hdmi);
1985
1986 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1987
1988 /* Leave low power consumption mode by asserting SVSRET. */
1989 if (phy->has_svsret) {
1990 dw_hdmi_phy_enable_svsret(hdmi, 1);
1991 }
1992
1993 dw_hdmi_phy_reset(hdmi);
1994
1995 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1996
1997 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1998
1999 /* Write to the PHY as configured by the platform */
2000 if (pdata->configure_phy) {
2001 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
2002 } else {
2003 ret = phy->configure(hdmi, pdata, mpixelclock);
2004 }
2005 if (ret) {
2006 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", mpixelclock);
2007 return ret;
2008 }
2009
2010 /* Wait for resuming transmission of TMDS clock and data */
2011 if (mtmdsclock > HDMI14_MAX_TMDSCLK) {
2012 msleep(0x64);
2013 }
2014
2015 return dw_hdmi_phy_power_on(hdmi);
2016 }
2017
dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *display, const struct drm_display_mode *mode)2018 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *display,
2019 const struct drm_display_mode *mode)
2020 {
2021 int i, ret;
2022
2023 /* HDMI Phy spec says to do the phy initialization sequence twice */
2024 for (i = 0; i < 0x2; i++) {
2025 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
2026 dw_hdmi_phy_sel_interface_control(hdmi, 0);
2027
2028 ret = hdmi_phy_configure(hdmi, display);
2029 if (ret) {
2030 return ret;
2031 }
2032 }
2033
2034 return 0;
2035 }
2036
dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)2037 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
2038 {
2039 dw_hdmi_phy_power_off(hdmi);
2040 }
2041
dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data)2042 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data)
2043 {
2044 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? connector_status_connected : connector_status_disconnected;
2045 }
2046 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
2047
dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense)2048 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense)
2049 {
2050 u8 old_mask = hdmi->phy_mask;
2051
2052 if (force || disabled || !rxsense) {
2053 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
2054 } else {
2055 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
2056 }
2057
2058 if (old_mask != hdmi->phy_mask) {
2059 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2060 }
2061 }
2062 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
2063
dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)2064 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
2065 {
2066 /*
2067 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
2068 * any pending interrupt.
2069 */
2070 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2071 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, HDMI_IH_PHY_STAT0);
2072
2073 if (!hdmi->next_bridge) {
2074 /* Enable cable hot plug irq. */
2075 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2076
2077 /* Clear and unmute interrupts. */
2078 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, HDMI_IH_PHY_STAT0);
2079 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), HDMI_IH_MUTE_PHY_STAT0);
2080 }
2081 }
2082 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
2083
2084 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
2085 .init = dw_hdmi_phy_init,
2086 .disable = dw_hdmi_phy_disable,
2087 .read_hpd = dw_hdmi_phy_read_hpd,
2088 .update_hpd = dw_hdmi_phy_update_hpd,
2089 .setup_hpd = dw_hdmi_phy_setup_hpd,
2090 };
2091
2092 /* -----------------------------------------------------------------------------
2093 * HDMI TX Setup
2094 */
2095
hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, const struct drm_display_mode *mode)2096 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, const struct drm_display_mode *mode)
2097 {
2098 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
2099 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi;
2100
2101 /* Configure the video polarity */
2102 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH
2103 : HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW;
2104 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH
2105 : HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW;
2106 data_pol =
2107 vmode->mdataenablepolarity ? HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH : HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
2108 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol,
2109 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | HDMI_A_VIDPOLCFG_DATAENPOL_MASK,
2110 HDMI_A_VIDPOLCFG);
2111
2112 /* Config the display mode */
2113 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : HDMI_A_HDCPCFG0_HDMIDVI_DVI;
2114 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, HDMI_A_HDCPCFG0);
2115
2116 if (hdmi->hdcp && hdmi->hdcp->hdcp_start) {
2117 hdmi->hdcp->hdcp_start(hdmi->hdcp);
2118 }
2119 }
2120
hdmi_config_AVI(struct dw_hdmi *hdmi, const struct drm_connector *connector, const struct drm_display_mode *mode)2121 static void hdmi_config_AVI(struct dw_hdmi *hdmi, const struct drm_connector *connector,
2122 const struct drm_display_mode *mode)
2123 {
2124 struct hdmi_avi_infoframe frame;
2125 u8 val;
2126
2127 /* Initialise info frame from DRM mode */
2128 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
2129
2130 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
2131 /* default range */
2132 if (!hdmi->hdmi_data.quant_range) {
2133 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
2134 hdmi->hdmi_data.rgb_limited_range ? HDMI_QUANTIZATION_RANGE_LIMITED
2135 : HDMI_QUANTIZATION_RANGE_FULL);
2136 } else {
2137 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, hdmi->hdmi_data.quant_range);
2138 }
2139 } else {
2140 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
2141 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
2142 }
2143
2144 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
2145 frame.colorspace = HDMI_COLORSPACE_YUV444;
2146 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
2147 frame.colorspace = HDMI_COLORSPACE_YUV422;
2148 } else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
2149 frame.colorspace = HDMI_COLORSPACE_YUV420;
2150 } else {
2151 frame.colorspace = HDMI_COLORSPACE_RGB;
2152 }
2153
2154 /* Set up colorimetry */
2155 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
2156 switch (hdmi->hdmi_data.enc_out_encoding) {
2157 case V4L2_YCBCR_ENC_601:
2158 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) {
2159 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
2160 } else {
2161 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
2162 }
2163 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
2164 break;
2165 case V4L2_YCBCR_ENC_709:
2166 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) {
2167 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
2168 } else {
2169 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
2170 }
2171 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
2172 break;
2173 case V4L2_YCBCR_ENC_BT2020:
2174 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) {
2175 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
2176 } else {
2177 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
2178 }
2179 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_BT2020;
2180 break;
2181 default: /* Carries no data */
2182 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
2183 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
2184 break;
2185 }
2186 } else {
2187 frame.colorimetry = HDMI_COLORIMETRY_NONE;
2188 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
2189 }
2190
2191 /*
2192 * The Designware IP uses a different byte format from standard
2193 * AVI info frames, though generally the bits are in the correct
2194 * bytes.
2195 */
2196
2197 /*
2198 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
2199 * scan info in bits 4,5 rather than 0,1 and active aspect present in
2200 * bit 6 rather than 4.
2201 */
2202 val = ((frame.scan_mode & 0x3) << 0x4) | (frame.colorspace & 0x3);
2203 if (frame.active_aspect & 0xf) {
2204 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
2205 }
2206 if (frame.top_bar || frame.bottom_bar) {
2207 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
2208 }
2209 if (frame.left_bar || frame.right_bar) {
2210 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
2211 }
2212 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
2213
2214 /* AVI data byte 2 differences: none */
2215 val = ((frame.colorimetry & 0x3) << 0x6) | ((frame.picture_aspect & 0x3) << 0x4) | (frame.active_aspect & 0xf);
2216 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
2217
2218 /* AVI data byte 3 differences: none */
2219 val = ((frame.extended_colorimetry & 0x7) << 0x4) | ((frame.quantization_range & 0x3) << 0x2) | (frame.nups & 0x3);
2220 if (frame.itc) {
2221 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
2222 }
2223 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
2224
2225 /* AVI data byte 4 differences: none */
2226 val = frame.video_code & 0x7f;
2227 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
2228
2229 /* AVI Data Byte 5- set up input and output pixel repetition */
2230 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
2231 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
2232 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
2233 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
2234 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
2235
2236 /*
2237 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
2238 * ycc range in bits 2,3 rather than 6,7
2239 */
2240 val = ((frame.ycc_quantization_range & 0x3) << 0x2) | (frame.content_type & 0x3);
2241 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
2242
2243 /* AVI Data Bytes 6-13 */
2244 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
2245 hdmi_writeb(hdmi, (frame.top_bar >> 0x8) & 0xff, HDMI_FC_AVIETB1);
2246 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
2247 hdmi_writeb(hdmi, (frame.bottom_bar >> 0x8) & 0xff, HDMI_FC_AVISBB1);
2248 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
2249 hdmi_writeb(hdmi, (frame.left_bar >> 0x8) & 0xff, HDMI_FC_AVIELB1);
2250 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
2251 hdmi_writeb(hdmi, (frame.right_bar >> 0x8) & 0xff, HDMI_FC_AVISRB1);
2252 }
2253
hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, const struct drm_connector *connector, const struct drm_display_mode *mode)2254 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, const struct drm_connector *connector,
2255 const struct drm_display_mode *mode)
2256 {
2257 struct hdmi_vendor_infoframe frame;
2258 u8 buffer[10];
2259 ssize_t err;
2260
2261 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector, mode);
2262 if (err < 0) {
2263 /*
2264 * Going into that statement does not means vendor infoframe
2265 * fails. It just informed us that vendor infoframe is not
2266 * needed for the selected mode. Only 4k or stereoscopic 3D
2267 * mode requires vendor infoframe. So just simply return.
2268 */
2269 return;
2270 }
2271
2272 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
2273 if (err < 0) {
2274 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", err);
2275 return;
2276 }
2277 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, HDMI_FC_DATAUTO0_VSD_MASK);
2278
2279 /* Set the length of HDMI vendor specific InfoFrame payload */
2280 hdmi_writeb(hdmi, buffer[0x2], HDMI_FC_VSDSIZE);
2281
2282 /* Set 24bit IEEE Registration Identifier */
2283 hdmi_writeb(hdmi, buffer[0x4], HDMI_FC_VSDIEEEID0);
2284 hdmi_writeb(hdmi, buffer[0x5], HDMI_FC_VSDIEEEID1);
2285 hdmi_writeb(hdmi, buffer[0x6], HDMI_FC_VSDIEEEID2);
2286
2287 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
2288 hdmi_writeb(hdmi, buffer[0x7], HDMI_FC_VSDPAYLOAD0);
2289 hdmi_writeb(hdmi, buffer[0x8], HDMI_FC_VSDPAYLOAD1);
2290
2291 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) {
2292 hdmi_writeb(hdmi, buffer[0x9], HDMI_FC_VSDPAYLOAD2);
2293 }
2294
2295 /* Packet frame interpolation */
2296 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
2297
2298 /* Auto packets per frame and line spacing */
2299 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
2300
2301 /* Configures the Frame Composer On RDRB mode */
2302 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, HDMI_FC_DATAUTO0_VSD_MASK);
2303 }
2304
hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, const struct drm_connector *connector)2305 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, const struct drm_connector *connector)
2306 {
2307 const struct drm_connector_state *conn_state = connector->state;
2308 struct hdr_output_metadata *hdr_metadata;
2309 struct hdmi_drm_infoframe frame;
2310 u8 buffer[0x1e];
2311 ssize_t err;
2312 int i;
2313
2314 /* Dynamic Range and Mastering Infoframe is introduced in v2.11a. */
2315 if (hdmi->version < 0x211a) {
2316 DRM_ERROR("Not support DRM Infoframe\n");
2317 return;
2318 }
2319
2320 if (!hdmi->plat_data->use_drm_infoframe) {
2321 return;
2322 }
2323
2324 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
2325
2326 if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
2327 DRM_DEBUG("No need to set HDR metadata in infoframe\n");
2328 return;
2329 }
2330
2331 if (!conn_state->hdr_output_metadata) {
2332 DRM_DEBUG("source metadata not set yet\n");
2333 return;
2334 }
2335
2336 hdr_metadata = (struct hdr_output_metadata *)conn_state->hdr_output_metadata->data;
2337
2338 if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf & BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
2339 DRM_ERROR("Not support EOTF %d\n", hdr_metadata->hdmi_metadata_type1.eotf);
2340 return;
2341 }
2342
2343 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
2344 if (err < 0) {
2345 return;
2346 }
2347
2348 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
2349 if (err < 0) {
2350 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
2351 return;
2352 }
2353
2354 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
2355 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
2356
2357 for (i = 0; i < frame.length; i++) {
2358 hdmi_writeb(hdmi, buffer[0x4 + i], HDMI_FC_DRM_PB0 + i);
2359 }
2360
2361 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
2362 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
2363
2364 DRM_DEBUG("%s eotf %d end\n", __func__, hdr_metadata->hdmi_metadata_type1.eotf);
2365 }
2366
hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock)2367 static unsigned int hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock)
2368 {
2369 unsigned int tmdsclock = mpixelclock;
2370 unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
2371
2372 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
2373 switch (depth) {
2374 case 0x10:
2375 tmdsclock = mpixelclock * 0x2;
2376 break;
2377 case 0xc:
2378 tmdsclock = mpixelclock * 0x3 / 0x2;
2379 break;
2380 case 0xa:
2381 tmdsclock = mpixelclock * 0x5 / 0x4;
2382 break;
2383 default:
2384 break;
2385 }
2386 }
2387
2388 return tmdsclock;
2389 }
2390
hdmi_av_composer(struct dw_hdmi *hdmi, const struct drm_display_info *display, const struct drm_display_mode *mode)2391 static void hdmi_av_composer(struct dw_hdmi *hdmi, const struct drm_display_info *display,
2392 const struct drm_display_mode *mode)
2393 {
2394 u8 inv_val, bytes;
2395 const struct drm_hdmi_info *hdmi_info = &display->hdmi;
2396 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
2397 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
2398 unsigned int vdisplay, hdisplay;
2399
2400 vmode->previous_pixelclock = vmode->mpixelclock;
2401 vmode->mpixelclock = mode->crtc_clock * 0x3e8;
2402 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) {
2403 vmode->mpixelclock *= 0x2;
2404 }
2405 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
2406
2407 vmode->previous_tmdsclock = vmode->mtmdsclock;
2408 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
2409 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
2410 vmode->mtmdsclock /= 0x2;
2411 }
2412 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
2413
2414 /* Set up HDMI_FC_INVIDCONF
2415 * Some display equipments require that the interval
2416 * between Video Data and Data island must be at least 58 pixels,
2417 * and fc_invidconf.HDCP_keepout set (1'b1) can meet the requirement.
2418 */
2419 inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE;
2420
2421 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH
2422 : HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
2423
2424 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH
2425 : HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
2426
2427 inv_val |= (vmode->mdataenablepolarity ? HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH
2428 : HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
2429
2430 if (hdmi->vic == 0x27) {
2431 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
2432 } else {
2433 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH
2434 : HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
2435 }
2436
2437 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? HDMI_FC_INVIDCONF_IN_I_P_INTERLACED
2438 : HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
2439
2440 inv_val |= hdmi->sink_is_hdmi ? HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
2441
2442 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
2443
2444 hdisplay = mode->hdisplay;
2445 hblank = mode->htotal - mode->hdisplay;
2446 h_de_hs = mode->hsync_start - mode->hdisplay;
2447 hsync_len = mode->hsync_end - mode->hsync_start;
2448
2449 /*
2450 * When we're setting a YCbCr420 mode, we need
2451 * to adjust the horizontal timing to suit.
2452 */
2453 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
2454 hdisplay /= 0x2;
2455 hblank /= 0x2;
2456 h_de_hs /= 0x2;
2457 hsync_len /= 0x2;
2458 }
2459
2460 vdisplay = mode->vdisplay;
2461 vblank = mode->vtotal - mode->vdisplay;
2462 v_de_vs = mode->vsync_start - mode->vdisplay;
2463 vsync_len = mode->vsync_end - mode->vsync_start;
2464
2465 /*
2466 * When we're setting an interlaced mode, we need
2467 * to adjust the vertical timing to suit.
2468 */
2469 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2470 vdisplay /= 0x2;
2471 vblank /= 0x2;
2472 v_de_vs /= 0x2;
2473 vsync_len /= 0x2;
2474 }
2475
2476 /* Scrambling Control */
2477 if (dw_hdmi_support_scdc(hdmi, display)) {
2478 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2479 (hdmi_info->scdc.scrambling.low_rates && hdmi->scramble_low_rates)) {
2480 /*
2481 * HDMI2.0 Specifies the following procedure:
2482 * After the Source Device has determined that
2483 * SCDC_Present is set (=1), the Source Device should
2484 * write the accurate Version of the Source Device
2485 * to the Source Version field in the SCDCS.
2486 * Source Devices compliant shall set the
2487 * Source Version = 1.
2488 */
2489 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes);
2490 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
2491
2492 /* Enabled Scrambling in the Sink */
2493 drm_scdc_set_scrambling(hdmi->ddc, 1);
2494
2495 /*
2496 * To activate the scrambler feature, you must ensure
2497 * that the quasi-static configuration bit
2498 * fc_invidconf.HDCP_keepout is set at configuration
2499 * time, before the required mc_swrstzreq.tmdsswrst_req
2500 * reset request is issued.
2501 */
2502 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2503 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
2504 } else {
2505 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
2506 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2507 drm_scdc_set_scrambling(hdmi->ddc, 0);
2508 }
2509 } else {
2510 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
2511 }
2512
2513 /* Set up horizontal active pixel width */
2514 hdmi_writeb(hdmi, hdisplay >> 0x8, HDMI_FC_INHACTV1);
2515 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
2516
2517 /* Set up vertical active lines */
2518 hdmi_writeb(hdmi, vdisplay >> 0x8, HDMI_FC_INVACTV1);
2519 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2520
2521 /* Set up horizontal blanking pixel region width */
2522 hdmi_writeb(hdmi, hblank >> 0x8, HDMI_FC_INHBLANK1);
2523 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2524
2525 /* Set up vertical blanking pixel region width */
2526 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2527
2528 /* Set up HSYNC active edge delay width (in pixel clks) */
2529 hdmi_writeb(hdmi, h_de_hs >> 0x8, HDMI_FC_HSYNCINDELAY1);
2530 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2531
2532 /* Set up VSYNC active edge delay (in lines) */
2533 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2534
2535 /* Set up HSYNC active pulse width (in pixel clks) */
2536 hdmi_writeb(hdmi, hsync_len >> 0x8, HDMI_FC_HSYNCINWIDTH1);
2537 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2538
2539 /* Set up VSYNC active edge delay (in lines) */
2540 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2541 }
2542
2543 /* HDMI Initialization Step B.4 */
dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)2544 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2545 {
2546 /* control period minimum duration */
2547 hdmi_writeb(hdmi, 0xc, HDMI_FC_CTRLDUR);
2548 hdmi_writeb(hdmi, 0x20, HDMI_FC_EXCTRLDUR);
2549 hdmi_writeb(hdmi, 0x1, HDMI_FC_EXCTRLSPAC);
2550
2551 /* Set to fill TMDS data channels */
2552 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2553 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2554 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2555
2556 /* Enable pixel clock and tmds data path */
2557 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | HDMI_MC_CLKDIS_CSCCLK_DISABLE | HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2558 HDMI_MC_CLKDIS_PREPCLK_DISABLE | HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2559 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2560 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2561
2562 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2563 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2564
2565 /* Enable pixel repetition path */
2566 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
2567 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
2568 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2569 }
2570
2571 /* Enable csc path */
2572 if (is_csc_needed(hdmi)) {
2573 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2574 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2575
2576 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, HDMI_MC_FLOWCTRL);
2577 } else {
2578 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2579 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2580
2581 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, HDMI_MC_FLOWCTRL);
2582 }
2583 }
2584
2585 /* Workaround to clear the overflow condition */
dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)2586 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2587 {
2588 unsigned int count;
2589 unsigned int i;
2590 u8 val;
2591
2592 /*
2593 * Under some circumstances the Frame Composer arithmetic unit can miss
2594 * an FC register write due to being busy processing the previous one.
2595 * The issue can be worked around by issuing a TMDS software reset and
2596 * then write one of the FC registers several times.
2597 *
2598 * The number of iterations matters and depends on the HDMI TX revision
2599 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
2600 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
2601 * as needing the workaround, with 4 iterations for v1.30a and 1
2602 * iteration for others.
2603 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2604 * the workaround with a single iteration.
2605 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
2606 * been identified as needing the workaround with a single iteration.
2607 */
2608
2609 switch (hdmi->version) {
2610 case 0x130a:
2611 count = 0x4;
2612 break;
2613 case 0x131a:
2614 case 0x132a:
2615 case 0x200a:
2616 case 0x201a:
2617 case 0x211a:
2618 case 0x212a:
2619 count = 0x1;
2620 break;
2621 default:
2622 return;
2623 }
2624
2625 /* TMDS software reset */
2626 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2627
2628 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2629 for (i = 0; i < count; i++) {
2630 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2631 }
2632 }
2633
hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)2634 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2635 {
2636 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, HDMI_IH_MUTE_FC_STAT2);
2637 }
2638
dw_hdmi_setup(struct dw_hdmi *hdmi, const struct drm_connector *connector, const struct drm_display_mode *mode)2639 static int dw_hdmi_setup(struct dw_hdmi *hdmi, const struct drm_connector *connector,
2640 const struct drm_display_mode *mode)
2641 {
2642 int ret;
2643 void *data = hdmi->plat_data->phy_data;
2644
2645 hdmi_disable_overflow_interrupts(hdmi);
2646
2647 hdmi->vic = drm_match_cea_mode(mode);
2648
2649 if (!hdmi->vic) {
2650 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2651 } else {
2652 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2653 }
2654
2655 if (hdmi->plat_data->get_enc_out_encoding) {
2656 hdmi->hdmi_data.enc_out_encoding = hdmi->plat_data->get_enc_out_encoding(data);
2657 } else if ((hdmi->vic == 0x6) || (hdmi->vic == 0x7) || (hdmi->vic == 0x15) || (hdmi->vic == 0x16) ||
2658 (hdmi->vic == 0x2) || (hdmi->vic == 0x3) || (hdmi->vic == 0x11) || (hdmi->vic == 0x12)) {
2659 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2660 } else {
2661 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2662 }
2663
2664 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2665 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
2666 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
2667 } else {
2668 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2669 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2670 }
2671 /* TOFIX: Get input format from plat data or fallback to RGB888 */
2672 if (hdmi->plat_data->get_input_bus_format) {
2673 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->get_input_bus_format(data);
2674 } else if (hdmi->plat_data->input_bus_format) {
2675 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->input_bus_format;
2676 } else {
2677 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2678 }
2679
2680 /* TOFIX: Default to RGB888 output format */
2681 if (hdmi->plat_data->get_output_bus_format) {
2682 hdmi->hdmi_data.enc_out_bus_format = hdmi->plat_data->get_output_bus_format(data);
2683 } else {
2684 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2685 }
2686
2687 /* TOFIX: Get input encoding from plat data or fallback to none */
2688 if (hdmi->plat_data->get_enc_in_encoding) {
2689 hdmi->hdmi_data.enc_in_encoding = hdmi->plat_data->get_enc_in_encoding(data);
2690 } else if (hdmi->plat_data->input_bus_encoding) {
2691 hdmi->hdmi_data.enc_in_encoding = hdmi->plat_data->input_bus_encoding;
2692 } else {
2693 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2694 }
2695
2696 if (hdmi->plat_data->get_quant_range) {
2697 hdmi->hdmi_data.quant_range = hdmi->plat_data->get_quant_range(data);
2698 }
2699
2700 hdmi->hdmi_data.rgb_limited_range =
2701 hdmi->sink_is_hdmi && drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED;
2702
2703 if (!hdmi->sink_is_hdmi) {
2704 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_FULL;
2705 }
2706
2707 /*
2708 * According to the dw-hdmi specification 6.4.2
2709 * vp_pr_cd[3:0]:
2710 * 0000b: No pixel repetition (pixel sent only once)
2711 * 0001b: Pixel sent two times (pixel repeated once)
2712 */
2713 hdmi->hdmi_data.pix_repet_factor = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
2714 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2715
2716 /* HDMI Initialization Step B.1 */
2717 hdmi_av_composer(hdmi, &connector->display_info, mode);
2718
2719 /* HDMI Initializateion Step B.2 */
2720 if (!hdmi->phy.enabled ||
2721 hdmi->hdmi_data.video_mode.previous_pixelclock != hdmi->hdmi_data.video_mode.mpixelclock ||
2722 hdmi->hdmi_data.video_mode.previous_tmdsclock != hdmi->hdmi_data.video_mode.mtmdsclock) {
2723 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &connector->display_info, &hdmi->previous_mode);
2724 if (ret) {
2725 return ret;
2726 }
2727 hdmi->phy.enabled = true;
2728 }
2729
2730 /* HDMI Initialization Step B.3 */
2731 dw_hdmi_enable_video_path(hdmi);
2732
2733 if (hdmi->sink_has_audio) {
2734 dev_dbg(hdmi->dev, "sink has audio support\n");
2735
2736 /* HDMI Initialization Step E - Configure audio */
2737 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2738 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2739 }
2740
2741 /* not for DVI mode */
2742 if (hdmi->sink_is_hdmi) {
2743 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2744
2745 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2746 hdmi_config_AVI(hdmi, connector, mode);
2747 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2748 hdmi_config_drm_infoframe(hdmi, connector);
2749 } else {
2750 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2751 }
2752
2753 hdmi_video_packetize(hdmi);
2754 hdmi_video_csc(hdmi);
2755 hdmi_video_sample(hdmi);
2756 hdmi_tx_hdcp_config(hdmi, mode);
2757
2758 dw_hdmi_clear_overflow(hdmi);
2759
2760 return 0;
2761 }
2762
initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)2763 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2764 {
2765 u8 ih_mute;
2766
2767 /*
2768 * Boot up defaults are:
2769 * HDMI_IH_MUTE = 0x03 (disabled)
2770 * HDMI_IH_MUTE_* = 0x00 (enabled)
2771 *
2772 * Disable top level interrupt bits in HDMI block
2773 */
2774 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2775
2776 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2777
2778 /* by default mask all interrupts */
2779 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2780 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2781 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2782 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2783 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2784 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2785 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2786 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2787 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2788 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2789 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2790 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2791 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2792 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2793
2794 /* Disable interrupts in the IH_MUTE_* registers */
2795 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2796 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2797 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2798 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2799 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2800 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2801 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2802 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2803 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2804 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2805
2806 /* Enable top level interrupt bits in HDMI block */
2807 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2808 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2809 }
2810
dw_hdmi_poweron(struct dw_hdmi *hdmi)2811 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2812 {
2813 hdmi->bridge_is_on = true;
2814
2815 /*
2816 * The curr_conn field is guaranteed to be valid here, as this function
2817 * is only be called when !hdmi->disabled.
2818 */
2819 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2820 }
2821
dw_hdmi_poweroff(struct dw_hdmi *hdmi)2822 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2823 {
2824 if (hdmi->phy.enabled) {
2825 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2826 hdmi->phy.enabled = false;
2827 }
2828
2829 if (hdmi->hdcp && hdmi->hdcp->hdcp_stop) {
2830 hdmi->hdcp->hdcp_stop(hdmi->hdcp);
2831 }
2832 hdmi->bridge_is_on = false;
2833 }
2834
dw_hdmi_update_power(struct dw_hdmi *hdmi)2835 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2836 {
2837 int force = hdmi->force;
2838
2839 if (hdmi->disabled) {
2840 force = DRM_FORCE_OFF;
2841 } else if (force == DRM_FORCE_UNSPECIFIED) {
2842 if (hdmi->rxsense) {
2843 force = DRM_FORCE_ON;
2844 } else {
2845 force = DRM_FORCE_OFF;
2846 }
2847 }
2848
2849 if (force == DRM_FORCE_OFF) {
2850 if (hdmi->initialized) {
2851 hdmi->initialized = false;
2852 hdmi->disabled = true;
2853 }
2854 if (hdmi->bridge_is_on) {
2855 dw_hdmi_poweroff(hdmi);
2856 }
2857 } else {
2858 if (!hdmi->bridge_is_on) {
2859 dw_hdmi_poweron(hdmi);
2860 }
2861 }
2862 }
2863
2864 /*
2865 * Adjust the detection of RXSENSE according to whether we have a forced
2866 * connection mode enabled, or whether we have been disabled. There is
2867 * no point processing RXSENSE interrupts if we have a forced connection
2868 * state, or DRM has us disabled.
2869 *
2870 * We also disable rxsense interrupts when we think we're disconnected
2871 * to avoid floating TDMS signals giving false rxsense interrupts.
2872 *
2873 * Note: we still need to listen for HPD interrupts even when DRM has us
2874 * disabled so that we can detect a connect event.
2875 */
dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)2876 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2877 {
2878 if (hdmi->phy.ops->update_hpd) {
2879 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, hdmi->force, hdmi->disabled, hdmi->rxsense);
2880 }
2881 }
2882
dw_hdmi_detect(struct dw_hdmi *hdmi)2883 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2884 {
2885 enum drm_connector_status result;
2886
2887 if (!hdmi->force_logo) {
2888 mutex_lock(&hdmi->mutex);
2889 hdmi->force = DRM_FORCE_UNSPECIFIED;
2890 dw_hdmi_update_power(hdmi);
2891 dw_hdmi_update_phy_mask(hdmi);
2892 mutex_unlock(&hdmi->mutex);
2893 }
2894
2895 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2896 mutex_lock(&hdmi->mutex);
2897 if (result != hdmi->last_connector_result) {
2898 dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2899 handle_plugged_change(hdmi, result == connector_status_connected);
2900 hdmi->last_connector_result = result;
2901 }
2902 mutex_unlock(&hdmi->mutex);
2903
2904 if (result == connector_status_connected) {
2905 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
2906 } else {
2907 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
2908 }
2909
2910 return result;
2911 }
2912
dw_hdmi_get_edid(struct dw_hdmi *hdmi, struct drm_connector *connector)2913 static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi, struct drm_connector *connector)
2914 {
2915 struct edid *edid;
2916
2917 if (!hdmi->ddc) {
2918 return NULL;
2919 }
2920
2921 edid = drm_get_edid(connector, hdmi->ddc);
2922 if (!edid) {
2923 dev_dbg(hdmi->dev, "failed to get edid\n");
2924 return NULL;
2925 }
2926
2927 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", edid->width_cm, edid->height_cm);
2928
2929 hdmi->support_hdmi = drm_detect_hdmi_monitor(edid);
2930 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2931
2932 return edid;
2933 }
2934
2935 /* -----------------------------------------------------------------------------
2936 * DRM Connector Operations
2937 */
2938
dw_hdmi_connector_detect(struct drm_connector *connector, bool force)2939 static enum drm_connector_status dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2940 {
2941 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
2942 return dw_hdmi_detect(hdmi);
2943 }
2944
dw_hdmi_update_hdr_property(struct drm_connector *connector)2945 static int dw_hdmi_update_hdr_property(struct drm_connector *connector)
2946 {
2947 struct drm_device *dev = connector->dev;
2948 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
2949 void *data = hdmi->plat_data->phy_data;
2950 const struct hdr_static_metadata *metadata = &connector->hdr_sink_metadata.hdmi_type1;
2951 size_t size = sizeof(*metadata);
2952 struct drm_property *property;
2953 struct drm_property_blob *blob;
2954 int ret;
2955
2956 if (hdmi->plat_data->get_hdr_property) {
2957 property = hdmi->plat_data->get_hdr_property(data);
2958 } else {
2959 return -EINVAL;
2960 }
2961
2962 if (hdmi->plat_data->get_hdr_blob) {
2963 blob = hdmi->plat_data->get_hdr_blob(data);
2964 } else {
2965 return -EINVAL;
2966 }
2967
2968 ret = drm_property_replace_global_blob(dev, &blob, size, metadata, &connector->base, property);
2969 return ret;
2970 }
2971
dw_hdmi_connector_get_modes(struct drm_connector *connector)2972 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2973 {
2974 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
2975 struct hdr_static_metadata *metedata = &connector->hdr_sink_metadata.hdmi_type1;
2976 struct edid *edid;
2977 struct drm_display_mode *mode;
2978 struct drm_display_info *info = &connector->display_info;
2979 int i, ret = 0;
2980
2981 memset(metedata, 0, sizeof(*metedata));
2982 edid = dw_hdmi_get_edid(hdmi, connector);
2983 if (edid) {
2984 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", edid->width_cm, edid->height_cm);
2985 drm_connector_update_edid_property(connector, edid);
2986 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2987 ret = drm_add_edid_modes(connector, edid);
2988 if (hdmi->plat_data->get_color_changed) {
2989 hdmi->plat_data->get_yuv422_format(connector, edid);
2990 }
2991 dw_hdmi_update_hdr_property(connector);
2992 kfree(edid);
2993 } else {
2994 hdmi->support_hdmi = true;
2995 hdmi->sink_has_audio = true;
2996 for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
2997 const struct drm_display_mode *ptr = &dw_hdmi_default_modes[i];
2998
2999 mode = drm_mode_duplicate(connector->dev, ptr);
3000 if (mode) {
3001 if (!i) {
3002 mode->type = DRM_MODE_TYPE_PREFERRED;
3003 mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
3004 }
3005 drm_mode_probed_add(connector, mode);
3006 ret++;
3007 }
3008 }
3009 info->edid_hdmi_dc_modes = 0;
3010 info->hdmi.y420_dc_modes = 0;
3011 info->color_formats = 0;
3012
3013 dev_info(hdmi->dev, "failed to get edid\n");
3014 }
3015 dw_hdmi_check_output_type_changed(hdmi);
3016
3017 return ret;
3018 }
3019
dw_hdmi_connector_best_encoder(struct drm_connector *connector)3020 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector *connector)
3021 {
3022 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
3023
3024 return hdmi->bridge.encoder;
3025 }
3026
dw_hdmi_color_changed(struct drm_connector *connector)3027 static bool dw_hdmi_color_changed(struct drm_connector *connector)
3028 {
3029 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
3030 void *data = hdmi->plat_data->phy_data;
3031 bool ret = false;
3032
3033 if (hdmi->plat_data->get_color_changed) {
3034 ret = hdmi->plat_data->get_color_changed(data);
3035 }
3036
3037 return ret;
3038 }
3039
hdr_metadata_equal(const struct drm_connector_state *old_state, const struct drm_connector_state *new_state)3040 static bool hdr_metadata_equal(const struct drm_connector_state *old_state, const struct drm_connector_state *new_state)
3041 {
3042 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
3043 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
3044
3045 if (!old_blob || !new_blob) {
3046 return old_blob == new_blob;
3047 }
3048
3049 if (old_blob->length != new_blob->length) {
3050 return false;
3051 }
3052
3053 return !memcmp(old_blob->data, new_blob->data, old_blob->length);
3054 }
3055
dw_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state)3056 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state)
3057 {
3058 struct drm_connector_state *old_state = drm_atomic_get_old_connector_state(state, connector);
3059 struct drm_connector_state *new_state = drm_atomic_get_new_connector_state(state, connector);
3060 struct drm_crtc *crtc = new_state->crtc;
3061 struct drm_crtc_state *crtc_state;
3062 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
3063 struct drm_display_mode *mode = NULL;
3064 void *data = hdmi->plat_data->phy_data;
3065 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
3066 unsigned int in_bus_format = hdmi->hdmi_data.enc_in_bus_format;
3067 unsigned int out_bus_format = hdmi->hdmi_data.enc_out_bus_format;
3068 bool color_changed = false;
3069
3070 if (!crtc) {
3071 return 0;
3072 }
3073
3074 /*
3075 * If HDMI is enabled in uboot, it's need to record
3076 * drm_display_mode and set phy status to enabled.
3077 */
3078 if (!vmode->mpixelclock) {
3079 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3080 if (hdmi->plat_data->get_enc_in_encoding) {
3081 hdmi->hdmi_data.enc_in_encoding = hdmi->plat_data->get_enc_in_encoding(data);
3082 }
3083 if (hdmi->plat_data->get_enc_out_encoding) {
3084 hdmi->hdmi_data.enc_out_encoding = hdmi->plat_data->get_enc_out_encoding(data);
3085 }
3086 if (hdmi->plat_data->get_input_bus_format) {
3087 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->get_input_bus_format(data);
3088 }
3089 if (hdmi->plat_data->get_output_bus_format) {
3090 hdmi->hdmi_data.enc_out_bus_format = hdmi->plat_data->get_output_bus_format(data);
3091 }
3092
3093 mode = &crtc_state->mode;
3094 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
3095 vmode->mpixelclock = mode->crtc_clock * 0x3e8;
3096 vmode->previous_pixelclock = mode->clock;
3097 vmode->previous_tmdsclock = mode->clock;
3098 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
3099 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
3100 vmode->mtmdsclock /= 0x2;
3101 }
3102
3103 if (in_bus_format != hdmi->hdmi_data.enc_in_bus_format ||
3104 out_bus_format != hdmi->hdmi_data.enc_out_bus_format) {
3105 color_changed = true;
3106 }
3107 }
3108
3109 if (!hdr_metadata_equal(old_state, new_state) || dw_hdmi_color_changed(connector) || color_changed) {
3110 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3111 if (IS_ERR(crtc_state)) {
3112 return PTR_ERR(crtc_state);
3113 }
3114
3115 crtc_state->mode_changed = true;
3116 }
3117
3118 return 0;
3119 }
3120
dw_hdmi_atomic_connector_set_property(struct drm_connector *connector, struct drm_connector_state *state, struct drm_property *property, uint64_t val)3121 static int dw_hdmi_atomic_connector_set_property(struct drm_connector *connector, struct drm_connector_state *state,
3122 struct drm_property *property, uint64_t val)
3123 {
3124 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
3125 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
3126
3127 if (ops && ops->set_property) {
3128 return ops->set_property(connector, state, property, val, hdmi->plat_data->phy_data);
3129 } else {
3130 return -EINVAL;
3131 }
3132 }
3133
dw_hdmi_atomic_connector_get_property(struct drm_connector *connector, const struct drm_connector_state *state, struct drm_property *property, uint64_t *val)3134 static int dw_hdmi_atomic_connector_get_property(struct drm_connector *connector,
3135 const struct drm_connector_state *state, struct drm_property *property,
3136 uint64_t *val)
3137 {
3138 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
3139 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
3140
3141 if (ops && ops->get_property) {
3142 return ops->get_property(connector, state, property, val, hdmi->plat_data->phy_data);
3143 } else {
3144 return -EINVAL;
3145 }
3146 }
3147
dw_hdmi_connector_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val)3148 static int dw_hdmi_connector_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val)
3149 {
3150 return dw_hdmi_atomic_connector_set_property(connector, NULL, property, val);
3151 }
3152
dw_hdmi_set_quant_range(struct dw_hdmi *hdmi)3153 void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi)
3154 {
3155 if (!hdmi->bridge_is_on) {
3156 return;
3157 }
3158
3159 hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
3160 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
3161 hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
3162 }
3163 EXPORT_SYMBOL_GPL(dw_hdmi_set_quant_range);
3164
dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val)3165 void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val)
3166 {
3167 hdmi->force_output = val;
3168
3169 if (!dw_hdmi_check_output_type_changed(hdmi)) {
3170 return;
3171 }
3172
3173 if (!hdmi->bridge_is_on) {
3174 return;
3175 }
3176
3177 hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
3178 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
3179 hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
3180 }
3181 EXPORT_SYMBOL_GPL(dw_hdmi_set_output_type);
3182
dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi)3183 bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi)
3184 {
3185 return hdmi->sink_is_hdmi;
3186 }
3187 EXPORT_SYMBOL_GPL(dw_hdmi_get_output_whether_hdmi);
3188
dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi)3189 int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi)
3190 {
3191 return hdmi->support_hdmi;
3192 }
3193 EXPORT_SYMBOL_GPL(dw_hdmi_get_output_type_cap);
3194
dw_hdmi_connector_force(struct drm_connector *connector)3195 static void dw_hdmi_connector_force(struct drm_connector *connector)
3196 {
3197 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector);
3198
3199 mutex_lock(&hdmi->mutex);
3200
3201 if (hdmi->force != connector->force) {
3202 if (!hdmi->disabled && connector->force == DRM_FORCE_OFF) {
3203 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
3204 } else if (hdmi->disabled && connector->force == DRM_FORCE_ON) {
3205 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
3206 }
3207 }
3208
3209 hdmi->force = connector->force;
3210 dw_hdmi_update_power(hdmi);
3211 dw_hdmi_update_phy_mask(hdmi);
3212 mutex_unlock(&hdmi->mutex);
3213 }
3214
3215 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
3216 .fill_modes = drm_helper_probe_single_connector_modes,
3217 .detect = dw_hdmi_connector_detect,
3218 .destroy = drm_connector_cleanup,
3219 .force = dw_hdmi_connector_force,
3220 .reset = drm_atomic_helper_connector_reset,
3221 .set_property = dw_hdmi_connector_set_property,
3222 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
3223 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3224 .atomic_set_property = dw_hdmi_atomic_connector_set_property,
3225 .atomic_get_property = dw_hdmi_atomic_connector_get_property,
3226 };
3227
3228 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
3229 .get_modes = dw_hdmi_connector_get_modes,
3230 .best_encoder = dw_hdmi_connector_best_encoder,
3231 .atomic_check = dw_hdmi_connector_atomic_check,
3232 };
3233
dw_hdmi_attach_properties(struct dw_hdmi *hdmi)3234 static void dw_hdmi_attach_properties(struct dw_hdmi *hdmi)
3235 {
3236 unsigned int color = MEDIA_BUS_FMT_RGB888_1X24;
3237 int video_mapping, colorspace;
3238 enum drm_connector_status connect_status = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
3239 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
3240
3241 if (connect_status == connector_status_connected) {
3242 video_mapping = (hdmi_readb(hdmi, HDMI_TX_INVID0) & HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
3243 colorspace = (hdmi_readb(hdmi, HDMI_FC_AVICONF0) & HDMI_FC_AVICONF0_PIX_FMT_MASK);
3244 switch (video_mapping) {
3245 case 0x01:
3246 color = MEDIA_BUS_FMT_RGB888_1X24;
3247 break;
3248 case 0x03:
3249 color = MEDIA_BUS_FMT_RGB101010_1X30;
3250 break;
3251 case 0x09:
3252 if (colorspace == HDMI_COLORSPACE_YUV420) {
3253 color = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
3254 } else if (colorspace == HDMI_COLORSPACE_YUV422) {
3255 color = MEDIA_BUS_FMT_UYVY8_1X16;
3256 } else {
3257 color = MEDIA_BUS_FMT_YUV8_1X24;
3258 }
3259 break;
3260 case 0x0b:
3261 if (colorspace == HDMI_COLORSPACE_YUV420) {
3262 color = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
3263 } else if (colorspace == HDMI_COLORSPACE_YUV422) {
3264 color = MEDIA_BUS_FMT_UYVY10_1X20;
3265 } else {
3266 color = MEDIA_BUS_FMT_YUV10_1X30;
3267 }
3268 break;
3269 case 0x14:
3270 color = MEDIA_BUS_FMT_UYVY10_1X20;
3271 break;
3272 case 0x16:
3273 color = MEDIA_BUS_FMT_UYVY8_1X16;
3274 break;
3275 default:
3276 color = MEDIA_BUS_FMT_RGB888_1X24;
3277 dev_err(hdmi->dev, "unexpected mapping: 0x%x\n", video_mapping);
3278 }
3279
3280 hdmi->hdmi_data.enc_in_bus_format = color;
3281 hdmi->hdmi_data.enc_out_bus_format = color;
3282 /*
3283 * input format will be set as yuv444 when output
3284 * format is yuv420
3285 */
3286 if (color == MEDIA_BUS_FMT_UYVY10_1X20) {
3287 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV10_1X30;
3288 } else if (color == MEDIA_BUS_FMT_UYVY8_1X16) {
3289 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
3290 }
3291 }
3292
3293 if (ops && ops->attach_properties) {
3294 return ops->attach_properties(&hdmi->connector, color, hdmi->version, hdmi->plat_data->phy_data);
3295 }
3296 }
3297
dw_hdmi_destroy_properties(struct dw_hdmi *hdmi)3298 static void dw_hdmi_destroy_properties(struct dw_hdmi *hdmi)
3299 {
3300 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
3301
3302 if (ops && ops->destroy_properties) {
3303 return ops->destroy_properties(&hdmi->connector, hdmi->plat_data->phy_data);
3304 }
3305 }
3306
dw_hdmi_connector_create(struct dw_hdmi *hdmi)3307 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
3308 {
3309 struct drm_connector *connector = &hdmi->connector;
3310 struct cec_connector_info conn_info;
3311 struct cec_notifier *notifier;
3312
3313 if (hdmi->version >= 0x200a) {
3314 connector->ycbcr_420_allowed = hdmi->plat_data->ycbcr_420_allowed;
3315 } else {
3316 connector->ycbcr_420_allowed = false;
3317 }
3318
3319 connector->interlace_allowed = 1;
3320 connector->polled = DRM_CONNECTOR_POLL_HPD;
3321
3322 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
3323
3324 drm_connector_init_with_ddc(hdmi->bridge.dev, connector, &dw_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA,
3325 hdmi->ddc);
3326
3327 /*
3328 * drm_connector_attach_max_bpc_property() requires the
3329 * connector to have a state.
3330 */
3331 drm_atomic_helper_connector_reset(connector);
3332
3333 drm_connector_attach_max_bpc_property(connector, 0x8, 0x10);
3334
3335 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) {
3336 drm_object_attach_property(&connector->base, connector->dev->mode_config.hdr_output_metadata_property, 0);
3337 }
3338
3339 drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
3340
3341 dw_hdmi_attach_properties(hdmi);
3342
3343 cec_fill_conn_info_from_drm(&conn_info, connector);
3344
3345 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
3346 if (!notifier) {
3347 return -ENOMEM;
3348 }
3349
3350 mutex_lock(&hdmi->cec_notifier_mutex);
3351 hdmi->cec_notifier = notifier;
3352 mutex_unlock(&hdmi->cec_notifier_mutex);
3353
3354 return 0;
3355 }
3356
3357 /* -----------------------------------------------------------------------------
3358 * DRM Bridge Operations
3359 */
3360
3361 /*
3362 * Possible output formats :
3363 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
3364 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
3365 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
3366 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
3367 * - MEDIA_BUS_FMT_YUV16_1X48,
3368 * - MEDIA_BUS_FMT_RGB161616_1X48,
3369 * - MEDIA_BUS_FMT_UYVY12_1X24,
3370 * - MEDIA_BUS_FMT_YUV12_1X36,
3371 * - MEDIA_BUS_FMT_RGB121212_1X36,
3372 * - MEDIA_BUS_FMT_UYVY10_1X20,
3373 * - MEDIA_BUS_FMT_YUV10_1X30,
3374 * - MEDIA_BUS_FMT_RGB101010_1X30,
3375 * - MEDIA_BUS_FMT_UYVY8_1X16,
3376 * - MEDIA_BUS_FMT_YUV8_1X24,
3377 * - MEDIA_BUS_FMT_RGB888_1X24,
3378 */
3379
3380 /* Can return a maximum of 11 possible output formats for a mode/connector */
3381 #define MAX_OUTPUT_SEL_FORMATS 11
3382
dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state, unsigned int *num_output_fmts)3383 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state,
3384 struct drm_crtc_state *crtc_state,
3385 struct drm_connector_state *conn_state,
3386 unsigned int *num_output_fmts)
3387 {
3388 struct drm_connector *conn = conn_state->connector;
3389 struct drm_display_info *info = &conn->display_info;
3390 struct drm_display_mode *mode = &crtc_state->mode;
3391 u8 max_bpc = conn_state->max_requested_bpc;
3392 bool is_hdmi2_sink = info->hdmi.scdc.supported || (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
3393 u32 *output_fmts;
3394 unsigned int i = 0;
3395
3396 *num_output_fmts = 0;
3397
3398 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), GFP_KERNEL);
3399 if (!output_fmts) {
3400 return NULL;
3401 }
3402
3403 /* If dw-hdmi is the only bridge, avoid negociating with ourselves */
3404 if (list_is_singular(&bridge->encoder->bridge_chain) ||
3405 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
3406 *num_output_fmts = 1;
3407 output_fmts[0] = MEDIA_BUS_FMT_FIXED;
3408
3409 return output_fmts;
3410 }
3411
3412 /*
3413 * If the current mode enforces 4:2:0, force the output but format
3414 * to 4:2:0 and do not add the YUV422/444/RGB formats
3415 */
3416 if (conn->ycbcr_420_allowed &&
3417 (drm_mode_is_420_only(info, mode) || (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
3418 /* Order bus formats from 16bit to 8bit if supported */
3419 if (max_bpc >= 0x10 && info->bpc == 0x10 && (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) {
3420 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
3421 }
3422
3423 if (max_bpc >= 0xc && info->bpc >= 0xc && (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) {
3424 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
3425 }
3426
3427 if (max_bpc >= 0xa && info->bpc >= 0xa && (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) {
3428 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
3429 }
3430
3431 /* Default 8bit fallback */
3432 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
3433
3434 *num_output_fmts = i;
3435
3436 return output_fmts;
3437 }
3438
3439 /*
3440 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
3441 * if supported. In any case the default RGB888 format is added
3442 */
3443
3444 if (max_bpc >= 0x10 && info->bpc == 0x10) {
3445 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
3446 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
3447 }
3448
3449 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
3450 }
3451
3452 if (max_bpc >= 0xc && info->bpc >= 0xc) {
3453 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
3454 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3455 }
3456
3457 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
3458 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3459 }
3460
3461 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3462 }
3463
3464 if (max_bpc >= 0xa && info->bpc >= 0xa) {
3465 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
3466 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3467 }
3468
3469 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
3470 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3471 }
3472
3473 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3474 }
3475
3476 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
3477 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3478 }
3479
3480 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
3481 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3482 }
3483
3484 /* Default 8bit RGB fallback */
3485 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3486
3487 *num_output_fmts = i;
3488
3489 return output_fmts;
3490 }
3491
3492 /*
3493 * Possible input formats :
3494 * - MEDIA_BUS_FMT_RGB888_1X24
3495 * - MEDIA_BUS_FMT_YUV8_1X24
3496 * - MEDIA_BUS_FMT_UYVY8_1X16
3497 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
3498 * - MEDIA_BUS_FMT_RGB101010_1X30
3499 * - MEDIA_BUS_FMT_YUV10_1X30
3500 * - MEDIA_BUS_FMT_UYVY10_1X20
3501 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
3502 * - MEDIA_BUS_FMT_RGB121212_1X36
3503 * - MEDIA_BUS_FMT_YUV12_1X36
3504 * - MEDIA_BUS_FMT_UYVY12_1X24
3505 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
3506 * - MEDIA_BUS_FMT_RGB161616_1X48
3507 * - MEDIA_BUS_FMT_YUV16_1X48
3508 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
3509 */
3510
3511 /* Can return a maximum of 3 possible input formats for an output format */
3512 #define MAX_INPUT_SEL_FORMATS 3
3513
dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state, u32 output_fmt, unsigned int *num_input_fmts)3514 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state,
3515 struct drm_crtc_state *crtc_state,
3516 struct drm_connector_state *conn_state, u32 output_fmt,
3517 unsigned int *num_input_fmts)
3518 {
3519 u32 *input_fmts;
3520 unsigned int i = 0;
3521
3522 *num_input_fmts = 0;
3523
3524 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), GFP_KERNEL);
3525 if (!input_fmts) {
3526 return NULL;
3527 }
3528
3529 switch (output_fmt) {
3530 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
3531 case MEDIA_BUS_FMT_FIXED:
3532 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3533 break;
3534 /* 8bit */
3535 case MEDIA_BUS_FMT_RGB888_1X24:
3536 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3537 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3538 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3539 break;
3540 case MEDIA_BUS_FMT_YUV8_1X24:
3541 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3542 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3543 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3544 break;
3545 case MEDIA_BUS_FMT_UYVY8_1X16:
3546 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3547 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3548 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3549 break;
3550
3551 /* 10bit */
3552 case MEDIA_BUS_FMT_RGB101010_1X30:
3553 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3554 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3555 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3556 break;
3557 case MEDIA_BUS_FMT_YUV10_1X30:
3558 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3559 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3560 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3561 break;
3562 case MEDIA_BUS_FMT_UYVY10_1X20:
3563 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3564 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3565 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3566 break;
3567
3568 /* 12bit */
3569 case MEDIA_BUS_FMT_RGB121212_1X36:
3570 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3571 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3572 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3573 break;
3574 case MEDIA_BUS_FMT_YUV12_1X36:
3575 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3576 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3577 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3578 break;
3579 case MEDIA_BUS_FMT_UYVY12_1X24:
3580 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3581 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3582 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3583 break;
3584
3585 /* 16bit */
3586 case MEDIA_BUS_FMT_RGB161616_1X48:
3587 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
3588 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
3589 break;
3590 case MEDIA_BUS_FMT_YUV16_1X48:
3591 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
3592 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
3593 break;
3594 /* YUV 4:2:0 */
3595 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
3596 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
3597 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
3598 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
3599 input_fmts[i++] = output_fmt;
3600 break;
3601 }
3602
3603 *num_input_fmts = i;
3604
3605 if (*num_input_fmts == 0) {
3606 kfree(input_fmts);
3607 input_fmts = NULL;
3608 }
3609
3610 return input_fmts;
3611 }
3612
dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state)3613 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state,
3614 struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state)
3615 {
3616 struct dw_hdmi *hdmi = bridge->driver_private;
3617 void *data = hdmi->plat_data->phy_data;
3618
3619 if (bridge_state->output_bus_cfg.format == MEDIA_BUS_FMT_FIXED) {
3620 if (hdmi->plat_data->get_output_bus_format) {
3621 hdmi->hdmi_data.enc_out_bus_format = hdmi->plat_data->get_output_bus_format(data);
3622 } else {
3623 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
3624 }
3625
3626 if (hdmi->plat_data->get_input_bus_format) {
3627 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->get_input_bus_format(data);
3628 } else if (hdmi->plat_data->input_bus_format) {
3629 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->input_bus_format;
3630 } else {
3631 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
3632 }
3633 } else {
3634 hdmi->hdmi_data.enc_out_bus_format = bridge_state->output_bus_cfg.format;
3635
3636 hdmi->hdmi_data.enc_in_bus_format = bridge_state->input_bus_cfg.format;
3637
3638 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", bridge_state->input_bus_cfg.format,
3639 bridge_state->output_bus_cfg.format);
3640 }
3641
3642 return 0;
3643 }
3644
dw_hdmi_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)3645 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
3646 {
3647 struct dw_hdmi *hdmi = bridge->driver_private;
3648 int ret;
3649
3650 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
3651 return 0;
3652 }
3653
3654 if (hdmi->next_bridge) {
3655 hdmi->next_bridge->encoder = bridge->encoder;
3656 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge, flags);
3657 if (ret) {
3658 DRM_ERROR("Failed to attach bridge with dw-hdmi\n");
3659 return ret;
3660 }
3661
3662 return 0;
3663 }
3664
3665 return dw_hdmi_connector_create(hdmi);
3666 }
3667
dw_hdmi_bridge_detach(struct drm_bridge *bridge)3668 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
3669 {
3670 struct dw_hdmi *hdmi = bridge->driver_private;
3671
3672 mutex_lock(&hdmi->cec_notifier_mutex);
3673 cec_notifier_conn_unregister(hdmi->cec_notifier);
3674 hdmi->cec_notifier = NULL;
3675 mutex_unlock(&hdmi->cec_notifier_mutex);
3676 }
3677
dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode)3678 static enum drm_mode_status dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info,
3679 const struct drm_display_mode *mode)
3680 {
3681 struct dw_hdmi *hdmi = bridge->driver_private;
3682 struct drm_connector *connector = &hdmi->connector;
3683 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
3684 enum drm_mode_status mode_status = MODE_OK;
3685
3686 if (hdmi->next_bridge) {
3687 return MODE_OK;
3688 }
3689
3690 if (pdata->mode_valid) {
3691 mode_status = pdata->mode_valid(connector, pdata->priv_data, info, mode);
3692 }
3693 return mode_status;
3694 }
3695
dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *orig_mode, const struct drm_display_mode *mode)3696 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *orig_mode,
3697 const struct drm_display_mode *mode)
3698 {
3699 struct dw_hdmi *hdmi = bridge->driver_private;
3700
3701 mutex_lock(&hdmi->mutex);
3702
3703 /* Store the display mode for plugin/DKMS poweron events */
3704 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
3705
3706 mutex_unlock(&hdmi->mutex);
3707 }
3708
dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_state)3709 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_state)
3710 {
3711 struct dw_hdmi *hdmi = bridge->driver_private;
3712
3713 mutex_lock(&hdmi->mutex);
3714 hdmi->disabled = true;
3715 hdmi->curr_conn = NULL;
3716 dw_hdmi_update_power(hdmi);
3717 dw_hdmi_update_phy_mask(hdmi);
3718 mutex_unlock(&hdmi->mutex);
3719 }
3720
dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_state)3721 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_state)
3722 {
3723 struct dw_hdmi *hdmi = bridge->driver_private;
3724 struct drm_atomic_state *state = old_state->base.state;
3725 struct drm_connector *connector;
3726
3727 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
3728
3729 mutex_lock(&hdmi->mutex);
3730 hdmi->disabled = false;
3731 hdmi->curr_conn = connector;
3732 dw_hdmi_update_power(hdmi);
3733 dw_hdmi_update_phy_mask(hdmi);
3734 mutex_unlock(&hdmi->mutex);
3735 }
3736
dw_hdmi_bridge_detect(struct drm_bridge *bridge)3737 static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
3738 {
3739 struct dw_hdmi *hdmi = bridge->driver_private;
3740
3741 return dw_hdmi_detect(hdmi);
3742 }
3743
dw_hdmi_bridge_get_edid(struct drm_bridge *bridge, struct drm_connector *connector)3744 static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge, struct drm_connector *connector)
3745 {
3746 struct dw_hdmi *hdmi = bridge->driver_private;
3747
3748 return dw_hdmi_get_edid(hdmi, connector);
3749 }
3750
3751 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
3752 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3753 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3754 .atomic_reset = drm_atomic_helper_bridge_reset,
3755 .attach = dw_hdmi_bridge_attach,
3756 .detach = dw_hdmi_bridge_detach,
3757 .atomic_check = dw_hdmi_bridge_atomic_check,
3758 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
3759 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
3760 .atomic_enable = dw_hdmi_bridge_atomic_enable,
3761 .atomic_disable = dw_hdmi_bridge_atomic_disable,
3762 .mode_set = dw_hdmi_bridge_mode_set,
3763 .mode_valid = dw_hdmi_bridge_mode_valid,
3764 .detect = dw_hdmi_bridge_detect,
3765 .get_edid = dw_hdmi_bridge_get_edid,
3766 };
3767
dw_hdmi_set_cec_adap(struct dw_hdmi *hdmi, struct cec_adapter *adap)3768 void dw_hdmi_set_cec_adap(struct dw_hdmi *hdmi, struct cec_adapter *adap)
3769 {
3770 hdmi->cec_adap = adap;
3771 }
3772 EXPORT_SYMBOL_GPL(dw_hdmi_set_cec_adap);
3773
3774 /* -----------------------------------------------------------------------------
3775 * IRQ Handling
3776 */
3777
dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)3778 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
3779 {
3780 struct dw_hdmi_i2c *i2c = hdmi->i2c;
3781 unsigned int stat;
3782
3783 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
3784 if (!stat) {
3785 return IRQ_NONE;
3786 }
3787
3788 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
3789
3790 i2c->stat = stat;
3791
3792 complete(&i2c->cmp);
3793
3794 return IRQ_HANDLED;
3795 }
3796
dw_hdmi_hardirq(int irq, void *dev_id)3797 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
3798 {
3799 struct dw_hdmi *hdmi = dev_id;
3800 u8 intr_stat, hdcp_stat;
3801 irqreturn_t ret = IRQ_NONE;
3802
3803 if (hdmi->i2c) {
3804 ret = dw_hdmi_i2c_irq(hdmi);
3805 }
3806
3807 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3808 if (intr_stat) {
3809 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3810 return IRQ_WAKE_THREAD;
3811 }
3812
3813 hdcp_stat = hdmi_readb(hdmi, HDMI_A_APIINTSTAT);
3814 if (hdcp_stat) {
3815 dev_dbg(hdmi->dev, "HDCP irq %#x\n", hdcp_stat);
3816 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
3817 return IRQ_WAKE_THREAD;
3818 }
3819
3820 return ret;
3821 }
3822
dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)3823 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
3824 {
3825 mutex_lock(&hdmi->mutex);
3826
3827 if (!hdmi->force && !hdmi->force_logo) {
3828 /*
3829 * If the RX sense status indicates we're disconnected,
3830 * clear the software rxsense status.
3831 */
3832 if (!rx_sense) {
3833 hdmi->rxsense = false;
3834 }
3835
3836 /*
3837 * Only set the software rxsense status when both
3838 * rxsense and hpd indicates we're connected.
3839 * This avoids what seems to be bad behaviour in
3840 * at least iMX6S versions of the phy.
3841 */
3842 if (hpd) {
3843 hdmi->rxsense = true;
3844 }
3845
3846 dw_hdmi_update_power(hdmi);
3847 dw_hdmi_update_phy_mask(hdmi);
3848 }
3849 mutex_unlock(&hdmi->mutex);
3850 }
3851 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
3852
dw_hdmi_irq(int irq, void *dev_id)3853 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
3854 {
3855 struct dw_hdmi *hdmi = dev_id;
3856 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat, hdcp_stat;
3857
3858 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3859 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
3860 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
3861
3862 phy_pol_mask = 0;
3863 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
3864 phy_pol_mask |= HDMI_PHY_HPD;
3865 }
3866 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) {
3867 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
3868 }
3869 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) {
3870 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
3871 }
3872 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) {
3873 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
3874 }
3875 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) {
3876 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
3877 }
3878
3879 if (phy_pol_mask) {
3880 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
3881 }
3882
3883 /*
3884 * RX sense tells us whether the TDMS transmitters are detecting
3885 * load - in other words, there's something listening on the
3886 * other end of the link. Use this to decide whether we should
3887 * power on the phy as HPD may be toggled by the sink to merely
3888 * ask the source to re-read the EDID.
3889 */
3890 if (intr_stat & (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
3891 dw_hdmi_setup_rx_sense(hdmi, phy_stat & HDMI_PHY_HPD, phy_stat & HDMI_PHY_RX_SENSE);
3892
3893 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
3894 mutex_lock(&hdmi->cec_notifier_mutex);
3895 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3896 mutex_unlock(&hdmi->cec_notifier_mutex);
3897 }
3898 }
3899
3900 check_hdmi_irq(hdmi, intr_stat, phy_int_pol);
3901
3902 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
3903 if (!hdmi->next_bridge) {
3904 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), HDMI_IH_MUTE_PHY_STAT0);
3905 }
3906
3907 hdcp_stat = hdmi_readb(hdmi, HDMI_A_APIINTSTAT);
3908 if (hdcp_stat) {
3909 if (hdmi->hdcp) {
3910 hdmi->hdcp->hdcp_isr(hdmi->hdcp, hdcp_stat);
3911 }
3912 hdmi_writeb(hdmi, hdcp_stat, HDMI_A_APIINTCLR);
3913 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK);
3914 }
3915 return IRQ_HANDLED;
3916 }
3917
3918 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
3919 {
3920 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
3921 .name = "DWC HDMI TX PHY",
3922 .gen = 1,
3923 },
3924 {
3925 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
3926 .name = "DWC MHL PHY + HEAC PHY",
3927 .gen = 2,
3928 .has_svsret = true,
3929 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3930 },
3931 {
3932 .type = DW_HDMI_PHY_DWC_MHL_PHY,
3933 .name = "DWC MHL PHY",
3934 .gen = 2,
3935 .has_svsret = true,
3936 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3937 },
3938 {
3939 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
3940 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
3941 .gen = 2,
3942 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3943 },
3944 {
3945 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
3946 .name = "DWC HDMI 3D TX PHY",
3947 .gen = 2,
3948 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3949 },
3950 {
3951 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
3952 .name = "DWC HDMI 2.0 TX PHY",
3953 .gen = 2,
3954 .has_svsret = true,
3955 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3956 },
3957 {
3958 .type = DW_HDMI_PHY_VENDOR_PHY,
3959 .name = "Vendor PHY",
3960 }
3961 };
3962
dw_hdmi_detect_phy(struct dw_hdmi *hdmi)3963 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3964 {
3965 unsigned int i;
3966 u8 phy_type;
3967
3968 phy_type = hdmi->plat_data->phy_force_vendor ? DW_HDMI_PHY_VENDOR_PHY : hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3969 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
3970 /* Vendor PHYs require support from the glue layer. */
3971 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3972 dev_err(hdmi->dev, "Vendor HDMI PHY not supported by glue layer\n");
3973 return -ENODEV;
3974 }
3975
3976 hdmi->phy.ops = hdmi->plat_data->phy_ops;
3977 hdmi->phy.data = hdmi->plat_data->phy_data;
3978 hdmi->phy.name = hdmi->plat_data->phy_name;
3979 return 0;
3980 }
3981
3982 /* Synopsys PHYs are handled internally. */
3983 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
3984 if (dw_hdmi_phys[i].type == phy_type) {
3985 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3986 hdmi->phy.name = dw_hdmi_phys[i].name;
3987 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3988
3989 if (!dw_hdmi_phys[i].configure && !hdmi->plat_data->configure_phy) {
3990 dev_err(hdmi->dev, "%s requires platform support\n", hdmi->phy.name);
3991 return -ENODEV;
3992 }
3993
3994 return 0;
3995 }
3996 }
3997
3998 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3999 return -ENODEV;
4000 }
4001
dw_hdmi_cec_enable(struct dw_hdmi *hdmi)4002 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
4003 {
4004 mutex_lock(&hdmi->mutex);
4005 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
4006 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
4007 mutex_unlock(&hdmi->mutex);
4008 }
4009
dw_hdmi_cec_disable(struct dw_hdmi *hdmi)4010 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
4011 {
4012 mutex_lock(&hdmi->mutex);
4013 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
4014 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
4015 mutex_unlock(&hdmi->mutex);
4016 }
4017
4018 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
4019 .write = hdmi_writeb,
4020 .read = hdmi_readb,
4021 .enable = dw_hdmi_cec_enable,
4022 .disable = dw_hdmi_cec_disable,
4023 };
4024
4025 static const struct regmap_config hdmi_regmap_8bit_config = {
4026 .reg_bits = 32,
4027 .val_bits = 8,
4028 .reg_stride = 1,
4029 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
4030 };
4031
4032 static const struct regmap_config hdmi_regmap_32bit_config = {
4033 .reg_bits = 32,
4034 .val_bits = 32,
4035 .reg_stride = 4,
4036 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
4037 };
4038
dw_hdmi_init_hw(struct dw_hdmi *hdmi)4039 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
4040 {
4041 initialize_hdmi_ih_mutes(hdmi);
4042
4043 /*
4044 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
4045 * Even if we are using a separate i2c adapter doing this doesn't
4046 * hurt.
4047 */
4048 if (hdmi->i2c) {
4049 dw_hdmi_i2c_init(hdmi);
4050 }
4051
4052 if (hdmi->phy.ops->setup_hpd) {
4053 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
4054 }
4055 }
4056
dw_hdmi_status_show(struct seq_file *s, void *v)4057 static int dw_hdmi_status_show(struct seq_file *s, void *v)
4058 {
4059 struct dw_hdmi *hdmi = s->private;
4060 u32 val;
4061
4062 seq_puts(s, "PHY: ");
4063 if (!hdmi->phy.enabled) {
4064 seq_puts(s, "disabled\n");
4065 return 0;
4066 }
4067 seq_puts(s, "enabled\t\t\tMode: ");
4068 if (hdmi->sink_is_hdmi) {
4069 seq_puts(s, "HDMI\n");
4070 } else {
4071 seq_puts(s, "DVI\n");
4072 }
4073 if (hdmi->hdmi_data.video_mode.mtmdsclock > 0x1433fd00) {
4074 val = hdmi->hdmi_data.video_mode.mtmdsclock / 0x4;
4075 } else {
4076 val = hdmi->hdmi_data.video_mode.mtmdsclock;
4077 }
4078 seq_printf(s, "Pixel Clk: %uHz\t\tTMDS Clk: %uHz\n", hdmi->hdmi_data.video_mode.mpixelclock, val);
4079 seq_puts(s, "Color Format: ");
4080 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
4081 seq_puts(s, "RGB");
4082 } else if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
4083 seq_puts(s, "YUV444");
4084 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
4085 seq_puts(s, "YUV422");
4086 } else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
4087 seq_puts(s, "YUV420");
4088 } else {
4089 seq_puts(s, "UNKNOWN");
4090 }
4091 val = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
4092 seq_printf(s, "\t\tColor Depth: %d bit\n", val);
4093 seq_puts(s, "Colorimetry: ");
4094 switch (hdmi->hdmi_data.enc_out_encoding) {
4095 case V4L2_YCBCR_ENC_601:
4096 seq_puts(s, "ITU.BT601");
4097 break;
4098 case V4L2_YCBCR_ENC_709:
4099 seq_puts(s, "ITU.BT709");
4100 break;
4101 case V4L2_YCBCR_ENC_BT2020:
4102 seq_puts(s, "ITU.BT2020");
4103 break;
4104 default: /* Carries no data */
4105 seq_puts(s, "ITU.BT601");
4106 break;
4107 }
4108
4109 seq_puts(s, "\t\tEOTF: ");
4110
4111 if (hdmi->version < 0x211a) {
4112 seq_puts(s, "Unsupported\n");
4113 return 0;
4114 }
4115
4116 val = hdmi_readb(hdmi, HDMI_FC_PACKET_TX_EN);
4117 if (!(val & HDMI_FC_PACKET_TX_EN_DRM_MASK)) {
4118 seq_puts(s, "Off\n");
4119 return 0;
4120 }
4121
4122 switch (hdmi_readb(hdmi, HDMI_FC_DRM_PB0)) {
4123 case HDMI_EOTF_TRADITIONAL_GAMMA_SDR:
4124 seq_puts(s, "SDR");
4125 break;
4126 case HDMI_EOTF_TRADITIONAL_GAMMA_HDR:
4127 seq_puts(s, "HDR");
4128 break;
4129 case HDMI_EOTF_SMPTE_ST2084:
4130 seq_puts(s, "ST2084");
4131 break;
4132 case HDMI_EOTF_BT_2100_HLG:
4133 seq_puts(s, "HLG");
4134 break;
4135 default:
4136 seq_puts(s, "Not Defined\n");
4137 return 0;
4138 }
4139
4140 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB3) << 0x8;
4141 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB2);
4142 seq_printf(s, "\nx0: %d", val);
4143 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB5) << 0x8;
4144 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB4);
4145 seq_printf(s, "\t\t\t\ty0: %d\n", val);
4146 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB7) << 0x8;
4147 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB6);
4148 seq_printf(s, "x1: %d", val);
4149 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB9) << 0x8;
4150 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB8);
4151 seq_printf(s, "\t\t\t\ty1: %d\n", val);
4152 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB11) << 0x8;
4153 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB10);
4154 seq_printf(s, "x2: %d", val);
4155 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB13) << 0x8;
4156 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB12);
4157 seq_printf(s, "\t\t\t\ty2: %d\n", val);
4158 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB15) << 0x8;
4159 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB14);
4160 seq_printf(s, "white x: %d", val);
4161 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB17) << 0x8;
4162 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB16);
4163 seq_printf(s, "\t\t\twhite y: %d\n", val);
4164 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB19) << 0x8;
4165 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB18);
4166 seq_printf(s, "max lum: %d", val);
4167 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB21) << 0x8;
4168 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB20);
4169 seq_printf(s, "\t\t\tmin lum: %d\n", val);
4170 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB23) << 0x8;
4171 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB22);
4172 seq_printf(s, "max cll: %d", val);
4173 val = hdmi_readb(hdmi, HDMI_FC_DRM_PB25) << 0x8;
4174 val |= hdmi_readb(hdmi, HDMI_FC_DRM_PB24);
4175 seq_printf(s, "\t\t\tmax fall: %d\n", val);
4176 return 0;
4177 }
4178
dw_hdmi_status_open(struct inode *inode, struct file *file)4179 static int dw_hdmi_status_open(struct inode *inode, struct file *file)
4180 {
4181 return single_open(file, dw_hdmi_status_show, inode->i_private);
4182 }
4183
4184 static const struct file_operations dw_hdmi_status_fops = {
4185 .owner = THIS_MODULE,
4186 .open = dw_hdmi_status_open,
4187 .read = seq_read,
4188 .llseek = seq_lseek,
4189 .release = single_release,
4190 };
4191
4192 #include <linux/fs.h>
4193 #include <linux/debugfs.h>
4194 #include <linux/seq_file.h>
4195
4196 struct dw_hdmi_reg_table {
4197 int reg_base;
4198 int reg_end;
4199 };
4200
4201 static const struct dw_hdmi_reg_table hdmi_reg_table[] = {
4202 {HDMI_DESIGN_ID, HDMI_CONFIG3_ID},
4203 {HDMI_IH_FC_STAT0, HDMI_IH_MUTE},
4204 {HDMI_TX_INVID0, HDMI_TX_BCBDATA1},
4205 {HDMI_VP_STATUS, HDMI_VP_POL},
4206 {HDMI_FC_INVIDCONF, HDMI_FC_DBGTMDS2},
4207 {HDMI_PHY_CONF0, HDMI_PHY_POL0},
4208 {HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR},
4209 {HDMI_AUD_CONF0, 0x3624},
4210 {HDMI_MC_SFRDIV, HDMI_MC_HEACPHY_RST},
4211 {HDMI_CSC_CFG, HDMI_CSC_COEF_C4_LSB},
4212 {HDMI_A_HDCPCFG0, 0x52bb},
4213 {0x7800, 0x7818},
4214 {0x7900, 0x790e},
4215 {HDMI_CEC_CTRL, HDMI_CEC_WKUPCTRL},
4216 {HDMI_I2CM_SLAVE, 0x7e31},
4217 };
4218
dw_hdmi_ctrl_show(struct seq_file *s, void *v)4219 static int dw_hdmi_ctrl_show(struct seq_file *s, void *v)
4220 {
4221 struct dw_hdmi *hdmi = s->private;
4222 u32 i = 0, j = 0, val = 0;
4223
4224 seq_puts(s, "\n>>>hdmi_ctl reg ");
4225 for (i = 0; i < 0x10; i++) {
4226 seq_printf(s, " %2x", i);
4227 }
4228 seq_puts(s, "\n---------------------------------------------------");
4229
4230 for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) {
4231 for (j = hdmi_reg_table[i].reg_base; j <= hdmi_reg_table[i].reg_end; j++) {
4232 val = hdmi_readb(hdmi, j);
4233 if ((j - hdmi_reg_table[i].reg_base) % 0x10 == 0) {
4234 seq_printf(s, "\n>>>hdmi_ctl %04x:", j);
4235 }
4236 seq_printf(s, " %02x", val);
4237 }
4238 }
4239 seq_puts(s, "\n---------------------------------------------------\n");
4240
4241 return 0;
4242 }
4243
dw_hdmi_ctrl_open(struct inode *inode, struct file *file)4244 static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file)
4245 {
4246 return single_open(file, dw_hdmi_ctrl_show, inode->i_private);
4247 }
4248
dw_hdmi_ctrl_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)4249 static ssize_t dw_hdmi_ctrl_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
4250 {
4251 struct dw_hdmi *hdmi = ((struct seq_file *)file->private_data)->private;
4252 u32 reg, val;
4253 char kbuf[0x19];
4254
4255 if (copy_from_user(kbuf, buf, count)) {
4256 return -EFAULT;
4257 }
4258 if (sscanf(kbuf, "%x%x", ®, &val) == -1) {
4259 return -EFAULT;
4260 }
4261 if (reg > HDMI_I2CM_FS_SCL_LCNT_0_ADDR) {
4262 dev_err(hdmi->dev, "it is no a hdmi register\n");
4263 return count;
4264 }
4265 dev_info(hdmi->dev, "/**********hdmi register config******/");
4266 dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
4267 hdmi_writeb(hdmi, val, reg);
4268 return count;
4269 }
4270
4271 static const struct file_operations dw_hdmi_ctrl_fops = {
4272 .owner = THIS_MODULE,
4273 .open = dw_hdmi_ctrl_open,
4274 .read = seq_read,
4275 .write = dw_hdmi_ctrl_write,
4276 .llseek = seq_lseek,
4277 .release = single_release,
4278 };
4279
dw_hdmi_phy_show(struct seq_file *s, void *v)4280 static int dw_hdmi_phy_show(struct seq_file *s, void *v)
4281 {
4282 struct dw_hdmi *hdmi = s->private;
4283 u32 i;
4284
4285 seq_puts(s, "\n>>>hdmi_phy reg ");
4286 for (i = 0; i < 0x28; i++) {
4287 seq_printf(s, "regs %02x val %04x\n", i, hdmi_phy_i2c_read(hdmi, i));
4288 }
4289 return 0;
4290 }
4291
dw_hdmi_phy_open(struct inode *inode, struct file *file)4292 static int dw_hdmi_phy_open(struct inode *inode, struct file *file)
4293 {
4294 return single_open(file, dw_hdmi_phy_show, inode->i_private);
4295 }
4296
dw_hdmi_phy_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)4297 static ssize_t dw_hdmi_phy_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
4298 {
4299 struct dw_hdmi *hdmi = ((struct seq_file *)file->private_data)->private;
4300 u32 reg, val;
4301 char kbuf[0x19];
4302
4303 if (copy_from_user(kbuf, buf, count)) {
4304 return -EFAULT;
4305 }
4306 if (sscanf(kbuf, "%x%x", ®, &val) == -1) {
4307 return -EFAULT;
4308 }
4309 if (reg > 0x28) {
4310 dev_err(hdmi->dev, "it is not a hdmi phy register\n");
4311 return count;
4312 }
4313 dev_info(hdmi->dev, "/*******hdmi phy register config******/");
4314 dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
4315 dw_hdmi_phy_i2c_write(hdmi, val, reg);
4316 return count;
4317 }
4318
4319 static const struct file_operations dw_hdmi_phy_fops = {
4320 .owner = THIS_MODULE,
4321 .open = dw_hdmi_phy_open,
4322 .read = seq_read,
4323 .write = dw_hdmi_phy_write,
4324 .llseek = seq_lseek,
4325 .release = single_release,
4326 };
4327
dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi *hdmi)4328 static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi *hdmi)
4329 {
4330 hdmi->debugfs_dir = debugfs_create_dir("dw-hdmi", NULL);
4331 if (IS_ERR(hdmi->debugfs_dir)) {
4332 dev_err(dev, "failed to create debugfs dir!\n");
4333 return;
4334 }
4335 debugfs_create_file("status", 0x100, hdmi->debugfs_dir, hdmi, &dw_hdmi_status_fops);
4336 debugfs_create_file("ctrl", 0x100, hdmi->debugfs_dir, hdmi, &dw_hdmi_ctrl_fops);
4337 debugfs_create_file("phy", 0x100, hdmi->debugfs_dir, hdmi, &dw_hdmi_phy_fops);
4338 }
4339
dw_hdmi_register_hdcp(struct device *dev, struct dw_hdmi *hdmi, u32 val, bool hdcp1x_enable)4340 static void dw_hdmi_register_hdcp(struct device *dev, struct dw_hdmi *hdmi, u32 val, bool hdcp1x_enable)
4341 {
4342 struct dw_hdcp hdmi_hdcp = {
4343 .hdmi = hdmi,
4344 .write = hdmi_writeb,
4345 .read = hdmi_readb,
4346 .regs = hdmi->regs,
4347 .reg_io_width = val,
4348 .enable = hdcp1x_enable,
4349 };
4350 struct platform_device_info hdcp_device_info = {
4351 .parent = dev,
4352 .id = PLATFORM_DEVID_AUTO,
4353 .res = NULL,
4354 .num_res = 0,
4355 .name = DW_HDCP_DRIVER_NAME,
4356 .data = &hdmi_hdcp,
4357 .size_data = sizeof(hdmi_hdcp),
4358 .dma_mask = DMA_BIT_MASK(0x20),
4359 };
4360
4361 hdmi->hdcp_dev = platform_device_register_full(&hdcp_device_info);
4362 if (IS_ERR(hdmi->hdcp_dev)) {
4363 dev_err(dev, "failed to register hdcp!\n");
4364 } else {
4365 hdmi->hdcp = hdmi->hdcp_dev->dev.platform_data;
4366 }
4367 }
4368
get_force_logo_property(struct dw_hdmi *hdmi)4369 static int get_force_logo_property(struct dw_hdmi *hdmi)
4370 {
4371 struct device_node *dss;
4372 struct device_node *route;
4373 struct device_node *route_hdmi;
4374
4375 dss = of_find_node_by_name(NULL, "display-subsystem");
4376 if (!dss) {
4377 dev_err(hdmi->dev, "can't find display-subsystem\n");
4378 return -ENODEV;
4379 }
4380
4381 route = of_find_node_by_name(dss, "route");
4382 if (!route) {
4383 dev_err(hdmi->dev, "can't find route\n");
4384 of_node_put(dss);
4385 return -ENODEV;
4386 }
4387 of_node_put(dss);
4388
4389 route_hdmi = of_find_node_by_name(route, "route-hdmi");
4390 if (!route_hdmi) {
4391 dev_err(hdmi->dev, "can't find route-hdmi\n");
4392 of_node_put(route);
4393 return -ENODEV;
4394 }
4395 of_node_put(route);
4396
4397 hdmi->force_logo = of_property_read_bool(route_hdmi, "force-output");
4398
4399 of_node_put(route_hdmi);
4400
4401 return 0;
4402 }
4403
4404 /* -----------------------------------------------------------------------------
4405 * Probe/remove API, used from platforms based on the DRM bridge API.
4406 */
dw_hdmi_probe(struct platform_device *pdev, const struct dw_hdmi_plat_data *plat_data)4407 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, const struct dw_hdmi_plat_data *plat_data)
4408 {
4409 struct device *dev = &pdev->dev;
4410 struct device_node *np = dev->of_node;
4411 struct device_node *endpoint;
4412 struct platform_device_info pdevinfo;
4413 struct device_node *ddc_node;
4414 struct dw_hdmi_cec_data cec;
4415 struct dw_hdmi *hdmi;
4416 struct resource *iores = NULL;
4417 int irq;
4418 int ret;
4419 u32 val = 1;
4420 u8 prod_id0;
4421 u8 prod_id1;
4422 u8 config0;
4423 u8 config3;
4424 bool hdcp1x_enable = 0;
4425
4426 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
4427 if (!hdmi) {
4428 return ERR_PTR(-ENOMEM);
4429 }
4430
4431 hdmi->connector.stereo_allowed = 1;
4432 hdmi->plat_data = plat_data;
4433 hdmi->dev = dev;
4434 hdmi->sample_rate = 0xbb80;
4435 hdmi->disabled = true;
4436 hdmi->rxsense = true;
4437 hdmi->phy_mask = (u8) ~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
4438 hdmi->mc_clkdis = 0x7f;
4439 hdmi->last_connector_result = connector_status_disconnected;
4440
4441 mutex_init(&hdmi->mutex);
4442 mutex_init(&hdmi->audio_mutex);
4443 mutex_init(&hdmi->cec_notifier_mutex);
4444 spin_lock_init(&hdmi->audio_lock);
4445
4446 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
4447 if (ddc_node) {
4448 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
4449 of_node_put(ddc_node);
4450 if (!hdmi->ddc) {
4451 dev_dbg(hdmi->dev, "failed to read ddc node\n");
4452 return ERR_PTR(-EPROBE_DEFER);
4453 }
4454 } else {
4455 dev_dbg(hdmi->dev, "no ddc property found\n");
4456 }
4457
4458 if (!plat_data->regm) {
4459 const struct regmap_config *reg_config;
4460
4461 of_property_read_u32(np, "reg-io-width", &val);
4462 switch (val) {
4463 case 0x4:
4464 reg_config = &hdmi_regmap_32bit_config;
4465 hdmi->reg_shift = 0x2;
4466 break;
4467 case 1:
4468 reg_config = &hdmi_regmap_8bit_config;
4469 break;
4470 default:
4471 dev_err(dev, "reg-io-width must be 1 or 4\n");
4472 return ERR_PTR(-EINVAL);
4473 }
4474
4475 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4476 hdmi->regs = devm_ioremap_resource(dev, iores);
4477 if (IS_ERR(hdmi->regs)) {
4478 ret = PTR_ERR(hdmi->regs);
4479 goto err_res;
4480 }
4481
4482 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
4483 if (IS_ERR(hdmi->regm)) {
4484 dev_err(dev, "Failed to configure regmap\n");
4485 ret = PTR_ERR(hdmi->regm);
4486 goto err_res;
4487 }
4488 } else {
4489 hdmi->regm = plat_data->regm;
4490 }
4491
4492 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
4493 if (IS_ERR(hdmi->isfr_clk)) {
4494 ret = PTR_ERR(hdmi->isfr_clk);
4495 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
4496 goto err_res;
4497 }
4498
4499 ret = clk_prepare_enable(hdmi->isfr_clk);
4500 if (ret) {
4501 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
4502 goto err_res;
4503 }
4504
4505 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
4506 if (IS_ERR(hdmi->iahb_clk)) {
4507 ret = PTR_ERR(hdmi->iahb_clk);
4508 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
4509 goto err_isfr;
4510 }
4511
4512 ret = clk_prepare_enable(hdmi->iahb_clk);
4513 if (ret) {
4514 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
4515 goto err_isfr;
4516 }
4517
4518 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
4519 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
4520 hdmi->cec_clk = NULL;
4521 } else if (IS_ERR(hdmi->cec_clk)) {
4522 ret = PTR_ERR(hdmi->cec_clk);
4523 if (ret != -EPROBE_DEFER) {
4524 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", ret);
4525 }
4526
4527 hdmi->cec_clk = NULL;
4528 goto err_iahb;
4529 } else {
4530 ret = clk_prepare_enable(hdmi->cec_clk);
4531 if (ret) {
4532 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", ret);
4533 goto err_iahb;
4534 }
4535 }
4536
4537 /* Product and revision IDs */
4538 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 0x8) | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
4539 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
4540 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
4541 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
4542 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", hdmi->version, prod_id0, prod_id1);
4543 ret = -ENODEV;
4544 goto err_iahb;
4545 }
4546
4547 ret = dw_hdmi_detect_phy(hdmi);
4548 if (ret < 0) {
4549 goto err_iahb;
4550 }
4551
4552 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", hdmi->version >> 0xc, hdmi->version & 0xfff,
4553 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", hdmi->phy.name);
4554
4555 ret = get_force_logo_property(hdmi);
4556 if (ret) {
4557 goto err_iahb;
4558 }
4559
4560 hdmi->initialized = false;
4561 ret = hdmi_readb(hdmi, HDMI_PHY_STAT0);
4562 if (((ret & HDMI_PHY_TX_PHY_LOCK) && (ret & HDMI_PHY_HPD) && hdmi_readb(hdmi, HDMI_FC_EXCTRLDUR)) ||
4563 hdmi->force_logo) {
4564 hdmi->mc_clkdis = hdmi_readb(hdmi, HDMI_MC_CLKDIS);
4565 hdmi->disabled = false;
4566 hdmi->bridge_is_on = true;
4567 hdmi->phy.enabled = true;
4568 hdmi->initialized = true;
4569 } else if (ret & HDMI_PHY_TX_PHY_LOCK) {
4570 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
4571 }
4572
4573 init_hpd_work(hdmi);
4574
4575 irq = platform_get_irq(pdev, 0);
4576 if (irq < 0) {
4577 ret = irq;
4578 goto err_iahb;
4579 }
4580
4581 hdmi->irq = irq;
4582 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, dw_hdmi_irq, IRQF_SHARED, dev_name(dev), hdmi);
4583 if (ret) {
4584 goto err_iahb;
4585 }
4586
4587 /*
4588 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
4589 * N and cts values before enabling phy
4590 */
4591 hdmi_init_clk_regenerator(hdmi);
4592
4593 /* If DDC bus is not specified, try to register HDMI I2C bus */
4594 if (!hdmi->ddc) {
4595 /* Look for (optional) stuff related to unwedging */
4596 hdmi->pinctrl = devm_pinctrl_get(dev);
4597 if (!IS_ERR(hdmi->pinctrl)) {
4598 hdmi->unwedge_state = pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
4599 hdmi->default_state = pinctrl_lookup_state(hdmi->pinctrl, "default");
4600
4601 if (IS_ERR(hdmi->default_state) || IS_ERR(hdmi->unwedge_state)) {
4602 if (!IS_ERR(hdmi->unwedge_state)) {
4603 dev_warn(dev, "Unwedge requires default pinctrl\n");
4604 }
4605 hdmi->default_state = NULL;
4606 hdmi->unwedge_state = NULL;
4607 }
4608 }
4609
4610 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
4611 if (IS_ERR(hdmi->ddc)) {
4612 hdmi->ddc = NULL;
4613 }
4614 /*
4615 * Read high and low time from device tree. If not available use
4616 * the default timing scl clock rate is about 99.6KHz.
4617 */
4618 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns", &hdmi->i2c->scl_high_ns)) {
4619 hdmi->i2c->scl_high_ns = 0x1264;
4620 }
4621 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns", &hdmi->i2c->scl_low_ns)) {
4622 hdmi->i2c->scl_low_ns = 0x1334;
4623 }
4624 }
4625
4626 dw_hdmi_init_hw(hdmi);
4627
4628 hdmi->bridge.driver_private = hdmi;
4629 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
4630 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
4631 #ifdef CONFIG_OF
4632 hdmi->bridge.of_node = pdev->dev.of_node;
4633 #endif
4634
4635 endpoint = of_graph_get_endpoint_by_regs(hdmi->dev->of_node, 1, -1);
4636 if (endpoint && of_device_is_available(endpoint)) {
4637 struct device_node *remote;
4638
4639 remote = of_graph_get_remote_port_parent(endpoint);
4640 of_node_put(endpoint);
4641 if (!remote || !of_device_is_available(remote)) {
4642 of_node_put(remote);
4643 ret = -ENODEV;
4644 goto err_iahb;
4645 }
4646
4647 hdmi->next_bridge = of_drm_find_bridge(remote);
4648 of_node_put(remote);
4649 if (!hdmi->next_bridge) {
4650 dev_err(hdmi->dev, "can't find next bridge\n");
4651 ret = -EPROBE_DEFER;
4652 goto err_iahb;
4653 }
4654
4655 hdmi->sink_is_hdmi = true;
4656 hdmi->sink_has_audio = true;
4657 }
4658
4659 memset(&pdevinfo, 0, sizeof(pdevinfo));
4660 pdevinfo.parent = dev;
4661 pdevinfo.id = PLATFORM_DEVID_AUTO;
4662
4663 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
4664 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
4665 if (iores && (config3 & HDMI_CONFIG3_AHBAUDDMA)) {
4666 struct dw_hdmi_audio_data audio;
4667 audio.phys = iores->start;
4668 audio.base = hdmi->regs;
4669 audio.irq = irq;
4670 audio.hdmi = hdmi;
4671 audio.eld = hdmi->connector.eld;
4672 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
4673 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
4674
4675 pdevinfo.name = "dw-hdmi-ahb-audio";
4676 pdevinfo.data = &audio;
4677 pdevinfo.size_data = sizeof(audio);
4678 pdevinfo.dma_mask = DMA_BIT_MASK(0x20);
4679 hdmi->audio = platform_device_register_full(&pdevinfo);
4680 } else if (config0 & HDMI_CONFIG0_I2S) {
4681 struct dw_hdmi_i2s_audio_data audio;
4682
4683 audio.hdmi = hdmi;
4684 audio.eld = hdmi->connector.eld;
4685 audio.write = hdmi_writeb;
4686 audio.read = hdmi_readb;
4687 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
4688 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
4689
4690 pdevinfo.name = "dw-hdmi-i2s-audio";
4691 pdevinfo.data = &audio;
4692 pdevinfo.size_data = sizeof(audio);
4693 pdevinfo.dma_mask = DMA_BIT_MASK(0x20);
4694 hdmi->audio = platform_device_register_full(&pdevinfo);
4695 }
4696
4697 if (config0 & HDMI_CONFIG0_CEC) {
4698 cec.hdmi = hdmi;
4699 cec.ops = &dw_hdmi_cec_ops;
4700 cec.irq = irq;
4701
4702 pdevinfo.name = "dw-hdmi-cec";
4703 pdevinfo.data = &cec;
4704 pdevinfo.size_data = sizeof(cec);
4705 pdevinfo.dma_mask = 0;
4706
4707 hdmi->cec = platform_device_register_full(&pdevinfo);
4708 }
4709
4710 hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable);
4711 if (IS_ERR(hdmi->extcon)) {
4712 ret = PTR_ERR(hdmi->extcon);
4713 dev_err(hdmi->dev, "allocate extcon failed: %d\n", ret);
4714 goto err_iahb;
4715 }
4716
4717 ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon);
4718 if (ret) {
4719 dev_err(hdmi->dev, "failed to register extcon: %d\n", ret);
4720 goto err_iahb;
4721 }
4722
4723 ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI, EXTCON_PROP_DISP_HPD);
4724 if (ret) {
4725 dev_err(hdmi->dev, "failed to set USB property capability: %d\n", ret);
4726 goto err_iahb;
4727 }
4728
4729 drm_bridge_add(&hdmi->bridge);
4730
4731 dw_hdmi_register_debugfs(dev, hdmi);
4732
4733 if (of_property_read_bool(np, "scramble-low-rates")) {
4734 hdmi->scramble_low_rates = true;
4735 }
4736
4737 if (of_property_read_bool(np, "hdcp1x-enable")) {
4738 hdcp1x_enable = 1;
4739 }
4740 dw_hdmi_register_hdcp(dev, hdmi, val, hdcp1x_enable);
4741
4742 return hdmi;
4743
4744 err_iahb:
4745 clk_disable_unprepare(hdmi->iahb_clk);
4746 if (hdmi->cec_clk) {
4747 clk_disable_unprepare(hdmi->cec_clk);
4748 }
4749 err_isfr:
4750 clk_disable_unprepare(hdmi->isfr_clk);
4751 err_res:
4752 if (hdmi->i2c) {
4753 i2c_del_adapter(&hdmi->i2c->adap);
4754 } else {
4755 i2c_put_adapter(hdmi->ddc);
4756 }
4757
4758 return ERR_PTR(ret);
4759 }
4760 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
4761
dw_hdmi_remove(struct dw_hdmi *hdmi)4762 void dw_hdmi_remove(struct dw_hdmi *hdmi)
4763 {
4764 if (hdmi->irq) {
4765 disable_irq(hdmi->irq);
4766 }
4767
4768 cancel_delayed_work(&hdmi->work);
4769 flush_workqueue(hdmi->workqueue);
4770 destroy_workqueue(hdmi->workqueue);
4771
4772 debugfs_remove_recursive(hdmi->debugfs_dir);
4773
4774 drm_bridge_remove(&hdmi->bridge);
4775
4776 if (hdmi->audio && !IS_ERR(hdmi->audio)) {
4777 platform_device_unregister(hdmi->audio);
4778 }
4779 if (hdmi->hdcp_dev && !IS_ERR(hdmi->hdcp_dev)) {
4780 platform_device_unregister(hdmi->hdcp_dev);
4781 }
4782 if (!IS_ERR(hdmi->cec)) {
4783 platform_device_unregister(hdmi->cec);
4784 }
4785
4786 /* Disable all interrupts */
4787 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
4788
4789 if (!hdmi->next_bridge) {
4790 dw_hdmi_destroy_properties(hdmi);
4791 hdmi->connector.funcs->destroy(&hdmi->connector);
4792 }
4793
4794 if (hdmi->bridge.encoder) {
4795 hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder);
4796 }
4797
4798 clk_disable_unprepare(hdmi->iahb_clk);
4799 clk_disable_unprepare(hdmi->isfr_clk);
4800 if (hdmi->cec_clk) {
4801 clk_disable_unprepare(hdmi->cec_clk);
4802 }
4803
4804 if (hdmi->i2c) {
4805 i2c_del_adapter(&hdmi->i2c->adap);
4806 } else {
4807 i2c_put_adapter(hdmi->ddc);
4808 }
4809 }
4810 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
4811
4812 /* -----------------------------------------------------------------------------
4813 * Bind/unbind API, used from platforms based on the component framework.
4814 */
dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, struct dw_hdmi_plat_data *plat_data)4815 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
4816 struct dw_hdmi_plat_data *plat_data)
4817 {
4818 struct dw_hdmi *hdmi;
4819 int ret;
4820
4821 hdmi = dw_hdmi_probe(pdev, plat_data);
4822 if (IS_ERR(hdmi)) {
4823 return hdmi;
4824 }
4825
4826 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
4827 if (ret) {
4828 dw_hdmi_remove(hdmi);
4829 DRM_ERROR("Failed to initialize bridge with drm\n");
4830 return ERR_PTR(ret);
4831 }
4832
4833 if (!hdmi->next_bridge) {
4834 plat_data->connector = &hdmi->connector;
4835 }
4836
4837 return hdmi;
4838 }
4839 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
4840
dw_hdmi_unbind(struct dw_hdmi *hdmi)4841 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
4842 {
4843 dw_hdmi_remove(hdmi);
4844 }
4845 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
4846
dw_hdmi_reg_initial(struct dw_hdmi *hdmi)4847 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
4848 {
4849 if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
4850 initialize_hdmi_ih_mutes(hdmi);
4851 /* unmute cec irq */
4852 hdmi_writeb(hdmi, 0x68, HDMI_IH_MUTE_CEC_STAT0);
4853
4854 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, HDMI_PHY_I2CM_INT_ADDR);
4855
4856 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
4857 HDMI_PHY_I2CM_CTLINT_ADDR);
4858
4859 if (!hdmi->next_bridge) {
4860 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
4861 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
4862 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), HDMI_IH_MUTE_PHY_STAT0);
4863 }
4864 }
4865 }
4866
dw_hdmi_suspend(struct dw_hdmi *hdmi)4867 void dw_hdmi_suspend(struct dw_hdmi *hdmi)
4868 {
4869 if (!hdmi) {
4870 return;
4871 }
4872
4873 mutex_lock(&hdmi->mutex);
4874
4875 /*
4876 * When system shutdown, hdmi should be disabled.
4877 * When system suspend, dw_hdmi_bridge_disable will disable hdmi first.
4878 * To prevent duplicate operation, we should determine whether hdmi
4879 * has been disabled.
4880 */
4881 if (!hdmi->disabled) {
4882 hdmi->disabled = true;
4883 dw_hdmi_update_power(hdmi);
4884 dw_hdmi_update_phy_mask(hdmi);
4885 }
4886 mutex_unlock(&hdmi->mutex);
4887
4888 if (hdmi->irq) {
4889 disable_irq(hdmi->irq);
4890 }
4891 cancel_delayed_work(&hdmi->work);
4892 flush_workqueue(hdmi->workqueue);
4893 pinctrl_pm_select_sleep_state(hdmi->dev);
4894 }
4895 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
4896
dw_hdmi_resume(struct dw_hdmi *hdmi)4897 void dw_hdmi_resume(struct dw_hdmi *hdmi)
4898 {
4899 if (!hdmi) {
4900 return;
4901 }
4902
4903 pinctrl_pm_select_default_state(hdmi->dev);
4904 mutex_lock(&hdmi->mutex);
4905 dw_hdmi_reg_initial(hdmi);
4906 if (hdmi->i2c) {
4907 dw_hdmi_i2c_init(hdmi);
4908 }
4909 if (hdmi->irq) {
4910 enable_irq(hdmi->irq);
4911 }
4912 /*
4913 * HDMI status maybe incorrect in the following condition:
4914 * HDMI plug in -> system sleep -> HDMI plug out -> system wake up.
4915 * At this time, cat /sys/class/drm/card 0-HDMI-A-1/status is connected.
4916 * There is no hpd interrupt, because HDMI is powerdown during suspend.
4917 * So we need check the current HDMI status in this case.
4918 */
4919 if (hdmi->connector.status == connector_status_connected) {
4920 if (hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data) == connector_status_disconnected) {
4921 hdmi->hpd_state = false;
4922 mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(0x14));
4923 }
4924 }
4925 mutex_unlock(&hdmi->mutex);
4926 }
4927 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
4928
4929 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
4930 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
4931 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
4932 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
4933 MODULE_DESCRIPTION("DW HDMI transmitter driver");
4934 MODULE_LICENSE("GPL");
4935 MODULE_ALIAS("platform:dw-hdmi");
4936