1 /*
2 * Copyright (c) 2020-2021 Huawei Device Co., Ltd.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "plic.h"
17 #include "soc.h"
18 #include "los_reg.h"
19 #include "los_arch_interrupt.h"
20 #include "los_debug.h"
21
22 #ifdef __cplusplus
23 #if __cplusplus
24 extern "C" {
25 #endif
26 #endif
27
OsMachineExternalInterrupt(VOID *arg)28 STATIC VOID OsMachineExternalInterrupt(VOID *arg)
29 {
30 volatile UINT32 *plicReg = (volatile UINT32 *)(PLIC_REG_BASE + 0x4);
31 UINT32 irqNum, saveIrqNum;
32
33 READ_UINT32(irqNum, plicReg);
34 saveIrqNum = irqNum;
35
36 if ((irqNum >= OS_RISCV_CUSTOM_IRQ_VECTOR_CNT) || (irqNum == 0)) {
37 HalHwiDefaultHandler((VOID *)irqNum);
38 }
39
40 irqNum += RISCV_SYS_MAX_IRQ;
41
42 g_hwiForm[irqNum].pfnHook(g_hwiForm[irqNum].uwParam);
43
44 WRITE_UINT32(saveIrqNum, plicReg);
45 }
46
47 #define OS_PLIC_MAX ((OS_RISCV_CUSTOM_IRQ_VECTOR_CNT >> 5) + 1)
48
PlicIrqInitnull49 VOID PlicIrqInit(VOID)
50 {
51 volatile UINT32 *plicPrioReg = (volatile UINT32 *)PLIC_PRIO_BASE;
52 volatile UINT32 *plicEnReg = (volatile UINT32 *)PLIC_ENABLE_BASE;
53 volatile UINT32 *plicReg = (volatile UINT32 *)PLIC_REG_BASE;
54 INT32 i;
55 UINT32 ret;
56
57 for (i = 0; i < OS_PLIC_MAX; i++) {
58 WRITE_UINT32(0x0, plicEnReg);
59 plicEnReg++;
60 }
61
62 for (i = 0; i < OS_RISCV_CUSTOM_IRQ_VECTOR_CNT; i++) {
63 WRITE_UINT32(0x0, plicPrioReg);
64 plicPrioReg++;
65 }
66
67 WRITE_UINT32(0, plicReg);
68
69 ret = LOS_HwiCreate(RISCV_MACH_EXT_IRQ, 0x1, 0, OsMachineExternalInterrupt, 0);
70 if (ret != LOS_OK) {
71 PRINT_ERR("Create machine external failed! ret : 0x%x\n", ret);
72 }
73 }
74
PlicIrqSetPrio(UINT32 vector, UINT32 pri)75 VOID PlicIrqSetPrio(UINT32 vector, UINT32 pri)
76 {
77 volatile UINT32 *plicReg = (volatile UINT32 *)PLIC_PRIO_BASE;
78
79 plicReg += (vector - RISCV_SYS_MAX_IRQ);
80 WRITE_UINT32(pri, plicReg);
81 }
82
PlicIrqEnable(UINT32 vector)83 VOID PlicIrqEnable(UINT32 vector)
84 {
85 UINT32 irqValue;
86 UINT32 locIrq = vector - RISCV_SYS_MAX_IRQ;
87 volatile UINT32 *plicReg = (volatile UINT32 *)PLIC_ENABLE_BASE;
88
89 plicReg += (locIrq >> 5); /* 5： The PLIC interrupt controls the bit width */
90 READ_UINT32(irqValue, plicReg);
91 irqValue |= (1 << (locIrq & 31)); /* 31: plic irq mask */
92 WRITE_UINT32(irqValue, plicReg);
93 }
94
PlicIrqDisable(UINT32 vector)95 VOID PlicIrqDisable(UINT32 vector)
96 {
97 UINT32 irqValue;
98 UINT32 locIrq = vector - RISCV_SYS_MAX_IRQ;
99 volatile UINT32 *plicReg = (volatile UINT32 *)PLIC_ENABLE_BASE;
100
101 plicReg += (locIrq >> 5); /* 5： The PLIC interrupt controls the bit width */
102 READ_UINT32(irqValue, plicReg);
103 irqValue &= ~(1 << (locIrq & 31)); /* 31: plic irq mask */
104 WRITE_UINT32(irqValue, plicReg);
105 }
106
107 #ifdef __cplusplus
108 #if __cplusplus
109 }
110 #endif /* __cplusplus */
111 #endif /* __cplusplus */
112
113