| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsBranchExpansion.cpp | 372 unsigned JIC = ABI.IsN64() ? Mips::JIC64 : Mips::JIC; in buildProperJumpMI() local
380 JumpOp = HasR6 ? JIC : JR; in buildProperJumpMI()
382 if (JumpOp == Mips::JIC && STI->inMicroMipsMode()) in buildProperJumpMI()
451 // jic $at, 0 in expandToLongBranch()
559 // jic $at, 0 in expandToLongBranch()
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| H A D | MipsInstrInfo.cpp | 534 // For MIPSR6, the instruction 'jic' can be used for these cases. Some in getEquivalentCompactForm()
535 // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'. in getEquivalentCompactForm()
542 return Mips::JIC; in getEquivalentCompactForm()
644 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
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| H A D | Mips32r6InstrInfo.td | 496 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
915 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
1003 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
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| H A D | Mips64r6InstrInfo.td | 102 class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd,
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| H A D | MicroMips32r6InstrInfo.td | 486 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
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| H A D | MipsScheduleGeneric.td | 320 BLTZC, BNEC, BNEZC, BNVC, BOVC, JIC, JR_HB_R6,
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | assembler-mips-inl.h | 132 // Encoded internal references are lui/jic load of 32-bit absolute address. in set_target_internal_reference_encoded_at()
214 // Encoded internal references are lui/ori or lui/jic load of 32-bit in target_internal_reference()
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| H A D | assembler-mips.cc | 754 // Use just lui and jic instructions. Insert lower part of the target address in
755 // jic offset part. Since jic sign-extends offset and then add it with register,
758 // in jic register with lui instruction.
1767 void Assembler::jic(Register rt, int16_t offset) { in jic() function in v8::internal::Assembler
3710 // lui/jic, aui/jic or lui/jialc. in target_address_at()
3738 // On r6, target address is stored in a lui/jic pair, and both instr have to be
3752 // Must use 2 instructions to insure patchable code => use lui and jic in set_target_value_at()
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| H A D | constants-mips.h | 485 POP66 = ((6U << 3) + 6) << kOpcodeShift, // beqzc, jic
737 JIC = ((0U << 5) + 0),
1873 case POP66: // beqzc, jic
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| H A D | macro-assembler-mips.cc | 3612 jic(target, offset); in CallRecordWriteStub()
3616 jic(target, offset); in CallRecordWriteStub()
3641 jic(base, offset); in CallRecordWriteStub()
3645 jic(base, offset); in CallRecordWriteStub()
3677 jic(target, jic_offset); in CallRecordWriteStub()
3681 jic(target, jic_offset); in CallRecordWriteStub()
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| H A D | assembler-mips.h | 490 void jic(Register rt, int16_t offset);
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| /kernel/linux/linux-5.10/drivers/atm/ |
| H A D | idt77105.c | 224 /* This should not happen (restart timer does it) but JIC */ in idt77105_int()
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| /kernel/linux/linux-6.6/drivers/atm/ |
| H A D | idt77105.c | 224 /* This should not happen (restart timer does it) but JIC */ in idt77105_int()
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| H A D | branch.c | 800 /* Compact branch: BEQZC || JIC */ in __compute_return_epc_for_insn()
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| /kernel/linux/linux-6.6/arch/mips/kernel/ |
| H A D | branch.c | 800 /* Compact branch: BEQZC || JIC */ in __compute_return_epc_for_insn()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 786 JIC = ((0U << 5) + 0),
1970 case POP66: // beqzc, jic
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| H A D | macro-assembler-mips64.cc | 4254 jic(target, 0); in CallRecordWriteStub()
4258 jic(target, 0); in CallRecordWriteStub()
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| H A D | assembler-mips64.h | 486 void jic(Register rt, int16_t offset);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| H A D | MipsGenAsmMatcher.inc | 5027 "jalrs16\004jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiu"
6780 { 5362 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6781 { 5362 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6782 { 5362 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6797 { 5390 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, { MCK_GPR32AsmReg }, },
10049 { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10050 { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10051 { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10052 { 5362 /* jic */,
[all...] |
| H A D | MipsGenAsmWriter.inc | 2942 18384U, // JIC
5696 0U, // JIC
7716 {Mips::JIC, 152, 1 },
8065 // Mips::JIC - 152
8706 // (JIC GPR32Opnd:$rs, 0) - 388
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| H A D | MipsGenMCCodeEmitter.inc | 1714 UINT64_C(3623878656), // JIC
6734 case Mips::JIC:
11176 CEFBS_HasStdEnc_HasMips32r6, // JIC = 1701
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| /third_party/node/deps/v8/src/diagnostics/mips64/ |
| H A D | disasm-mips64.cc | 2026 if (instr->RsValue() == JIC) { in DecodeTypeImmediate()
2027 Format(instr, "jic 'rt, 'imm16s"); in DecodeTypeImmediate()
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| /third_party/node/deps/v8/src/diagnostics/mips/ |
| H A D | disasm-mips.cc | 1796 if (instr->RsValue() == JIC) { in DecodeTypeImmediate()
1797 Format(instr, "jic 'rt, 'imm16s"); in DecodeTypeImmediate()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 6865 case POP66: // BEQZC, JIC
6868 } else { // JIC
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 6558 case POP66: // BEQZC, JIC
6561 } else { // JIC
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