| /third_party/ffmpeg/libavcodec/mips/ |
| H A D | vp8_idct_msa.c | 51 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in ff_vp8_idct_add_msa() local
64 VP8_IDCT_1D_W(hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3); in ff_vp8_idct_add_msa()
65 SRARI_W4_SW(vt0, vt1, vt2, vt3, 3); in ff_vp8_idct_add_msa()
67 TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3); in ff_vp8_idct_add_msa()
73 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in ff_vp8_idct_add_msa()
109 v4i32 hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in ff_vp8_luma_dc_wht_msa() local
120 BUTTERFLY_4(a1, d1, c1, b1, vt0, vt1, vt3, vt2); in ff_vp8_luma_dc_wht_msa()
121 ADD4(vt0, 3, vt1, 3, vt2, 3, vt3, 3, vt0, vt1, vt2, vt3); in ff_vp8_luma_dc_wht_msa()
[all...] |
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 1199 void St1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in St1() argument
1202 st1(vt, vt2, vt3, dst); in St1()
1204 void St1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in St1() argument
1207 st1(vt, vt2, vt3, vt4, dst); in St1()
1640 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld1() argument
1643 ld1(vt, vt2, vt3, src); in Ld1()
1645 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld1() argument
1648 ld1(vt, vt2, vt3, vt4, src); in Ld1()
1671 void Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld3() argument
1674 ld3(vt, vt2, vt3, sr in Ld3()
1676 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) Ld3() argument
1681 Ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) Ld3r() argument
1686 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) Ld4() argument
1691 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) Ld4() argument
1696 Ld4r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) Ld4r() argument
1705 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& dst) St3() argument
1710 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& dst) St4() argument
1720 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) St3() argument
1725 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) St4() argument
[all...] |
| H A D | assembler-arm64.cc | 2355 const VRegister& vt3, const MemOperand& src) { in ld1()
2357 USE(vt3); in ld1()
2358 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld1()
2359 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld1()
2364 const VRegister& vt3, const VRegister& vt4, in ld1()
2367 USE(vt3); in ld1()
2369 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld1()
2370 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld1()
2399 const VRegister& vt3, const MemOperand& src) { in ld3()
2401 USE(vt3); in ld3()
2354 ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) ld1() argument
2363 ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) ld1() argument
2398 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) ld3() argument
2407 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) ld3() argument
2416 ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) ld3r() argument
2425 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) ld4() argument
2436 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) ld4() argument
2447 ld4r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) ld4r() argument
2470 st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) st1() argument
2479 st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) st1() argument
2506 st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& dst) st3() argument
2515 st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) st3() argument
2524 st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& dst) st4() argument
2535 st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) st4() argument
[all...] |
| H A D | assembler-arm64.h | 1230 void st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1234 void st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1248 void st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1252 void st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1256 void st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1260 void st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1844 void ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1848 void ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1868 void ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
1872 void ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
[all...] |
| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 389 VRegister vt3((vt.GetCode() + 2) % kNumberOfVRegisters, kQRegSize); in GenerateNEONSequence()
393 VIXL_ASSERT(!kCalleeSavedV.IncludesAliasOf(vt3)); in GenerateNEONSequence()
395 __ Ld3(vt.V4S(), vt2.V4S(), vt3.V4S(), MemOperand(scratch)); in GenerateNEONSequence()
396 __ St4(vt.V16B(), vt2.V16B(), vt3.V16B(), vt4.V16B(), MemOperand(scratch)); in GenerateNEONSequence()
|
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 2607 const VRegister& vt3, in ld1()
2609 USE(vt2, vt3); in ld1()
2611 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3)); in ld1()
2612 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3)); in ld1()
2619 const VRegister& vt3, in ld1()
2622 USE(vt2, vt3, vt4); in ld1()
2624 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4)); in ld1()
2625 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4)); in ld1()
2666 const VRegister& vt3, in ld3()
2668 USE(vt2, vt3); in ld3()
2605 ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) ld1() argument
2617 ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) ld1() argument
2664 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) ld3() argument
2676 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) ld3() argument
2689 ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) ld3r() argument
2701 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) ld4() argument
2714 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) ld4() argument
2728 ld4r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) ld4r() argument
2758 st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) st1() argument
2770 st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) st1() argument
2806 st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& dst) st3() argument
2818 st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) st3() argument
2831 st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& dst) st4() argument
2844 st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) st4() argument
[all...] |
| H A D | macro-assembler-aarch64.h | 3359 const VRegister& vt3, in Ld1()
3363 ld1(vt, vt2, vt3, src); in Ld1()
3367 const VRegister& vt3, in Ld1()
3372 ld1(vt, vt2, vt3, vt4, src); in Ld1()
3404 const VRegister& vt3, in Ld3()
3408 ld3(vt, vt2, vt3, src); in Ld3()
3412 const VRegister& vt3, in Ld3()
3417 ld3(vt, vt2, vt3, lane, src); in Ld3()
3421 const VRegister& vt3, in Ld3r()
3425 ld3r(vt, vt2, vt3, sr in Ld3r()
3357 Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) Ld1() argument
3365 Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) Ld1() argument
3402 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) Ld3() argument
3410 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) Ld3() argument
3419 Ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) Ld3r() argument
3427 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) Ld4() argument
3436 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) Ld4() argument
3446 Ld4r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) Ld4r() argument
3526 St1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& dst) St1() argument
3534 St1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& dst) St1() argument
3553 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& dst) St3() argument
3561 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& dst) St4() argument
3578 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) St3() argument
3587 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) St4() argument
[all...] |
| H A D | assembler-aarch64.h | 2880 const VRegister& vt3,
2886 const VRegister& vt3,
2911 const VRegister& vt3,
2917 const VRegister& vt3,
2924 const VRegister& vt3,
2930 const VRegister& vt3,
2937 const VRegister& vt3,
2945 const VRegister& vt3,
3084 const VRegister& vt3,
3090 const VRegister& vt3,
[all...] |
| /third_party/skia/third_party/externals/libwebp/src/dsp/ |
| H A D | dec_msa.c | 45 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in TransformOne() local
55 IDCT_1D_W(hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3); in TransformOne()
56 SRARI_W4_SW(vt0, vt1, vt2, vt3, 3); in TransformOne()
57 TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3); in TransformOne()
63 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in TransformOne()
|
| H A D | enc_msa.c | 47 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in ITransformOne() local
57 IDCT_1D_W(hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3); in ITransformOne()
58 SRARI_W4_SW(vt0, vt1, vt2, vt3, 3); in ITransformOne()
59 TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3); in ITransformOne()
65 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in ITransformOne()
|