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Searched refs:vswp (Results 1 - 23 of 23) sorted by relevance

/third_party/ffmpeg/libavcodec/arm/
H A Dvp9lpf_16bpp_neon.S24 vswp \r1, \r8 @ vtrn.64 \rq0, \rq4
25 vswp \r3, \r10 @ vtrn.64 \rq1, \rq5
26 vswp \r5, \r12 @ vtrn.64 \rq2, \rq6
27 vswp \r7, \r14 @ vtrn.64 \rq3, \rq7
H A Dfft_neon.S141 vswp d25, d26 @ q12{r8,i8,i10,r11} q13{r9,i9,i11,r10}
143 vswp d29, d30 @ q14{r12,i12,i14,r15} q15{r13,i13,i15,r14}
152 vswp d1, d26 @ q0{t1,t2,t3,t4} q13{t6,t5,t7,t8}
153 vswp d3, d30 @ q1{t1a,t2a,t3a,t4a} q15{t6a,t5a,t7a,t8a}
159 vswp d25, d28 @ q12{r8,i8,r12,i12} q14{r9,i9,r13,i13}
165 vswp d27, d30 @ q13{r10,i10,r14,i14} q15{r11,i11,r15,i15}
220 vswp d21, d22
248 vswp d21, d22
H A Dsbrdsp_neon.S95 vswp d0, d1
101 vswp d18, d19
111 vswp d0, d1
114 vswp d4, d5
131 vswp d2, d3
139 vswp d6, d7
H A Dh264idct_neon.S28 vswp d1, d2
46 vswp d1, d3
206 vswp d21, d4
208 vswp d17, d24
210 vswp d19, d26
212 vswp d23, d30
H A Dvc1dsp_neon.S145 vswp d4, d5 @ q2 = src[48]|src[16]
162 vswp d2, d3 @ q1 = src[40]|src[8]
164 vswp d6, d7 @ q3 = src[56]|src[24]
167 vswp d3, d6 @ q1 = src[40]|src[56], q3 = src[8]|src[24]
172 vswp d6, d7 @ q3 = src[24]|src[8]
173 vswp d2, d3 @ q1 = src[56]|src[40]
184 vswp d22, d23 @ q11 = t7|t8
604 vswp d1, d2 @ so that we can later access column 1 and column 3 as a single q1 register
630 vswp d2, d3 @ so that we can later access column 1 and column 3 in order as a single q1 register
H A Dvp3dsp_neon.S255 vswp d17, d24
256 vswp d19, d26
258 vswp d21, d28
260 vswp d23, d30
H A Drv34dsp_neon.S47 vswp d3, d6
48 vswp d5, d16
H A Dsbcdsp_neon.S547 vswp d5, d20
566 vswp d5, d20
660 vswp q3, q10
683 vswp q3, q10
H A Drv40dsp_neon.S293 vswp d0, d1
392 vswp d0, d1
531 vswp d0, d1
629 vswp d0, d1
842 vswp d3, d6 @ q1q2, p1p0
912 vswp d4, d5
H A Dhpeldsp_neon.S231 vswp d1, d2
H A Dvp9itxfm_16bpp_neon.S48 vswp \r1, \r4 @ vtrn.64 \rq0, \rq2
49 vswp \r3, \r6 @ vtrn.64 \rq1, \rq3
50 vswp \r9, \r12 @ vtrn.64 \rq4, \rq6
51 vswp \r11, \r14 @ vtrn.64 \rq5, \rq7
414 vswp d5, d16
415 vswp d7, d18
848 vswp d27, d29 @ d27 = t12, d29 = t13a
849 vswp d28, d27 @ d28 = t12, d27 = t11
/third_party/ffmpeg/libavutil/arm/
H A Dfloat_dsp_neon.S182 vswp d22, d23
191 vswp d22, d23
/third_party/node/deps/openssl/openssl/crypto/aes/asm/
H A Dbsaes-armv7.pl1718 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
1735 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
1788 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2133 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2150 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2203 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2413 vswp `&Dhi("@XMM[6]")`,`&Dlo("@XMM[6]")`
/third_party/openssl/crypto/aes/asm/
H A Dbsaes-armv7.pl1718 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
1735 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
1788 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2133 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2150 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2203 vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")`
2413 vswp `&Dhi("@XMM[6]")`,`&Dlo("@XMM[6]")`
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc2275 Format(instr, q ? "vswp 'Qd, 'Qm" : "vswp 'Dd, 'Dm"); in DecodeAdvancedSIMDTwoOrThreeRegisters()
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.h6075 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
6076 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } in vswp() function in vixl::aarch32::Assembler
6077 void vswp(DRegister rd, DRegister rm) { in vswp() function in vixl::aarch32::Assembler
6078 vswp(al, kDataTypeValueNone, rd, rm); in vswp()
6080 void vswp(Condition cond, DRegister rd, DRegister rm) { in vswp() function in vixl::aarch32::Assembler
6081 vswp(cond, kDataTypeValueNone, rd, rm); in vswp()
6084 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
6085 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(a function in vixl::aarch32::Assembler
6086 void vswp(QRegister rd, QRegister rm) { vswp() function in vixl::aarch32::Assembler
6089 void vswp(Condition cond, QRegister rd, QRegister rm) { vswp() function in vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h2607 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
2609 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
H A Dassembler-aarch32.cc27569 void Assembler::vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) { in vswp() function in vixl::aarch32::Assembler
27587 Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm); in vswp()
27590 void Assembler::vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) { in vswp() function in vixl::aarch32::Assembler
27608 Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm); in vswp()
H A Ddisasm-aarch32.cc6855 void Disassembler::vswp(Condition cond, in vswp() function in vixl::aarch32::Disassembler
6864 void Disassembler::vswp(Condition cond, in vswp() function in vixl::aarch32::Disassembler
[all...]
H A Dmacro-assembler-aarch32.h12566 vswp(cond, dt, rd, rm); in MacroAssembler()
12587 vswp(cond, dt, rd, rm); in MacroAssembler()
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h881 void vswp(DwVfpRegister dst, DwVfpRegister src);
882 void vswp(QwNeonRegister dst, QwNeonRegister src);
H A Dmacro-assembler-arm.cc527 vswp(srcdst0, srcdst1); in Swap()
539 vswp(srcdst0, srcdst1); in Swap()
H A Dassembler-arm.cc4080 DCHECK_EQ(Neon8, size); // size == 0 for vswp in EncodeNeonUnaryOp()
4175 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) { in vswp() function in v8::internal::Assembler
4177 // Dd = vswp(Dn, Dm) SIMD d-register swap. in vswp()
4183 void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) { in vswp() function in v8::internal::Assembler
4184 // Qd = vswp(Qn, Qm) SIMD q-register swap. in vswp()

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