| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | hevcdsp_sao_neon.S | 103 uzp1 v0.16b, v3.16b, v3.16b // sao_offset_val -> lower
160 uzp1 v0.16b, v3.16b, v3.16b
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| H A D | vp9lpf_neon.S | 171 uzp1 v0.16b, v0.16b, v1.16b
172 uzp1 v2.16b, v2.16b, v4.16b
173 uzp1 v3.16b, v3.16b, v5.16b
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| /third_party/ffmpeg/tests/checkasm/aarch64/ |
| H A D | checkasm.S | 153 uzp1 v2.2d, v\reg1\().2d, v\reg2\().2d
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| /third_party/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 640 uzp1(vform, temp1, src1, src2); in addp()
2729 uzp1(vform, src1_r, src1, zero);
2731 uzp1(vform, src2_r, src2, zero);
2770 uzp1(vform, src1_a, src1, zero);
2771 uzp1(vform, src2_a, src2, zero);
2776 uzp1(vform, src2_b, src2, zero);
2779 uzp1(vform, srca_r, srca, zero);
4082 uzp1(vform, src1_a, src1, zero);
4083 uzp1(vform, src2_a, src2, zero);
4088 uzp1(vfor
[all...] |
| H A D | assembler-aarch64.h | 3207 void uzp1(const VRegister& vd, const VRegister& vn, const VRegister& vm);
5852 void uzp1(const PRegisterWithLaneSize& pd,
5857 void uzp1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
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| H A D | simulator-aarch64.cc | 3255 uzp1(vform_half, zn_b, zn, zero); in Simulator()
3256 uzp1(vform_half, zm_b, zm, zero); in Simulator()
9619 uzp1(vf, rd, rn, rm); in Simulator()
13244 uzp1(vform, temp0, temp0, temp1); in Simulator()
13312 uzp1(vform, zd, zn, zm); in Simulator()
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| H A D | macro-assembler-aarch64.h | 2981 V(uzp1, Uzp1) \
6478 uzp1(pd, pn, pm); in Uzp1()
6483 uzp1(zd, zn, zm); in Uzp1()
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| H A D | simulator-aarch64.h | 4120 LogicVRegister uzp1(VectorFormat vform,
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| H A D | assembler-sve-aarch64.cc | 5509 void Assembler::uzp1(const PRegisterWithLaneSize& pd, in uzp1() function in vixl::aarch64::Assembler
5623 void Assembler::uzp1(const ZRegister& zd, in uzp1() function in vixl::aarch64::Assembler
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| H A D | assembler-aarch64.cc | 5431 void Assembler::uzp1(const VRegister& vd,
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2487 __ uzp1(v30.V16B(), v9.V16B(), v17.V16B()); in GenerateTestSequenceNEON()
2488 __ uzp1(v7.V2D(), v26.V2D(), v28.V2D()); in GenerateTestSequenceNEON()
2489 __ uzp1(v26.V2S(), v16.V2S(), v22.V2S()); in GenerateTestSequenceNEON()
2490 __ uzp1(v14.V4H(), v19.V4H(), v6.V4H()); in GenerateTestSequenceNEON()
2491 __ uzp1(v17.V4S(), v23.V4S(), v30.V4S()); in GenerateTestSequenceNEON()
2492 __ uzp1(v28.V8B(), v27.V8B(), v13.V8B()); in GenerateTestSequenceNEON()
2493 __ uzp1(v17.V8H(), v1.V8H(), v12.V8H()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2750 TEST_NEON(uzp1_0, uzp1(v0.V8B(), v1.V8B(), v2.V8B()))
2751 TEST_NEON(uzp1_1, uzp1(v0.V16B(), v1.V16B(), v2.V16B()))
2752 TEST_NEON(uzp1_2, uzp1(v0.V4H(), v1.V4H(), v2.V4H()))
2753 TEST_NEON(uzp1_3, uzp1(v0.V8H(), v1.V8H(), v2.V8H()))
2754 TEST_NEON(uzp1_4, uzp1(v0.V2S(), v1.V2S(), v2.V2S()))
2755 TEST_NEON(uzp1_5, uzp1(v0.V4S(), v1.V4S(), v2.V4S()))
2756 TEST_NEON(uzp1_6, uzp1(v0.V2D(), v1.V2D(), v2.V2D()))
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| H A D | test-disasm-sve-aarch64.cc | 5468 COMPARE(uzp1(p14.VnB(), p4.VnB(), p14.VnB()), "uzp1 p14.b, p4.b, p14.b"); in TEST()
5469 COMPARE(uzp1(p14.VnH(), p4.VnH(), p14.VnH()), "uzp1 p14.h, p4.h, p14.h"); in TEST()
5470 COMPARE(uzp1(p14.VnS(), p4.VnS(), p14.VnS()), "uzp1 p14.s, p4.s, p14.s"); in TEST()
5471 COMPARE(uzp1(p14.VnD(), p4.VnD(), p14.VnD()), "uzp1 p14.d, p4.d, p14.d"); in TEST()
5516 COMPARE(uzp1(z3.VnB(), z27.VnB(), z10.VnB()), "uzp1 z in TEST()
[all...] |
| H A D | test-simulator-aarch64.cc | 4962 DEFINE_TEST_NEON_3SAME(uzp1, Basic)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 677 uzp1(vform, temp1, src1, src2); in addp()
2886 LogicVRegister Simulator::uzp1(VectorFormat vform, LogicVRegister dst, in uzp1() function in v8::internal::Simulator
3611 uzp1(vform, temp1, src1, src2); \
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| H A D | simulator-arm64.h | 1885 LogicVRegister uzp1(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 6030 uzp1(vf, rd, rn, rm);
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1336 void uzp1(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 479 V(uzp1, Uzp1) \
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| H A D | assembler-arm64.cc | 1551 void Assembler::uzp1(const VRegister& vd, const VRegister& vn, in uzp1() function in v8::internal::Assembler
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