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Searched refs:tess_offchip_offset (Results 1 - 7 of 7) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader_llvm_tess.c419 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
481 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_tcs_build_end()
488 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_tcs_build_end()
545 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
610 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
636 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
H A Dsi_shader.c462 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
483 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
558 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
657 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
662 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
H A Dsi_shader_llvm.c788 return ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_llvm_load_intrinsic()
H A Dgfx10_shader_ngg.c1424 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 4); in gfx10_ngg_culling_build_end()
/third_party/mesa3d/src/amd/common/
H A Dac_shader_args.h88 struct ac_arg tess_offchip_offset; member
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_shader_args.c653 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
685 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
704 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
709 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
726 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
H A Dradv_nir_lower_abi.c78 return ac_nir_load_arg(b, &s->args->ac, s->args->ac.tess_offchip_offset); in lower_abi_instr()

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