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Searched refs:regid (Results 1 - 25 of 32) sorted by relevance

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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_shader.c69 * regid's might not even be valid) in fixup_regfootprint()
77 if (v->inputs[i].regid >= regid(48, 0)) in fixup_regfootprint()
82 int32_t regid = v->inputs[i].regid + n; in fixup_regfootprint() local
85 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2); in fixup_regfootprint()
87 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); in fixup_regfootprint()
90 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); in fixup_regfootprint()
97 if (!VALIDREG(v->outputs[i].regid)) in fixup_regfootprint()
99 int32_t regid in fixup_regfootprint() local
113 int32_t regid = v->sampler_prefetch[i].dst + n; fixup_regfootprint() local
701 uint32_t regid; dump_output() local
786 uint8_t regid; ir3_shader_disasm() local
832 uint8_t regid = so->outputs[i].regid; ir3_shader_disasm() local
841 uint8_t regid = so->inputs[i].regid; ir3_shader_disasm() local
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H A Dir3_shader.h483 /* Represents half register in regid */
582 * + From the vert shader, we only need the output regid
598 uint8_t regid; member
623 uint8_t regid; member
1021 uint8_t regid; member
1047 if (regid_ != regid(63, 0)) { in ir3_link_add()
1052 l->var[i].regid = regid_; in ir3_link_add()
1071 const unsigned default_regid = pack_vs_out ? regid(63, 0) : regid(0, 0); in ir3_link_shaders()
1106 k >= 0 ? vs->outputs[k].regid in ir3_link_shaders()
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H A Dir3_compiler_nir.c111 unsigned r = regid(n + dp / 4, dp % 4); in create_driver_param()
944 unsigned ubo = regid(const_state->offsets.ubo, 0); in emit_intrinsic_load_ubo()
1024 unsigned p = regid(const_state->offsets.kernel_params, 0); in emit_intrinsic_load_kernel_input()
2464 cond->dsts[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2481 kill->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2503 cond->dsts[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2523 dst[0]->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2545 dst[0]->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2569 ballot->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
3799 cond->dsts[0]->num = regid(REG_P in emit_stream_out()
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H A Dir3_legalize.c318 ir3_dst_create(baryf, regid(63, 0), 0); in legalize_block()
320 ir3_src_create(baryf, regid(0, 0), 0); in legalize_block()
348 ir3_dst_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI; in legalize_block()
350 ir3_src_create(baryf, regid(0, 0), 0); in legalize_block()
756 ir3_src_create(br1, regid(REG_P0, 0), 0)->def = in block_sched()
763 ir3_src_create(br2, regid(REG_P0, 0), 0)->def = in block_sched()
H A Dir3_legalize_relative.c37 if (reg->num == regid(REG_A0, 0)) in is_dst_a0()
H A Dir3_context.c449 instr->dsts[0]->num = regid(REG_A0, 0); in create_addr0()
460 instr->dsts[0]->num = regid(REG_A0, 1); in create_addr1()
524 cond->dsts[0]->num = regid(REG_P0, 0); in ir3_get_predicate()
H A Dinstr-a3xx.h489 regid(int num, int comp) in regid() function
494 #define INVALID_REG regid(63, 0)
H A Dir3.c76 uint32_t min_const_reg = regid(compiler->shared_consts_base_offset, 0); in is_shared_consts()
78 regid(compiler->shared_consts_base_offset + in is_shared_consts()
119 } else if (max < regid(48, 0)) { in collect_reg_info()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_const.c32 /* regid: base const register
38 const struct ir3_shader_variant *v, uint32_t regid, in fd6_emit_const_user()
41 emit_const_asserts(ring, v, regid, sizedwords); in fd6_emit_const_user()
51 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS, in fd6_emit_const_user()
59 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS, in fd6_emit_const_user()
69 const struct ir3_shader_variant *v, uint32_t regid, in fd6_emit_const_bo()
72 uint32_t dst_off = regid / 4; in fd6_emit_const_bo()
77 emit_const_asserts(ring, v, regid, sizedwords); in fd6_emit_const_bo()
115 const unsigned regid = const_state->offsets.primitive_param; in emit_stage_tess_consts() local
116 int size = MIN2(1 + regid, in emit_stage_tess_consts()
37 fd6_emit_const_user(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords, const uint32_t *dwords) fd6_emit_const_user() argument
68 fd6_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t offset, uint32_t sizedwords, struct fd_bo *bo) fd6_emit_const_bo() argument
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H A Dfd6_compute.c90 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
91 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
93 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
99 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
100 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
102 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
H A Dfd6_program.c363 return regid(63, 0); in next_regid()
371 const unsigned regid = const_state->offsets.primitive_param + 1; variable
374 if (regid >= s->constlen)
378 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid) |
441 vs_primitive_regid = regid(63, 0);
460 tess_coord_x_regid = regid(63, 0);
461 tess_coord_y_regid = regid(63, 0);
462 hs_rel_patch_regid = regid(63, 0);
463 ds_rel_patch_regid = regid(63, 0);
464 ds_primitive_regid = regid(6
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/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
H A Dfd3_emit.c55 /* regid: base const register
61 const struct ir3_shader_variant *v, uint32_t regid, in fd3_emit_const_user()
64 emit_const_asserts(ring, v, regid, sizedwords); in fd3_emit_const_user()
67 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) | in fd3_emit_const_user()
79 const struct ir3_shader_variant *v, uint32_t regid, in fd3_emit_const_bo()
82 uint32_t dst_off = regid / 2; in fd3_emit_const_bo()
91 emit_const_asserts(ring, v, regid, sizedwords); in fd3_emit_const_bo()
103 uint32_t regid, uint32_t num, struct fd_bo **bos, in fd3_emit_const_ptrs()
109 assert((regid % 4) == 0); in fd3_emit_const_ptrs()
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / in fd3_emit_const_ptrs()
60 fd3_emit_const_user(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords, const uint32_t *dwords) fd3_emit_const_user() argument
78 fd3_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t offset, uint32_t sizedwords, struct fd_bo *bo) fd3_emit_const_bo() argument
102 fd3_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type, uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets) fd3_emit_const_ptrs() argument
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H A Dfd3_program.c174 (coord_regid == regid(63, 0)) ? regid(63, 0) : (coord_regid + 2); in fd3_program_emit()
258 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd3_program_emit()
262 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd3_program_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_emit.c51 /* regid: base const register
57 const struct ir3_shader_variant *v, uint32_t regid, in fd4_emit_const_user()
60 emit_const_asserts(ring, v, regid, sizedwords); in fd4_emit_const_user()
63 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | in fd4_emit_const_user()
75 const struct ir3_shader_variant *v, uint32_t regid, in fd4_emit_const_bo()
78 uint32_t dst_off = regid / 4; in fd4_emit_const_bo()
83 emit_const_asserts(ring, v, regid, sizedwords); in fd4_emit_const_bo()
95 uint32_t regid, uint32_t num, struct fd_bo **bos, in fd4_emit_const_ptrs()
101 assert((regid % 4) == 0); in fd4_emit_const_ptrs()
104 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / in fd4_emit_const_ptrs()
56 fd4_emit_const_user(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords, const uint32_t *dwords) fd4_emit_const_user() argument
74 fd4_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t offset, uint32_t sizedwords, struct fd_bo *bo) fd4_emit_const_bo() argument
94 fd4_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type, uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets) fd4_emit_const_ptrs() argument
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H A Dfd4_program.c178 if (pos_regid == regid(63, 0)) { in fd4_program_emit()
183 pos_regid = regid(0, 0); in fd4_program_emit()
208 (coord_regid == regid(63, 0)) ? regid(63, 0) : (coord_regid + 2); in fd4_program_emit()
323 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd4_program_emit()
327 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd4_program_emit()
/third_party/mesa3d/src/freedreno/computerator/
H A Da6xx.c175 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in cs_program_emit()
176 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in cs_program_emit()
178 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in cs_program_emit()
184 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in cs_program_emit()
185 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in cs_program_emit()
187 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in cs_program_emit()
230 emit_const(struct fd_ringbuffer *ring, uint32_t regid, uint32_t sizedwords, in emit_const() argument
235 assert((regid % 4) == 0); in emit_const()
240 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) | in emit_const()
H A Da4xx.c138 A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(regid(63, 0)) | in cs_program_emit()
140 OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(regid(63, 0)) | in cs_program_emit()
141 A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(regid(63, 0))); in cs_program_emit()
144 OUT_RING(ring, A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(regid(63, 0)) | in cs_program_emit()
148 OUT_RING(ring, A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(regid(63, 0))); in cs_program_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_const.h43 const struct ir3_shader_variant *v, uint32_t regid,
47 const struct ir3_shader_variant *v, uint32_t regid,
52 uint32_t regid, uint32_t offset, uint32_t size, in emit_const_prsc()
56 emit_const_bo(ring, v, regid, offset, size, rsc->bo); in emit_const_prsc()
66 const struct ir3_shader_variant *v, uint32_t regid, in emit_const_asserts()
69 assert((regid % 4) == 0); in emit_const_asserts()
71 assert(regid + sizedwords <= v->constlen * 4); in emit_const_asserts()
490 regid(63, 0);
51 emit_const_prsc(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t offset, uint32_t size, struct pipe_resource *buffer) emit_const_prsc() argument
65 emit_const_asserts(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords) emit_const_asserts() argument
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_emit.c53 /* regid: base const register
59 const struct ir3_shader_variant *v, uint32_t regid, in fd5_emit_const_user()
62 emit_const_asserts(ring, v, regid, sizedwords); in fd5_emit_const_user()
65 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | in fd5_emit_const_user()
78 const struct ir3_shader_variant *v, uint32_t regid, in fd5_emit_const_bo()
81 uint32_t dst_off = regid / 4; in fd5_emit_const_bo()
86 emit_const_asserts(ring, v, regid, sizedwords); in fd5_emit_const_bo()
98 uint32_t regid, uint32_t num, struct fd_bo **bos, in fd5_emit_const_ptrs()
104 assert((regid % 4) == 0); in fd5_emit_const_ptrs()
107 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / in fd5_emit_const_ptrs()
58 fd5_emit_const_user(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords, const uint32_t *dwords) fd5_emit_const_user() argument
77 fd5_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, uint32_t regid, uint32_t offset, uint32_t sizedwords, struct fd_bo *bo) fd5_emit_const_bo() argument
97 fd5_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type, uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets) fd5_emit_const_ptrs() argument
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H A Dfd5_compute.c99 A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) | in cs_program_emit()
100 A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) | in cs_program_emit()
H A Dfd5_program.c234 return regid(63, 0); in next_regid()
460 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd5_program_emit()
464 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd5_program_emit()
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_pipeline.c708 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in tu6_emit_cs_config()
709 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in tu6_emit_cs_config()
711 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in tu6_emit_cs_config()
718 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in tu6_emit_cs_config()
719 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in tu6_emit_cs_config()
721 tu_cs_emit(cs, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in tu6_emit_cs_config()
740 regid(63, 0); in tu6_emit_vs_system_values()
743 regid(63, 0); in tu6_emit_vs_system_values()
746 regid(63, 0); in tu6_emit_vs_system_values()
749 regid(6 in tu6_emit_vs_system_values()
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/third_party/mesa3d/src/freedreno/decode/
H A Dpgmdump2.c277 uint32_t regid; member
287 R(c, regid, 'c'); in decode_shader_constant_block()
/third_party/mesa3d/src/gallium/drivers/r600/sb/
H A Dsb_valtable.cpp367 value* sb_value_pool::create(value_kind k, sel_chan regid, in create() argument
370 value *v = new (np) value(size(), k, regid, ver); in create()
H A Dsb_shader.h409 value* create_value(value_kind k, sel_chan regid, unsigned ver);

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