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Searched refs:reg_count (Results 1 - 25 of 30) sorted by relevance

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/third_party/skia/third_party/externals/spirv-tools/source/opt/
H A Dregister_pressure.cpp217 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
221 live_inout->used_registers_ = reg_count; in EvaluateRegisterRequirements()
232 [live_inout, &die_in_block, &reg_count, this](uint32_t* id) { in EvaluateRegisterRequirements()
241 reg_count++; in EvaluateRegisterRequirements()
246 std::max(live_inout->used_registers_, reg_count); in EvaluateRegisterRequirements()
248 reg_count--; in EvaluateRegisterRequirements()
/third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/
H A Dregister_pressure.cpp217 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
221 live_inout->used_registers_ = reg_count; in EvaluateRegisterRequirements()
232 [live_inout, &die_in_block, &reg_count, this](uint32_t* id) { in EvaluateRegisterRequirements()
241 reg_count++; in EvaluateRegisterRequirements()
246 std::max(live_inout->used_registers_, reg_count); in EvaluateRegisterRequirements()
248 reg_count--; in EvaluateRegisterRequirements()
/third_party/spirv-tools/source/opt/
H A Dregister_pressure.cpp216 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
220 live_inout->used_registers_ = reg_count; in EvaluateRegisterRequirements()
231 [live_inout, &die_in_block, &reg_count, this](uint32_t* id) { in EvaluateRegisterRequirements()
240 reg_count++; in EvaluateRegisterRequirements()
245 std::max(live_inout->used_registers_, reg_count); in EvaluateRegisterRequirements()
247 reg_count--; in EvaluateRegisterRequirements()
/third_party/mesa3d/src/util/
H A Dregister_allocate.c429 unsigned int reg_count = blob_read_uint32(blob); in ra_set_deserialize() local
433 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, reg_count, false); in ra_set_deserialize()
434 assert(regs->count == reg_count); in ra_set_deserialize()
442 for (unsigned int r = 0; r < reg_count; r++) { in ra_set_deserialize()
444 blob_copy_bytes(blob, reg->conflicts, BITSET_WORDS(reg_count) * in ra_set_deserialize()
459 class->regs = ralloc_array(class, BITSET_WORD, BITSET_WORDS(reg_count)); in ra_set_deserialize()
460 blob_copy_bytes(blob, class->regs, BITSET_WORDS(reg_count) * in ra_set_deserialize()
/third_party/node/deps/v8/src/compiler/
H A Dbytecode-graph-builder.cc166 size_t reg_count);
2447 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); in BuildCallVarArgs() local
2451 ? static_cast<int>(reg_count) in BuildCallVarArgs()
2452 : static_cast<int>(reg_count) - 1; in BuildCallVarArgs()
2546 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); in VisitCallWithSpread() local
2548 int arg_count = static_cast<int>(reg_count) - 1; in VisitCallWithSpread()
2579 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); in VisitCallJSRuntime() local
2580 int arg_count = static_cast<int>(reg_count); in VisitCallJSRuntime()
2592 size_t reg_count) { in ProcessCallRuntimeArguments()
2593 int arg_count = static_cast<int>(reg_count); in ProcessCallRuntimeArguments()
2590 ProcessCallRuntimeArguments( const Operator* call_runtime_op, interpreter::Register receiver, size_t reg_count) ProcessCallRuntimeArguments() argument
2610 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitCallRuntime() local
2638 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitCallRuntimeForPair() local
2681 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitConstruct() local
2713 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitConstructWithSpread() local
2746 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitInvokeIntrinsic() local
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H A Dbytecode-analysis.cc119 uint32_t reg_count = iterator.GetRegisterCountOperand(i + 1); in UpdateInLivenessForOutOperand() local
121 for (uint32_t j = 0; j < reg_count; ++j) { in UpdateInLivenessForOutOperand()
177 uint32_t reg_count = iterator.GetRegisterCountOperand(i + 1); in UpdateInLivenessForInOperand() local
179 for (uint32_t j = 0; j < reg_count; ++j) { in UpdateInLivenessForInOperand()
438 uint32_t reg_count = iterator.GetRegisterCountOperand(i); in UpdateAssignments() local
439 assignments->AddList(r, reg_count); in UpdateAssignments()
/third_party/node/deps/v8/src/interpreter/
H A Dinterpreter-assembler.cc264 TNode<Uint32T> reg_count = BytecodeOperandCount(operand_index + 1); in GetRegisterListAtOperandIndex() local
265 return RegListNodePair(base_reg, reg_count); in GetRegisterListAtOperandIndex()
277 Uint32GreaterThan(reg_list.reg_count(), Int32Constant(index))); in RegisterLocationInRegisterList()
715 TNode<Word32T> args_count = args.reg_count(); in CallJSAndDispatch()
791 TNode<Word32T> args_count = args.reg_count(); in CallJSWithSpreadAndDispatch()
810 TNode<Word32T> args_count = JSParameterCount(args.reg_count()); in Construct()
961 TNode<Word32T> args_count = JSParameterCount(args.reg_count()); in ConstructWithSpread()
987 args.reg_count(), args.base_reg_location(), in CallRuntimeN()
1440 TNode<UintPtrT> register_count = ChangeUint32ToWord(registers.reg_count()); in ExportParametersAndRegisterFile()
1512 TNode<UintPtrT> register_count = ChangeUint32ToWord(registers.reg_count()); in ImportRegisterFile()
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H A Dinterpreter-assembler.h88 RegListNodePair(TNode<IntPtrT> base_reg_location, TNode<Word32T> reg_count) in RegListNodePair() argument
89 : base_reg_location_(base_reg_location), reg_count_(reg_count) {} in RegListNodePair()
91 TNode<Word32T> reg_count() const { return reg_count_; } in reg_count() function in v8::internal::interpreter::InterpreterAssembler::RegListNodePair
H A Dinterpreter-intrinsics-generator.cc91 AbortIfArgCountMismatch(expected_arg_count, args.reg_count()); \ in InvokeIntrinsic()
151 __ ChangeInt32ToIntPtr(args.reg_count()), __ IntPtrConstant(1)); in CopyDataPropertiesWithExcludedPropertiesOnStack()
/third_party/vixl/test/aarch64/
H A Dtest-utils-aarch64.cc493 int reg_count, in PopulateRegisterArray()
497 for (unsigned n = 0; (n < kNumberOfRegisters) && (i < reg_count); n++) { in PopulateRegisterArray()
514 VIXL_ASSERT(CountSetBits(list, kNumberOfRegisters) == reg_count); in PopulateRegisterArray()
524 int reg_count, in PopulateVRegisterArray()
528 for (unsigned n = 0; (n < kNumberOfVRegisters) && (i < reg_count); n++) { in PopulateVRegisterArray()
545 VIXL_ASSERT(CountSetBits(list, kNumberOfVRegisters) == reg_count); in PopulateVRegisterArray()
489 PopulateRegisterArray(Register* w, Register* x, Register* r, int reg_size, int reg_count, RegList allowed) PopulateRegisterArray() argument
520 PopulateVRegisterArray(VRegister* s, VRegister* d, VRegister* v, int reg_size, int reg_count, RegList allowed) PopulateVRegisterArray() argument
H A Dtest-utils-aarch64.h493 int reg_count,
501 int reg_count,
H A Dtest-assembler-sve-aarch64.cc7340 int reg_count = 2;
7346 MemoryWrite(middle, 0, (i * reg_count) + 0, lane0);
7347 MemoryWrite(middle, 0, (i * reg_count) + 1, lane1);
7356 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
7357 MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
7366 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
7367 MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
7376 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
7377 MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
7510 int reg_count
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H A Dtest-assembler-aarch64.cc8374 // supports (where a reg_count argument would otherwise be provided).
8379 // * Push <reg_count> registers with size <reg_size>.
8381 // * Pop <reg_count> registers to restore the original contents.
8386 static void PushPopSimpleHelper(int reg_count,
8398 if (reg_count == kPushPopUseMaxRegCount) {
8399 reg_count = CountSetBits(allowed, kNumberOfRegisters);
8405 PopulateRegisterArray(NULL, x, r, reg_size, reg_count, allowed);
8426 for (i = 0; i < reg_count; i++) {
8438 for (i = reg_count; i >= 4; i -= 4) {
8468 for (i = 0; i <= (reg_count
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/third_party/backends/backend/
H A Drts8891_low.h220 SANE_Int reg_count; member
H A Drts8891.c2535 device->reg_count = 244; in attach_rts8891()
3005 rts8891_write_all (dev->devnum, dev->regs, dev->reg_count); in init_lamp()
3196 rts8891_simple_scan (dev->devnum, dev->regs, dev->reg_count, 0x03, in find_origin()
3311 rts8891_write_all (dev->devnum, dev->regs, dev->reg_count); in find_origin()
3469 rts8891_simple_scan (dev->devnum, dev->regs, dev->reg_count, 0x0c, in find_margin()
3688 status = rts8891_write_all (dev->devnum, dev->regs, dev->reg_count); in initialize_device()
3946 for (i = 0; i < dev->reg_count; i++) in init_registers()
4138 sanei_rts88xx_read_regs (dev->devnum, 0, dev->regs, dev->reg_count); in init_device()
4142 for (i = 0; i < dev->reg_count; i++) in init_device()
4170 rts8891_write_all (dev->devnum, dev->regs, dev->reg_count); in init_device()
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/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc1541 int reg_count, in Simulator()
1549 for (int r = 0; r < reg_count; r++) { in Simulator()
1561 int reg_count, in Simulator()
1576 for (int r = 0; r < reg_count; r++) { in Simulator()
1852 int reg_count, in Simulator()
1865 PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format); in Simulator()
1874 reg_count, in Simulator()
1877 address + (i * reg_count)); in Simulator()
1882 int reg_count, in Simulator()
1896 PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mas in Simulator()
1540 PrintVRegistersForStructuredAccess(int rt_code, int reg_count, uint16_t focus_mask, PrintRegisterFormat format) Simulator() argument
1559 PrintZRegistersForStructuredAccess(int rt_code, int q_index, int reg_count, uint16_t focus_mask, PrintRegisterFormat format) Simulator() argument
1851 PrintVStructAccess(int rt_code, int reg_count, PrintRegisterFormat format, const char* op, uintptr_t address) Simulator() argument
1881 PrintVSingleStructAccess(int rt_code, int reg_count, int lane, PrintRegisterFormat format, const char* op, uintptr_t address) Simulator() argument
1900 PrintVReplicatingStructAccess(int rt_code, int reg_count, PrintRegisterFormat format, const char* op, uintptr_t address) Simulator() argument
1943 PrintZStructAccess(int rt_code, int reg_count, const LogicPRegister& pg, PrintRegisterFormat format, int msize_in_bytes, const char* op, const LogicSVEAddressVector& addr) Simulator() argument
8235 int reg_count = 1; Simulator() local
8506 int reg_count = 0; Simulator() local
12537 int reg_count = instr->ExtractBits(22, 21) + 1; Simulator() local
12973 int reg_count = instr->ExtractBits(22, 21) + 1; Simulator() local
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H A Dsimulator-aarch64.h1072 void SetRegCount(int reg_count) { in SetRegCount() argument
1073 VIXL_ASSERT(reg_count >= 1); // E.g. ld1/st1 in SetRegCount()
1074 VIXL_ASSERT(reg_count <= 4); // E.g. ld4/st4 in SetRegCount()
1075 reg_count_ = reg_count; in SetRegCount()
2587 int reg_count,
2593 int reg_count,
2600 int reg_count,
2607 int reg_count,
2621 int reg_count,
2628 int reg_count,
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H A Dlogic-aarch64.cc7248 int reg_count = addr.GetRegCount();
7251 VIXL_ASSERT((reg_count >= 1) && (reg_count <= 4));
7275 for (int r = 0; r < reg_count; r++) {
7292 reg_count,
7309 int reg_count = addr.GetRegCount();
7313 VIXL_ASSERT((reg_count >= 1) && (reg_count <= 4));
7327 for (int r = 0; r < reg_count; r++) {
7350 reg_count,
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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3.c257 unsigned reg_count, bool double_threadsize) in ir3_get_reg_dependent_max_waves()
259 return reg_count ? (compiler->reg_size_vec4 / in ir3_get_reg_dependent_max_waves()
260 (reg_count * (double_threadsize ? 2 : 1)) * in ir3_get_reg_dependent_max_waves()
256 ir3_get_reg_dependent_max_waves(const struct ir3_compiler *compiler, unsigned reg_count, bool double_threadsize) ir3_get_reg_dependent_max_waves() argument
H A Dir3_ra.c2326 unsigned reg_count = DIV_ROUND_UP(pressure, 2 * 4); in calc_target_full_pressure() local
2328 bool double_threadsize = ir3_should_double_threadsize(v, reg_count); in calc_target_full_pressure()
2330 unsigned target = reg_count; in calc_target_full_pressure()
2334 v->compiler, reg_count, double_threadsize); in calc_target_full_pressure()
/third_party/node/deps/v8/src/maglev/
H A Dmaglev-graph-builder.cc643 int reg_count = argc_count_with_recv; in BuildCallFromRegisters() local
645 reg_count = argc_count; in BuildCallFromRegisters()
648 for (int i = 0; i < reg_count; i++) { in BuildCallFromRegisters()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs.cpp2139 int reg_count = 0;
2142 vgrf_to_reg[i] = reg_count;
2143 reg_count += alloc.sizes[i];
2152 bool *split_points = new bool[reg_count];
2153 memset(split_points, 0, reg_count * sizeof(*split_points));
2202 int *new_virtual_grf = new int[reg_count];
2203 int *new_reg_offset = new int[reg_count];
2241 assert(reg == reg_count);
4565 unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE);
4568 reg_count
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/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dir2_private.h179 unsigned reg_count; member
H A Dir2_nir.c357 reg = share_reg ? share_reg->reg : &ctx->reg[ctx->reg_count++]; in instr_create_alu_reg()
1171 ctx->reg_count = MAX2(ctx->reg_count, reg->index + 1); in ir2_nir_compile()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dregister-arm64.h331 int reg_count = IsVectorFormat(format) ? LaneCountFromFormat(format) : 1; in Create() local
332 return VRegister::Create(reg_code, reg_size, reg_count); in Create()

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