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Searched refs:reg1 (Results 1 - 25 of 93) sorted by relevance

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/third_party/ffmpeg/libavcodec/loongarch/
H A Dvp9_intra_lsx.c435 __m128i tmp0, tmp1, tmp2, tmp3, reg0, reg1; in ff_tm_4x4_lsx() local
440 reg1 = __lsx_vld(src_top_ptr, 0); in ff_tm_4x4_lsx()
443 DUP4_ARG2(__lsx_vilvl_b, tmp0, reg1, tmp1, reg1, tmp2, reg1, tmp3, reg1, in ff_tm_4x4_lsx()
467 __m128i reg0, reg1; in ff_tm_8x8_lsx() local
470 reg1 = __lsx_vld(src_top_ptr, 0); in ff_tm_8x8_lsx()
475 DUP4_ARG2(__lsx_vilvl_b, tmp0, reg1, tmp1, reg1, tmp in ff_tm_8x8_lsx()
517 __m128i reg0, reg1; ff_tm_16x16_lsx() local
600 __m128i tmp0, tmp1, tmp2, tmp3, reg0, reg1, reg2; ff_tm_32x32_lsx() local
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H A Dvp9_idct_lsx.c68 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \
76 s1_m = __lsx_vilvl_h(__lsx_vneg_h(reg1), reg0); \
77 s0_m = __lsx_vilvh_h(__lsx_vneg_h(reg1), reg0); \
78 s3_m = __lsx_vilvl_h(reg0, reg1); \
79 s2_m = __lsx_vilvh_h(reg0, reg1); \
377 __m128i reg1, reg3, reg5, reg7, reg9, reg11, reg13, reg15; in vp9_idct16_1d_columns_addblk_lsx() local
383 reg0, reg1, reg2, reg3); in vp9_idct16_1d_columns_addblk_lsx()
426 VP9_DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); in vp9_idct16_1d_columns_addblk_lsx()
429 reg9 = __lsx_vsub_h(reg1, loc in vp9_idct16_1d_columns_addblk_lsx()
501 __m128i reg1, reg3, reg5, reg7, reg9, reg11, reg13, reg15; vp9_idct16_1d_columns_lsx() local
883 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
956 VP9_DOTP_CONST_PAIR(__lsx_vneg_h(reg6), reg1, cospi_24_64, cospi_8_64, vp9_idct8x32_column_even_process_store() local
957 reg6, reg1); vp9_idct8x32_column_even_process_store() local
998 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
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H A Dh264_intrapred_lasx.c30 __m256i reg0, reg1, reg2, reg3, reg4; \
49 reg1 = __lasx_xvldx(src, (8 - stride)); \
50 reg0 = __lasx_xvilvl_d(reg1, reg0); \
72 reg1 = __lasx_xvreplgr2vr_w(res1); \
82 reg2 = __lasx_xvadd_w(reg2, reg1); \
88 reg2 = __lasx_xvadd_w(reg2, reg1); \
H A Dvp9_mc_lsx.c457 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_4w_lsx() local
474 DUP2_ARG2(__lsx_vilvl_d, tmp3, tmp0, tmp4, tmp1, reg0, reg1); in common_vt_8t_4w_lsx()
476 DUP2_ARG2(__lsx_vxori_b, reg0, 128, reg1, 128, reg0, reg1); in common_vt_8t_4w_lsx()
488 out0 = FILT_8TAP_DPADD_S_H(reg0, reg1, reg2, reg3, filter0, filter1, in common_vt_8t_4w_lsx()
490 out1 = FILT_8TAP_DPADD_S_H(reg1, reg2, reg3, reg4, filter0, filter1, in common_vt_8t_4w_lsx()
504 reg1 = reg3; in common_vt_8t_4w_lsx()
517 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
541 reg0, reg1, reg2, reg3); in common_vt_8t_8w_lsx()
553 out0 = FILT_8TAP_DPADD_S_H(reg0, reg1, reg in common_vt_8t_8w_lsx()
589 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_lsx() local
683 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_mult_lsx() local
1543 __m128i reg0, reg1, reg2, reg3, reg4; common_vt_8t_and_aver_dst_4w_lsx() local
1619 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_8w_lsx() local
1705 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_16w_mult_lsx() local
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H A Dhevc_mc_bi_lsx.c64 __m128i reg0, reg1, reg2, reg3; in hevc_bi_copy_4w_lsx() local
69 reg1 = __lsx_vldrepl_w(src0_ptr + src_stride, 0); in hevc_bi_copy_4w_lsx()
73 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1); in hevc_bi_copy_4w_lsx()
76 reg1 = __lsx_vldrepl_w(src0_ptr + src_stride, 0); in hevc_bi_copy_4w_lsx()
79 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1); in hevc_bi_copy_4w_lsx()
113 reg1 = __lsx_vldrepl_w(src0_ptr + src_stride, 0); in hevc_bi_copy_4w_lsx()
116 src0 = __lsx_vilvl_w(reg1, reg0); in hevc_bi_copy_4w_lsx()
150 __m128i reg0, reg1, reg2, reg3; in hevc_bi_copy_6w_lsx() local
154 reg1 = __lsx_vldrepl_d(src0_ptr + src_stride, 0); in hevc_bi_copy_6w_lsx()
157 DUP2_ARG2(__lsx_vilvl_d, reg1, reg in hevc_bi_copy_6w_lsx()
246 __m128i reg0, reg1, reg2, reg3; hevc_bi_copy_8w_lsx() local
1507 __m128i reg0, reg1, reg2, reg3; hevc_hv_4t_6w_lsx() local
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/third_party/vixl/src/aarch64/
H A Dregisters-aarch64.h973 bool AreAliased(const CPURegister& reg1,
989 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1027 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
1029 bool AreSameSizeAndType(const CPURegister& reg1,
1037 VIXL_ASSERT(reg1.IsValid());
1039 match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
1040 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
1041 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
1042 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
1043 match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
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/third_party/node/deps/openssl/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
490 reg1 = GET_U32_BE(in, 1); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
516 reg1 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
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/third_party/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
490 reg1 = GET_U32_BE(in, 1); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
516 reg1 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/tests/
H A Dsfn_value_test.cpp100 UniformValue reg1(513, 2, 1); in TEST_F()
102 EXPECT_EQ(reg1.sel(), 513); in TEST_F()
103 EXPECT_EQ(reg1.chan(), 2); in TEST_F()
104 EXPECT_EQ(reg1.kcache_bank(), 1); in TEST_F()
105 EXPECT_FALSE(reg1.buf_addr()); in TEST_F()
106 EXPECT_FALSE(reg1.is_virtual()); in TEST_F()
/third_party/node/deps/openssl/openssl/crypto/perlasm/
H A Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
H A Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
H A Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
68 $ret .= "+$reg1" if ($reg1 ne "");
71 { $ret .= "$reg1"; }
/third_party/openssl/crypto/perlasm/
H A Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
H A Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
H A Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
68 $ret .= "+$reg1" if ($reg1 ne "");
71 { $ret .= "$reg1"; }
/third_party/ffmpeg/libavcodec/mips/
H A Dvp9_idct_msa.c67 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \
75 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
76 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
968 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
999 VP9_DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); in vp9_idct16_1d_columns_addblk_msa()
1002 reg9 = reg1 - loc2; in vp9_idct16_1d_columns_addblk_msa()
1003 reg1 = reg1 in vp9_idct16_1d_columns_addblk_msa()
1071 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; vp9_idct16_1d_columns_msa() local
1634 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
1718 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
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/third_party/ffmpeg/libavutil/mips/
H A Dmmiutils.h130 #define MMI_LQ(reg1, reg2, addr, bias) \
131 "ld "#reg1", "#bias"("#addr") \n\t" \
134 #define MMI_SQ(reg1, reg2, addr, bias) \
135 "sd "#reg1", "#bias"("#addr") \n\t" \
216 #define MMI_LQ(reg1, reg2, addr, bias) \
217 "gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
219 #define MMI_SQ(reg1, reg2, addr, bias) \
220 "gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
/third_party/ffmpeg/libavcodec/aarch64/
H A Dvp9mc_16bpp_neon.S325 // Round, shift and saturate and store reg1-reg4
326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
327 sqrshrun \reg1\().4h, \reg1\().4s, #7
337 umin \reg1\().4h, \reg1\().4h, \minreg\().4h
342 urhadd \reg1\().4h, \reg1\().4h, \tmp1\().4h
347 st1 {\reg1\().4h}, [x0], x1
353 // Round, shift and saturate and store reg1
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H A Dvp9mc_neon.S388 // Round, shift and saturate and store reg1-reg2 over 4 lines
389 .macro do_store4 reg1, reg2, tmp1, tmp2, type
390 sqrshrun \reg1\().8b, \reg1\().8h, #7
397 urhadd \reg1\().8b, \reg1\().8b, \tmp1\().8b
400 st1 {\reg1\().s}[0], [x0], x1
402 st1 {\reg1\().s}[1], [x0], x1
406 // Round, shift and saturate and store reg1-4
407 .macro do_store reg1, reg
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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs_bank_conflicts.cpp416 for (unsigned reg1 = reg + 1; reg1 <= max_reg; reg1++) {
417 if (offsets[atoms[reg1]] < reg + n) {
418 atoms[reg1] = r;
420 if (offsets[atoms[reg1 - 1]] != offsets[atoms[reg1]])
423 offsets[r] = offsets[atoms[reg1]];
424 atoms[reg1] = r;
/third_party/ffmpeg/tests/checkasm/aarch64/
H A Dcheckasm.S151 .macro check_reg_neon reg1, reg2
153 uzp1 v2.2d, v\reg1\().2d, v\reg2\().2d
164 .macro check_reg reg1, reg2
166 eor x0, x0, \reg1
/third_party/mesa3d/src/panfrost/bifrost/
H A Ddisassemble.c59 return regs.reg0 | ((regs.reg1 & 0x1) << 5); in get_reg0()
61 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0; in get_reg0()
66 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1; in get_reg1()
141 ctrl = regs.reg1 >> 2; in DecodeRegCtrl()
142 decoded.read_reg0 = !(regs.reg1 & 0x2); in DecodeRegCtrl()
/third_party/backends/backend/
H A Dsm3840_lib.h84 static void write_regs (p_usb_dev_handle udev, int regs, int reg1, int val1,
124 static void write_regs (p_usb_dev_handle udev, int regs, int reg1, int val1,
/third_party/node/deps/v8/src/interpreter/
H A Dbytecode-register.cc105 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous() argument
107 if (reg1.index() + 1 != reg2.index()) { in AreContiguous()
/third_party/mesa3d/src/freedreno/decode/
H A Dcrashdec-mempool.c57 uint32_t reg1 : 18; in dump_mem_pool_chunk() member
73 dump_mem_pool_reg_write(fields.reg1, fields.data1, fields.reg1_context, in dump_mem_pool_chunk()

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