Lines Matching refs:reg1

973 bool AreAliased(const CPURegister& reg1,
989 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1027 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
1029 bool AreSameSizeAndType(const CPURegister& reg1,
1037 VIXL_ASSERT(reg1.IsValid());
1039 match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
1040 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
1041 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
1042 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
1043 match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
1044 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);
1045 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1);
1051 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
1053 bool AreEven(const CPURegister& reg1,
1061 VIXL_ASSERT(reg1.IsValid());
1062 bool even = (reg1.GetCode() % 2) == 0;
1075 // any subsequent arguments. At least one argument (reg1) must be valid
1078 bool AreConsecutive(const CPURegister& reg1,
1082 VIXL_ASSERT(reg1.IsValid());
1087 ((reg1.GetCode() + 1) % (reg1.GetMaxCode() + 1))) {
1094 ((reg2.GetCode() + 1) % (reg1.GetMaxCode() + 1))) {
1101 ((reg3.GetCode() + 1) % (reg1.GetMaxCode() + 1))) {
1110 // arguments. At least one argument (reg1) must be valid (not NoVReg).
1112 bool AreSameFormat(const CPURegister& reg1,
1116 VIXL_ASSERT(reg1.IsValid());
1118 match &= !reg2.IsValid() || reg2.IsSameFormat(reg1);
1119 match &= !reg3.IsValid() || reg3.IsSameFormat(reg1);
1120 match &= !reg4.IsValid() || reg4.IsSameFormat(reg1);
1127 // At least one argument (reg1) must be valid (not NoVReg).
1130 bool AreSameLaneSize(const CPURegister& reg1,
1134 VIXL_ASSERT(reg1.IsValid());
1137 !reg2.IsValid() || (reg2.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());
1139 !reg3.IsValid() || (reg3.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());
1141 !reg4.IsValid() || (reg4.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());