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Searched refs:num_patches (Results 1 - 12 of 12) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_shader.h669 unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4; in get_tcs_num_patches() local
684 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size)); in get_tcs_num_patches()
687 num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size); in get_tcs_num_patches()
691 num_patches = MIN2(num_patches, 40); in get_tcs_num_patches()
696 num_patches = MIN2(num_patches, one_wave); in get_tcs_num_patches()
698 return num_patches; in get_tcs_num_patches()
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H A Dradv_nir_lower_abi.c200 unsigned num_patches = s->info->num_tess_patches; in lower_abi_instr() local
205 return nir_imm_int(b, num_patches * per_vertex_output_patch_size); in lower_abi_instr()
H A Dradv_pipeline.c3809 unsigned num_patches = get_tcs_num_patches( in gather_tess_info() local
3820 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs, num_patches, in gather_tess_info()
3824 stages[MESA_SHADER_TESS_CTRL].info.num_tess_patches = num_patches; in gather_tess_info()
3833 stages[MESA_SHADER_TESS_EVAL].info.num_tess_patches = num_patches; in gather_tess_info()
3834 stages[MESA_SHADER_GEOMETRY].info.num_tess_patches = num_patches; in gather_tess_info()
3835 stages[MESA_SHADER_VERTEX].info.num_tess_patches = num_patches; in gather_tess_info()
3871 ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level, s, num_patches, in gather_tess_info()
6021 unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches; in radv_pipeline_emit_tess_state() local
6027 num_patches = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches; in radv_pipeline_emit_tess_state()
6029 ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | S_028B58_HS_NUM_INPUT_C in radv_pipeline_emit_tess_state()
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp622 static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_patches)
644 *num_patches = sctx->last_num_patches;
695 *num_patches = 256 / max_verts_per_patch;
701 *num_patches = MIN2(*num_patches, 64); /* e.g. 64 triangles in exactly 3 waves */
707 *num_patches = MIN2(*num_patches, 16); /* recommended */
710 *num_patches =
711 MIN2(*num_patches, (sctx->screen->hs.tess_offchip_block_dw_size * 4) / output_patch_size);
721 *num_patches
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H A Dsi_shader_llvm_tess.c154 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices; in get_tcs_tes_buffer_address() local
158 num_patches = si_unpack_param(ctx, ctx->tcs_offchip_layout, 0, 6); in get_tcs_tes_buffer_address()
159 num_patches = LLVMBuildAdd(ctx->ac.builder, num_patches, ctx->ac.i32_1, ""); in get_tcs_tes_buffer_address()
160 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch, num_patches, ""); in get_tcs_tes_buffer_address()
168 param_stride = num_patches; in get_tcs_tes_buffer_address()
/third_party/ffmpeg/libavcodec/
H A Daacsbr_template.c144 for (k = 1; k <= sbr->num_patches; k++)
149 if (sbr->num_patches > 1)
151 (sbr->num_patches - 1) * sizeof(patch_borders[0]));
153 AV_QSORT(sbr->f_tablelim, sbr->num_patches + sbr->n[0],
157 sbr->n_lim = sbr->n[0] + sbr->num_patches - 1;
166 !in_table_int16(patch_borders, sbr->num_patches, *in)) {
169 } else if (!in_table_int16(patch_borders, sbr->num_patches, *out)) {
490 sbr->num_patches = 0;
514 if (sbr->num_patches > 5) {
515 av_log(ac->avctx, AV_LOG_ERROR, "Too many patches: %d\n", sbr->num_patches);
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H A Dsbr.h187 AAC_SIGNE num_patches; member
/third_party/mesa3d/src/gallium/auxiliary/draw/
H A Ddraw_tess.c169 unsigned num_patches = input_prim->count / shader->draw->pt.vertices_per_patch; in draw_tess_ctrl_shader_run() local
189 shader->draw->statistics.hs_invocations += num_patches; in draw_tess_ctrl_shader_run()
192 for (unsigned i = 0; i < num_patches; i++) { in draw_tess_ctrl_shader_run()
211 output_prims->primitive_count = num_patches; in draw_tess_ctrl_shader_run()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_gmem.c259 unsigned num_patches = fd_patch_num_elements(&batch->fb_read_patches); in patch_fb_read_gmem() local
260 if (!num_patches) in patch_fb_read_gmem()
285 for (unsigned i = 0; i < num_patches; i++) { in patch_fb_read_gmem()
300 unsigned num_patches = fd_patch_num_elements(&batch->fb_read_patches); in patch_fb_read_sysmem() local
301 if (!num_patches) in patch_fb_read_sysmem()
335 for (unsigned i = 0; i < num_patches; i++) { in patch_fb_read_sysmem()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_pipe.h807 unsigned *num_patches);
810 unsigned num_patches);
H A Devergreen_state.c4525 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches) in evergreen_setup_tess_constants() argument
4543 *num_patches = 1; in evergreen_setup_tess_constants()
4583 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0; in evergreen_setup_tess_constants()
4586 lds_size = output_patch0_offset + output_patch_size * *num_patches; in evergreen_setup_tess_constants()
4600 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor); in evergreen_setup_tess_constants()
4621 unsigned num_patches) in evergreen_get_ls_hs_config()
4632 return S_028B58_NUM_PATCHES(num_patches) | in evergreen_get_ls_hs_config()
4619 evergreen_get_ls_hs_config(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned num_patches) evergreen_get_ls_hs_config() argument
H A Dr600_state_common.c2169 unsigned num_patches, dirty_tex_counter, index_offset = 0; in r600_draw_vbo() local
2329 evergreen_setup_tess_constants(rctx, info, &num_patches); in r600_draw_vbo()
2369 num_patches); in r600_draw_vbo()

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