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Searched refs:laneidx (Results 1 - 25 of 39) sorted by relevance

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/third_party/node/deps/v8/src/compiler/
H A Dmachine-operator.cc138 return base::hash_combine(params.kind, params.rep, params.laneidx); in hash_value()
142 return os << "(" << params.kind << " " << params.rep << " " << params.laneidx in operator <<()
153 lhs.laneidx == rhs.laneidx; in operator ==()
189 return base::hash_combine(params.kind, params.rep, params.laneidx); in hash_value()
194 << static_cast<unsigned int>(params.laneidx) << ")"; in operator <<()
204 lhs.laneidx == rhs.laneidx; in operator ==()
1486 uint8_t laneidx) { in LoadLane()
1489 laneidx in LoadLane()
1484 LoadLane(MemoryAccessKind kind, LoadRepresentation rep, uint8_t laneidx) LoadLane() argument
1523 StoreLane(MemoryAccessKind kind, MachineRepresentation rep, uint8_t laneidx) StoreLane() argument
[all...]
H A Dmachine-operator.h129 uint8_t laneidx; member
211 uint8_t laneidx; member
941 uint8_t laneidx);
949 uint8_t laneidx);
H A Dwasm-compiler.h406 uint8_t laneidx, wasm::WasmCodePosition position);
411 uint32_t alignment, Node* val, uint8_t laneidx,
/third_party/node/deps/v8/src/codegen/shared-ia32-x64/
H A Dmacro-assembler-shared-ia32-x64.cc355 uint8_t laneidx) { in S128Store32Lane()
357 if (laneidx == 0) { in S128Store32Lane()
360 DCHECK_GE(3, laneidx); in S128Store32Lane()
361 Extractps(dst, src, laneidx); in S128Store32Lane()
1202 uint8_t laneidx) { in S128Store64Lane()
1204 if (laneidx == 0) { in S128Store64Lane()
1207 DCHECK_EQ(1, laneidx); in S128Store64Lane()
354 S128Store32Lane(Operand dst, XMMRegister src, uint8_t laneidx) S128Store32Lane() argument
1201 S128Store64Lane(Operand dst, XMMRegister src, uint8_t laneidx) S128Store64Lane() argument
H A Dmacro-assembler-shared-ia32-x64.h415 void S128Store32Lane(Operand dst, XMMRegister src, uint8_t laneidx);
477 void S128Store64Lane(Operand dst, XMMRegister src, uint8_t laneidx);
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h1445 uint8_t laneidx; member in v8::internal::LoadStoreLaneParams
1449 // laneidx and load/store size, whether the low or high D reg is accessed, and
1451 LoadStoreLaneParams(MachineRepresentation rep, uint8_t laneidx);
1454 LoadStoreLaneParams(uint8_t laneidx, NeonSize sz, int lanes) in LoadStoreLaneParams() argument
1455 : low_op(laneidx < lanes), sz(sz), laneidx(laneidx % lanes) {} in LoadStoreLaneParams()
H A Dassembler-arm.cc5517 uint8_t laneidx) { in LoadStoreLaneParams()
5519 *this = LoadStoreLaneParams(laneidx, Neon8, 8); in LoadStoreLaneParams()
5521 *this = LoadStoreLaneParams(laneidx, Neon16, 4); in LoadStoreLaneParams()
5523 *this = LoadStoreLaneParams(laneidx, Neon32, 2); in LoadStoreLaneParams()
5525 *this = LoadStoreLaneParams(laneidx, Neon64, 1); in LoadStoreLaneParams()
5516 LoadStoreLaneParams(MachineRepresentation rep, uint8_t laneidx) LoadStoreLaneParams() argument
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dassembler-riscv64.h1817 uint8_t laneidx; member in v8::internal::Assembler::LoadStoreLaneParams
1819 LoadStoreLaneParams(MachineRepresentation rep, uint8_t laneidx);
1822 LoadStoreLaneParams(uint8_t laneidx, int sz, int lanes) in LoadStoreLaneParams() argument
1823 : sz(sz), laneidx(laneidx % lanes) {} in LoadStoreLaneParams()
H A Dmacro-assembler-riscv64.cc3990 void TurboAssembler::LoadLane(int ts, VRegister dst, uint8_t laneidx, in LoadLane() argument
3995 li(kScratchReg, 0x1 << laneidx); in LoadLane()
4002 li(kScratchReg, 0x1 << laneidx); in LoadLane()
4008 li(kScratchReg, 0x1 << laneidx); in LoadLane()
4014 li(kScratchReg, 0x1 << laneidx); in LoadLane()
4022 void TurboAssembler::StoreLane(int sz, VRegister src, uint8_t laneidx, in StoreLane() argument
4026 vslidedown_vi(kSimd128ScratchReg, src, laneidx); in StoreLane()
4031 vslidedown_vi(kSimd128ScratchReg, src, laneidx); in StoreLane()
4036 vslidedown_vi(kSimd128ScratchReg, src, laneidx); in StoreLane()
4042 vslidedown_vi(kSimd128ScratchReg, src, laneidx); in StoreLane()
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H A Dmacro-assembler-riscv64.h982 void LoadLane(int sz, VRegister dst, uint8_t laneidx, MemOperand src);
983 void StoreLane(int sz, VRegister src, uint8_t laneidx, MemOperand dst);
/third_party/node/deps/v8/src/codegen/mips64/
H A Dmacro-assembler-mips64.cc2614 void TurboAssembler::LoadLane(MSASize sz, MSARegister dst, uint8_t laneidx, in CallRecordWriteStub()
2621 insert_b(dst, laneidx, scratch); in CallRecordWriteStub()
2625 insert_h(dst, laneidx, scratch); in CallRecordWriteStub()
2629 insert_w(dst, laneidx, scratch); in CallRecordWriteStub()
2633 insert_d(dst, laneidx, scratch); in CallRecordWriteStub()
2640 void TurboAssembler::StoreLane(MSASize sz, MSARegister src, uint8_t laneidx, in CallRecordWriteStub()
2646 copy_u_b(scratch, src, laneidx); in CallRecordWriteStub()
2650 copy_u_h(scratch, src, laneidx); in CallRecordWriteStub()
2654 if (laneidx == 0) { in CallRecordWriteStub()
2658 copy_u_w(scratch, src, laneidx); in CallRecordWriteStub()
[all...]
H A Dassembler-mips64.h1956 uint8_t laneidx; member in v8::internal::Assembler::OffsetAccessType::LoadStoreLaneParams
1958 LoadStoreLaneParams(MachineRepresentation rep, uint8_t laneidx);
1961 LoadStoreLaneParams(uint8_t laneidx, MSASize sz, int lanes) in LoadStoreLaneParams() argument
1962 : sz(sz), laneidx(laneidx % lanes) {} in LoadStoreLaneParams()
H A Dmacro-assembler-mips64.h842 void LoadLane(MSASize sz, MSARegister dst, uint8_t laneidx, MemOperand src);
843 void StoreLane(MSASize sz, MSARegister src, uint8_t laneidx, MemOperand dst);
H A Dassembler-mips64.cc4002 uint8_t laneidx) { in LoadStoreLaneParams()
4005 *this = LoadStoreLaneParams(laneidx, MSA_B, 16); in LoadStoreLaneParams()
4008 *this = LoadStoreLaneParams(laneidx, MSA_H, 8); in LoadStoreLaneParams()
4011 *this = LoadStoreLaneParams(laneidx, MSA_W, 4); in LoadStoreLaneParams()
4014 *this = LoadStoreLaneParams(laneidx, MSA_D, 2); in LoadStoreLaneParams()
4001 LoadStoreLaneParams(MachineRepresentation rep, uint8_t laneidx) LoadStoreLaneParams() argument
/third_party/node/deps/v8/src/wasm/
H A Dgraph-builder-interface.cc609 const uint8_t laneidx, Value* result) { in LoadLane()
612 imm.alignment, laneidx, decoder->position()); in LoadLane()
624 const Value& value, const uint8_t laneidx) { in StoreLane()
626 value.node, laneidx, decoder->position(), in StoreLane()
/third_party/node/deps/v8/src/wasm/baseline/arm64/
H A Dliftoff-assembler-arm64.h1726 uint8_t laneidx, uint32_t* protected_load_pc) { in LoadLane()
1738 ld1(dst.fp().B(), laneidx, src_op); in LoadLane()
1740 ld1(dst.fp().H(), laneidx, src_op); in LoadLane()
1742 ld1(dst.fp().S(), laneidx, src_op); in LoadLane()
1744 ld1(dst.fp().D(), laneidx, src_op); in LoadLane()
1723 LoadLane(LiftoffRegister dst, LiftoffRegister src, Register addr, Register offset_reg, uintptr_t offset_imm, LoadType type, uint8_t laneidx, uint32_t* protected_load_pc) LoadLane() argument
/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dcode-generator-ia32.cc543 int8_t laneidx = i.InputInt8(1); \
547 __ v##OPCODE(dst, src, i.MemoryOperand(2), laneidx); \
551 __ OPCODE(dst, i.MemoryOperand(2), laneidx); \
556 __ v##OPCODE(dst, src, i.InputOperand(2), laneidx); \
560 __ OPCODE(dst, i.InputOperand(2), laneidx); \
2757 uint8_t laneidx = i.InputUint8(index + 1); in AssembleArchInstruction() local
2758 __ S128Store32Lane(operand, i.InputSimd128Register(index), laneidx); in AssembleArchInstruction()
H A Dinstruction-selector-ia32.cc495 if (params.laneidx == 0) { in VisitLoadLane()
498 DCHECK_EQ(1, params.laneidx); in VisitLoadLane()
515 inputs[input_count++] = g.UseImmediate(params.laneidx); in VisitLoadLane()
770 if (params.laneidx == 0) { in VisitStoreLane()
773 DCHECK_EQ(1, params.laneidx); in VisitStoreLane()
788 inputs[input_count++] = g.UseImmediate(params.laneidx); in VisitStoreLane()
/third_party/node/deps/v8/src/wasm/baseline/s390/
H A Dliftoff-assembler-s390.h2637 uint8_t laneidx, uint32_t* protected_load_pc) { in LoadLane()
2656 LoadLane8LE(dst.fp(), src_op, 15 - laneidx, r1); in LoadLane()
2658 LoadLane16LE(dst.fp(), src_op, 7 - laneidx, r1); in LoadLane()
2660 LoadLane32LE(dst.fp(), src_op, 3 - laneidx, r1); in LoadLane()
2663 LoadLane64LE(dst.fp(), src_op, 1 - laneidx, r1); in LoadLane()
2634 LoadLane(LiftoffRegister dst, LiftoffRegister src, Register addr, Register offset_reg, uintptr_t offset_imm, LoadType type, uint8_t laneidx, uint32_t* protected_load_pc) LoadLane() argument
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dinstruction-selector-arm.cc508 LoadStoreLaneParams f(params.rep, params.laneidx); in VisitStoreLane()
517 inputs[1] = g.UseImmediate(f.laneidx); in VisitStoreLane()
526 LoadStoreLaneParams f(params.rep.representation(), params.laneidx); in VisitLoadLane()
536 inputs[1] = g.UseImmediate(f.laneidx); in VisitLoadLane()
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dinstruction-selector-mips64.cc396 LoadStoreLaneParams f(params.rep, params.laneidx); in VisitStoreLane()
404 g.UseImmediate(f.laneidx), in VisitStoreLane()
413 LoadStoreLaneParams f(params.rep.representation(), params.laneidx); in VisitLoadLane()
420 g.UseImmediate(f.laneidx), addr, g.TempImmediate(0)); in VisitLoadLane()
/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dinstruction-selector-riscv64.cc434 LoadStoreLaneParams f(params.rep, params.laneidx); in VisitStoreLane()
445 g.UseImmediate(f.laneidx), in VisitStoreLane()
454 LoadStoreLaneParams f(params.rep.representation(), params.laneidx); in VisitLoadLane()
465 g.UseImmediate(params.laneidx), addr_reg, g.TempImmediate(0)); in VisitLoadLane()
/third_party/node/deps/v8/src/wasm/baseline/ia32/
H A Dliftoff-assembler-ia32.h2810 uint8_t laneidx, uint32_t* protected_load_pc) { in LoadLane()
2817 Pinsrb(dst.fp(), src.fp(), src_op, laneidx); in LoadLane()
2819 Pinsrw(dst.fp(), src.fp(), src_op, laneidx); in LoadLane()
2821 Pinsrd(dst.fp(), src.fp(), src_op, laneidx); in LoadLane()
2824 if (laneidx == 0) { in LoadLane()
2827 DCHECK_EQ(1, laneidx); in LoadLane()
2807 LoadLane(LiftoffRegister dst, LiftoffRegister src, Register addr, Register offset_reg, uintptr_t offset_imm, LoadType type, uint8_t laneidx, uint32_t* protected_load_pc) LoadLane() argument
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h2416 uint8_t laneidx, uint32_t* protected_load_pc) { in LoadLane()
2423 LoadStoreLaneParams load_params(type.mem_type().representation(), laneidx); in LoadLane()
2426 TurboAssembler::LoadLane(load_params.sz, dst_op, load_params.laneidx, in LoadLane()
2432 StoreType type, uint8_t laneidx, in StoreLane()
2439 LoadStoreLaneParams store_params(type.mem_rep(), laneidx); in StoreLane()
2442 TurboAssembler::StoreLane(store_params.sz, src_op, store_params.laneidx, in StoreLane()
2413 LoadLane(LiftoffRegister dst, LiftoffRegister src, Register addr, Register offset_reg, uintptr_t offset_imm, LoadType type, uint8_t laneidx, uint32_t* protected_load_pc) LoadLane() argument
2430 StoreLane(Register dst, Register offset, uintptr_t offset_imm, LiftoffRegister src, StoreType type, uint8_t laneidx, uint32_t* protected_store_pc) StoreLane() argument
/third_party/node/deps/v8/src/compiler/backend/x64/
H A Dcode-generator-x64.cc1026 uint8_t laneidx = i.InputUint8(1); \
1029 __ ASM_INSTR(dst, src, i.MemoryOperand(2), laneidx, &load_offset); \
1032 __ ASM_INSTR(dst, src, kScratchRegister, laneidx, &load_offset); \
1034 __ ASM_INSTR(dst, src, i.InputRegister(2), laneidx, &load_offset); \
1036 __ ASM_INSTR(dst, src, i.InputOperand(2), laneidx, &load_offset); \

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