Home
last modified time | relevance | path

Searched refs:kSRegSize (Results 1 - 25 of 25) sorted by relevance

/third_party/vixl/test/aarch64/
H A Dtest-assembler-sve-aarch64.cc478 TEST_SVE(sve_mla_mls_s) { MlaMlsHelper(config, kSRegSize); }
1669 ASSERT_EQUAL_64(-core.GetSVELaneCount(kSRegSize), x23);
1778 ASSERT_EQUAL_64(0x40000000 - core.GetSVELaneCount(kSRegSize), x22);
1911 int s_lane_count = core.GetSVELaneCount(kSRegSize);
2059 int s_lane_count = core.GetSVELaneCount(kSRegSize);
2219 int s_lane_count = core.GetSVELaneCount(kSRegSize);
2278 int s_lane_count = core.GetSVELaneCount(kSRegSize);
2283 uint64_t s_mask = GetUintMask(kSRegSize);
3205 PnextHelper(config, kSRegSize, in0, in0, exp00);
3206 PnextHelper(config, kSRegSize, in
[all...]
H A Dtest-simulator-aarch64.cc249 VIXL_ASSERT((d_size == kDRegSize) || (d_size == kSRegSize) || in Test1Op_Helper()
251 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize) || in Test1Op_Helper()
275 } else if (n_size == kSRegSize) { in Test1Op_Helper()
285 } else if (d_size == kSRegSize) { in Test1Op_Helper()
394 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize) || in Test2Op_Helper()
410 bool float_op = reg_size == kSRegSize; in Test2Op_Helper()
551 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize) || in Test3Op_Helper()
568 bool single_op = reg_size == kSRegSize; in Test3Op_Helper()
709 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmp_Helper()
850 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmpZero_Helper()
[all...]
H A Dtest-api-aarch64.cc248 VIXL_CHECK(VRegister(2, kSRegSize).Is(s2)); in TEST()
255 VIXL_CHECK(VRegister(2, kSRegSize, 1).Is(s2)); in TEST()
259 VIXL_CHECK(VRegister(0, kSRegSize, 2).Is(v0.V2H())); in TEST()
292 VIXL_CHECK(ZRegister(2, kSRegSize).Is(z2.VnS())); in TEST()
307 VIXL_CHECK(PRegisterWithLaneSize(2, kSRegSize).Is(p2.VnS())); in TEST()
328 VIXL_CHECK(CPURegister(4, kSRegSize, CPURegister::kVRegister).Is(s4)); in TEST()
581 VIXL_CHECK(p14.VnS().GetLaneSizeInBits() == kSRegSize); in TEST()
1174 VRegister temp = temps.AcquireVRegisterOfSize(kSRegSize); in TEST()
H A Dtest-utils-aarch64.cc538 s[i] = VRegister(n, kSRegSize); in PopulateVRegisterArray()
740 case kSRegSize: in GetSignallingNan()
807 case kSRegSize: in SetFpData()
878 SetFpData(masm, kSRegSize, kInputFloatBasic, lcg_mult); in InitialiseRegisterFp()
H A Dtest-utils-aarch64.h179 case kSRegSize:
H A Dtest-assembler-aarch64.cc8236 ASSERT_EQUAL_FP64(RawbitsToDouble((base_d >> kSRegSize) |
8237 ((2 * base_d) << kSRegSize)),
8241 ASSERT_EQUAL_FP32(RawbitsToFloat((4 * base_d) >> kSRegSize), s17);
8336 VIXL_CHECK(array[12] == ((1 * low_base) << kSRegSize));
8337 VIXL_CHECK(array[13] == (((2 * low_base) << kSRegSize) | (1 * high_base)));
8338 VIXL_CHECK(array[14] == (((3 * low_base) << kSRegSize) | (2 * high_base)));
8339 VIXL_CHECK(array[15] == (((4 * low_base) << kSRegSize) | (3 * high_base)));
8340 VIXL_CHECK(array[16] == (((1 * low_base) << kSRegSize) | (4 * high_base)));
8341 VIXL_CHECK(array[17] == (((2 * low_base) << kSRegSize) | (1 * high_base)));
8342 VIXL_CHECK(array[18] == (((3 * low_base) << kSRegSize) | (
[all...]
/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc902 VIXL_ASSERT(static_cast<unsigned>(lane_size_in_bits) <= kSRegSize); in PolynomialMult()
2164 VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) <= kSRegSize);
2438 VIXL_ASSERT(LaneSizeInBitsFromFormat(vformsrc) <= kSRegSize);
2559 case kSRegSize:
2615 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
2694 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
2711 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
5024 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { \
5068 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
5100 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
[all...]
H A Dregisters-aarch64.h449 VIXL_STATIC_ASSERT(kSRegSize == kWRegSize);
479 case kSRegSize:
653 ZRegister VnS() const { return ZRegister(GetCode(), kSRegSize); }
786 return PRegisterWithLaneSize(GetCode(), kSRegSize);
811 V(SRegister, kSRegSize, VRegister) \
H A Dinstructions-aarch64.cc40 (reg_size == kSRegSize) || (reg_size == kDRegSize)); in RepeatBitsAcrossReg()
1238 return kSRegSize; in RegisterSizeInBitsFromFormat()
H A Dinstructions-aarch64.h67 const unsigned kSRegSize = 32; member
69 const unsigned kSRegSizeInBytes = kSRegSize / 8;
H A Dmacro-assembler-sve-aarch64.cc394 case kSRegSize: in Cpy()
831 case kSRegSize: in Fdup()
853 case kSRegSize: in Fdup()
879 case kSRegSize: in Fdup()
H A Dassembler-sve-aarch64.cc57 VIXL_ASSERT((lane_size == kSRegSize) || (lane_size == kDRegSize)); in adr()
76 op = (lane_size == kSRegSize) ? ADR_z_az_s_same_scaled in adr()
4512 case kSRegSize: in SVEGatherPrefetchVectorPlusImmediateHelper()
4546 case kSRegSize: in SVEGatherPrefetchScalarPlusImmediateHelper()
4579 case kSRegSize: in SVEContiguousPrefetchScalarPlusScalarHelper()
4617 case kSRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4642 case kSRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4667 case kSRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4743 SVEPrefetchHelper(prfop, pg, addr, kSRegSize); in prfw()
5335 case kSRegSize in sdot()
[all...]
H A Dsimulator-aarch64.cc1018 (reg_size == kSRegSize) || (reg_size == kDRegSize)); in Simulator()
1511 case kSRegSize: in Simulator()
9646 sxt(vform, temp, temp, kSRegSize); in Simulator()
9649 uxt(vform, temp, temp, kSRegSize); in Simulator()
10698 dst_data_size = kSRegSize; in Simulator()
10713 dst_data_size = kSRegSize; in Simulator()
10723 dst_data_size = kSRegSize; in Simulator()
10724 src_data_size = kSRegSize; in Simulator()
10729 src_data_size = kSRegSize; in Simulator()
10867 src_data_size = kSRegSize; in Simulator()
[all...]
H A Ddisasm-aarch64.cc2274 if ((ls_dst == kDRegSize) || (ls_dst == kSRegSize)) { in Disassembler()
2283 VIXL_ASSERT((ls_dst == kSRegSize) || (ls_dst == kDRegSize)); in Disassembler()
6131 case kSRegSize: in Disassembler()
6492 reg_size = kSRegSize; in Disassembler()
H A Dmacro-assembler-aarch64.h975 // parameter. Only kXRegSize, kWRegSize, kDRegSize and kSRegSize are
1004 PushSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PushSRegList()
1007 PopSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PopSRegList()
1030 // parameter. Only kXRegSize, kWRegSize, kDRegSize and kSRegSize are
1074 PeekSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PeekSRegList()
1077 PokeSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PokeSRegList()
H A Dassembler-aarch64.cc6521 (width == kSRegSize) || (width == kDRegSize));
6728 case kSRegSize:
6751 case kSRegSize:
H A Dsimulator-aarch64.h1838 case kSRegSize:
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc3266 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { \
3302 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frecps()
3387 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frsqrts()
3435 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp()
3447 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp_zero()
3464 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabscmp()
3495 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmla()
3522 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmls()
3545 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fneg()
3570 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabs_()
3834 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); fcvtn() local
3851 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); fcvtn2() local
3862 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); fcvtxn() local
3871 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); fcvtxn2() local
[all...]
H A Dsimulator-arm64.h1005 (sizeof(T) == kSRegSize) || (sizeof(T) == kDRegSize) || in vreg()
1044 case kSRegSize: in vreg()
1067 (sizeof(value) == kSRegSize) || (sizeof(value) == kDRegSize) || in set_vreg()
1119 (sizeof(value) == kSRegSize) || in set_vreg_no_log()
1284 static_assert(sizeof(value) == kSRegSize, in GetPrintRegisterFormat()
1305 case kSRegSize: in GetPrintRegisterFormatForSizeFP()
1311 if ((GetPrintRegLaneSizeInBytes(format) == kSRegSize) || in GetPrintRegisterFormatTryFP()
H A Dsimulator-arm64.cc1222 case kSRegSize:
1235 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size.");
1453 DCHECK((lane_size_in_bytes == kSRegSize) ||
1466 const char* name = (lane_size_in_bytes == kSRegSize)
1482 double value = (lane_size_in_bytes == kSRegSize)
2205 DCHECK_EQ(access_size, static_cast<unsigned>(kSRegSize));
2241 DCHECK_EQ(access_size, static_cast<unsigned>(kSRegSize));
/third_party/vixl/benchmarks/aarch64/
H A Dbench-utils.h240 vixl::aarch64::VRegister PickS() { return PickV(vixl::aarch64::kSRegSize); } in PickS()
H A Dbench-utils.cc94 return ((entropy & 1) == 0) ? kSRegSize : kDRegSize; in PickFPSize()
/third_party/vixl/examples/aarch64/
H A Dneon-matrix-multiply.cc52 VRegister v_in = VRegister(in_column, kSRegSize); in GenerateMultiplyColumn()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dinstructions-arm64.cc172 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size."); in CalcLSPairDataSize()
H A Dconstants-arm64.h55 const int kSRegSize = kSRegSizeInBits >> 3; member

Completed in 117 milliseconds