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Searched refs:esgs_ring_size (Results 1 - 10 of 10) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_device.c3853 uint32_t esgs_ring_size, struct radeon_winsys_bo *esgs_ring_bo, in radv_fill_shader_rings()
3868 desc[2] = esgs_ring_size; in radv_fill_shader_rings()
3898 desc[6] = esgs_ring_size; in radv_fill_shader_rings()
4086 struct radeon_winsys_bo *esgs_ring_bo, uint32_t esgs_ring_size, in radv_emit_gs_ring_sizes()
4100 radeon_emit(cs, esgs_ring_size >> 8); in radv_emit_gs_ring_sizes()
4104 radeon_emit(cs, esgs_ring_size >> 8); in radv_emit_gs_ring_sizes()
4395 if (needs->esgs_ring_size > queue->ring_info.esgs_ring_size) { in radv_update_preamble_cs()
4396 result = ws->buffer_create(ws, needs->esgs_ring_size, 4096, RADEON_DOMAIN_VRAM, ring_bo_flags, in radv_update_preamble_cs()
4515 radv_fill_shader_rings(device, map, add_sample_positions, needs->esgs_ring_size, in radv_update_preamble_cs()
3852 radv_fill_shader_rings(struct radv_device *device, uint32_t *map, bool add_sample_positions, uint32_t esgs_ring_size, struct radeon_winsys_bo *esgs_ring_bo, uint32_t gsvs_ring_size, struct radeon_winsys_bo *gsvs_ring_bo, struct radeon_winsys_bo *tess_rings_bo, struct radeon_winsys_bo *task_rings_bo, struct radeon_winsys_bo *mesh_scratch_ring_bo) radv_fill_shader_rings() argument
4085 radv_emit_gs_ring_sizes(struct radv_device *device, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *esgs_ring_bo, uint32_t esgs_ring_size, struct radeon_winsys_bo *gsvs_ring_bo, uint32_t gsvs_ring_size) radv_emit_gs_ring_sizes() argument
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H A Dradv_shader.h236 uint32_t esgs_ring_size; member
H A Dradv_pipeline.c2465 ngg->esgs_ring_size = 1; in gfx10_get_ngg_ms_info()
2696 ngg->esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) * esvert_lds_size * 4; in gfx10_get_ngg_info()
2734 unsigned esgs_ring_size = in radv_pipeline_init_gs_ring_state() local
2739 esgs_ring_size = align(esgs_ring_size, alignment); in radv_pipeline_init_gs_ring_state()
2743 pipeline->esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); in radv_pipeline_init_gs_ring_state()
H A Dradv_shader.c1344 ngg_stage->info.ngg_info.esgs_ring_size = nir->info.shared_size; in radv_lower_ngg()
1348 info->ngg_info.esgs_ring_size, info->gs.gsvs_vertex_size, in radv_lower_ngg()
1927 sym->size = binary->info.ngg_info.esgs_ring_size; in radv_open_rtld_binary()
H A Dradv_private.h733 uint32_t esgs_ring_size;
2147 unsigned esgs_ring_size;
H A Dradv_cmd_buffer.c5609 if (graphics_pipeline->esgs_ring_size > cmd_buffer->esgs_ring_size_needed) in radv_CmdBindPipeline()
5610 cmd_buffer->esgs_ring_size_needed = graphics_pipeline->esgs_ring_size; in radv_CmdBindPipeline()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state_shaders.cpp922 out->esgs_ring_size = esgs_lds_size; in gfx9_get_gs_info()
3787 unsigned esgs_ring_size =
3792 esgs_ring_size = align(esgs_ring_size, alignment);
3795 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3803 bool update_esgs = sctx->gfx_level <= GFX8 && esgs_ring_size &&
3804 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size);
3818 esgs_ring_size, sctx->screen->info.pte_fragment_size);
H A Dsi_shader.h805 unsigned esgs_ring_size; /* in bytes */ member
H A Dsi_shader.c850 sym->size = shader->gs_info.esgs_ring_size * 4; in si_shader_binary_open()
H A Dgfx10_shader_ngg.c2506 shader->gs_info.esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) * in gfx10_ngg_calculate_subgroup_info()

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