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Searched refs:ds_info (Results 1 - 6 of 6) sorted by relevance

/third_party/mesa3d/src/broadcom/vulkan/
H A Dv3dvx_pipeline.c146 const VkPipelineDepthStencilStateCreateInfo *ds_info, in pack_cfg_bits()
216 if (ds_info && ds_info->depthTestEnable && has_ds_attachment) { in pack_cfg_bits()
217 config.z_updates_enable = ds_info->depthWriteEnable; in pack_cfg_bits()
218 config.depth_test_function = ds_info->depthCompareOp; in pack_cfg_bits()
228 ds_info ? ds_info->stencilTestEnable && has_ds_attachment: false; in pack_cfg_bits()
308 const VkPipelineDepthStencilStateCreateInfo *ds_info) in pack_stencil_cfg()
312 if (!ds_info || !ds_info in pack_stencil_cfg()
145 pack_cfg_bits(struct v3dv_pipeline *pipeline, const VkPipelineDepthStencilStateCreateInfo *ds_info, const VkPipelineRasterizationStateCreateInfo *rs_info, const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info, const VkPipelineRasterizationLineStateCreateInfoEXT *ls_info, const VkPipelineMultisampleStateCreateInfo *ms_info) pack_cfg_bits() argument
307 pack_stencil_cfg(struct v3dv_pipeline *pipeline, const VkPipelineDepthStencilStateCreateInfo *ds_info) pack_stencil_cfg() argument
348 pipeline_pack_state(struct v3dv_pipeline *pipeline, const VkPipelineColorBlendStateCreateInfo *cb_info, const VkPipelineDepthStencilStateCreateInfo *ds_info, const VkPipelineRasterizationStateCreateInfo *rs_info, const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info, const VkPipelineRasterizationLineStateCreateInfoEXT *ls_info, const VkPipelineMultisampleStateCreateInfo *ms_info) pipeline_pack_state() argument
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H A Dv3dv_pipeline.c2799 const VkPipelineDepthStencilStateCreateInfo *ds_info) in pipeline_set_ez_state()
2801 if (!ds_info || !ds_info->depthTestEnable) { in pipeline_set_ez_state()
2806 switch (ds_info->depthCompareOp) { in pipeline_set_ez_state()
2826 if (ds_info->stencilTestEnable && in pipeline_set_ez_state()
2827 (!stencil_op_is_no_op(&ds_info->front) || in pipeline_set_ez_state()
2828 !stencil_op_is_no_op(&ds_info->back))) { in pipeline_set_ez_state()
2953 const VkPipelineDepthStencilStateCreateInfo *ds_info = in pipeline_init() local
2984 vp_info, ds_info, cb_info, rs_info, cw_info); in pipeline_init()
2989 assert(!ds_info || !ds_inf in pipeline_init()
2798 pipeline_set_ez_state(struct v3dv_pipeline *pipeline, const VkPipelineDepthStencilStateCreateInfo *ds_info) pipeline_set_ez_state() argument
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/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_pipeline.c3476 const VkPipelineDepthStencilStateCreateInfo *ds_info = in tu_pipeline_builder_parse_depth_stencil() local
3485 if (ds_info->depthTestEnable) { in tu_pipeline_builder_parse_depth_stencil()
3488 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) | in tu_pipeline_builder_parse_depth_stencil()
3494 if (ds_info->depthWriteEnable) in tu_pipeline_builder_parse_depth_stencil()
3498 if (ds_info->depthBoundsTestEnable) in tu_pipeline_builder_parse_depth_stencil()
3501 if (ds_info->depthBoundsTestEnable && !ds_info->depthTestEnable) in tu_pipeline_builder_parse_depth_stencil()
3516 const VkStencilOpState *front = &ds_info->front; in tu_pipeline_builder_parse_depth_stencil()
3517 const VkStencilOpState *back = &ds_info->back; in tu_pipeline_builder_parse_depth_stencil()
3529 if (ds_info in tu_pipeline_builder_parse_depth_stencil()
3693 const VkPipelineDepthStencilStateCreateInfo *ds_info = tu_pipeline_builder_parse_rasterization_order() local
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/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_draw.c178 struct shader_info *ds_info = ir3_get_shader_info(emit.key.ds); variable
179 emit.key.key.tessellation = ir3_tess_mode(ds_info->tess._primitive_mode);
184 BITSET_TEST(ds_info->system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
/third_party/mesa3d/src/vulkan/runtime/
H A Dvk_graphics_state.c675 const VkPipelineDepthStencilStateCreateInfo *ds_info) in vk_depth_stencil_state_init()
679 ds->depth.test_enable = ds_info->depthTestEnable; in vk_depth_stencil_state_init()
680 ds->depth.write_enable = ds_info->depthWriteEnable; in vk_depth_stencil_state_init()
681 ds->depth.compare_op = ds_info->depthCompareOp; in vk_depth_stencil_state_init()
682 ds->depth.bounds_test.enable = ds_info->depthBoundsTestEnable; in vk_depth_stencil_state_init()
683 ds->depth.bounds_test.min = ds_info->minDepthBounds; in vk_depth_stencil_state_init()
684 ds->depth.bounds_test.max = ds_info->maxDepthBounds; in vk_depth_stencil_state_init()
686 ds->stencil.test_enable = ds_info->stencilTestEnable; in vk_depth_stencil_state_init()
688 vk_stencil_test_face_state_init(&ds->stencil.front, &ds_info->front); in vk_depth_stencil_state_init()
689 vk_stencil_test_face_state_init(&ds->stencil.back, &ds_info in vk_depth_stencil_state_init()
673 vk_depth_stencil_state_init(struct vk_depth_stencil_state *ds, const BITSET_WORD *dynamic, const VkPipelineDepthStencilStateCreateInfo *ds_info) vk_depth_stencil_state_init() argument
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_pipeline.c919 radv_is_depth_write_enabled(const struct radv_depth_stencil_info *ds_info) in radv_is_depth_write_enabled() argument
921 return ds_info->depth_test_enable && ds_info->depth_write_enable && in radv_is_depth_write_enabled()
922 ds_info->depth_compare_op != VK_COMPARE_OP_NEVER; in radv_is_depth_write_enabled()
934 radv_is_stencil_write_enabled(const struct radv_depth_stencil_info *ds_info) in radv_is_stencil_write_enabled() argument
936 return ds_info->stencil_test_enable && in radv_is_stencil_write_enabled()
937 (radv_writes_stencil(&ds_info->front) || radv_writes_stencil(&ds_info->back)); in radv_is_stencil_write_enabled()

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