Lines Matching refs:ds_info
3476 const VkPipelineDepthStencilStateCreateInfo *ds_info =
3485 if (ds_info->depthTestEnable) {
3488 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
3494 if (ds_info->depthWriteEnable)
3498 if (ds_info->depthBoundsTestEnable)
3501 if (ds_info->depthBoundsTestEnable && !ds_info->depthTestEnable)
3516 const VkStencilOpState *front = &ds_info->front;
3517 const VkStencilOpState *back = &ds_info->back;
3529 if (ds_info->stencilTestEnable) {
3558 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
3559 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
3563 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
3564 .bfmask = ds_info->back.compareMask & 0xff));
3568 update_stencil_mask(&pipeline->stencil_wrmask, VK_STENCIL_FACE_FRONT_BIT, ds_info->front.writeMask);
3569 update_stencil_mask(&pipeline->stencil_wrmask, VK_STENCIL_FACE_BACK_BIT, ds_info->back.writeMask);
3574 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
3575 .bfref = ds_info->back.reference & 0xff));
3693 const VkPipelineDepthStencilStateCreateInfo *ds_info =
3704 ds_info->flags &