| /third_party/jerryscript/jerry-libm/ |
| H A D | expm1.c | 55 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
60 * Q5 = -6.2843505682382617102E-9;
64 * | 1.0+Q1*z+...+Q5*z - R1(z) | <= 2
137 #define Q5 -2.01099218183624371326e-07 /* BE8AFDB7 6E09C32D */ macro
233 r1 = one + hxs * (Q1 + hxs * (Q2 + hxs * (Q3 + hxs * (Q4 + hxs * Q5)))); in expm1()
305 #undef Q5 macro
|
| /third_party/ffmpeg/libavcodec/x86/ |
| H A D | vp9lpf.asm | 331 %define Q5 dst2q + strideq + %1
351 %define Q5 rsp + 13*mmsize + %1
430 movx m13, [Q5]
469 mova [Q5], m13
489 movhps [Q5], m6
497 movx m5, [Q5]
513 movhps [Q5], m6
528 movx m7, [Q5]
737 mova m15, [Q5]
742 %define rq5 [Q5]
[all...] |
| H A D | vp9lpf_16bpp.asm | 580 PRELOAD 8, %%q5, Q5
|
| /third_party/musl/porting/liteos_a/kernel/src/math/ |
| H A D | expm1.c | 38 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
43 * Q5 = -6.2843505682382617102E-9;
47 * | 1.0+Q1*z+...+Q5*z - R1(z) | <= 2
119 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
170 r1 = 1.0+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
|
| /third_party/musl/src/math/ |
| H A D | expm1.c | 38 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
43 * Q5 = -6.2843505682382617102E-9;
47 * | 1.0+Q1*z+...+Q5*z - R1(z) | <= 2
119 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
170 r1 = 1.0+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
|
| H A D | AArch64PBQPRegAlloc.cpp | 81 case AArch64::Q5: in isOdd()
|
| H A D | AArch64FastISel.cpp | 3018 AArch64::Q5, AArch64::Q6, AArch64::Q7 } in fastLowerArguments()
|
| H A D | AArch64ISelLowering.cpp | 3639 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7}; in saveVarArgRegisters()
|
| /third_party/mesa3d/src/mesa/main/ |
| H A D | texcompress_astc.cpp | 174 uint8_t Q5 = (in >> (3*n+5)) & 0x1; in unpack_quint_block() local
183 if (CAT_BITS_4(Q6, Q5, Q2, Q1) == 0x3) { in unpack_quint_block()
190 C = CAT_BITS_5(Q4, Q3, 0x1 & ~Q6, 0x1 & ~Q5, Q0); in unpack_quint_block()
192 q2 = CAT_BITS_2(Q6, Q5); in unpack_quint_block()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 200 {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, in initLLVMToCVRegMapping()
|
| H A D | AArch64InstPrinter.cpp | 1169 case AArch64::Q4: Reg = AArch64::Q5; break; in getNextVectorRegister()
1170 case AArch64::Q5: Reg = AArch64::Q6; break; in getNextVectorRegister()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 96 SP::Q5, SP::Q13, ~0U, ~0U,
|
| /third_party/node/deps/v8/src/base/ |
| H A D | ieee754.cc | 2141 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
2146 * Q5 = -6.2843505682382617102E-9;
2150 * | 1.0+Q1*z+...+Q5*z - R1(z) | <= 2
2223 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ in expm1() local
2284 r1 = one + hxs * (Q1 + hxs * (Q2 + hxs * (Q3 + hxs * (Q4 + hxs * Q5)))); in expm1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 306 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
630 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 580 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: in getMachineOpValue()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 160 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1365 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1383 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2095 .Case("v5", AArch64::Q5) in MatchNeonVectorRegName()
|