Searched refs:NSACR (Results 1 - 6 of 6) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm35p.h	547 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ member 858 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 859 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 861 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 862 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 864 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ 865 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
H A D	core_cm33.h	547 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ member 858 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 859 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 861 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 862 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 864 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ 865 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
H A D	core_starmc1.h	559 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ member 876 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 877 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 879 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 880 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 882 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ 883 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
H A D	core_ca.h	779 __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ member
H A D	core_cm85.h	578 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ member 902 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 903 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 905 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 906 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 908 #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ 909 #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ 911 #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ 912 #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ 914 #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR [all...]
H A D	core_cm55.h	557 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ member 881 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 882 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 884 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 885 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 887 #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ 888 #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ 890 #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ 891 #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ 893 #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR [all...]

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Indexes created Thu Nov 07 10:32:03 CST 2024