Home
last modified time | relevance | path

Searched refs:HasLaneSize (Results 1 - 8 of 8) sorted by relevance

/third_party/vixl/src/aarch64/
H A Dregisters-aarch64.h118 bool HasLaneSize() const { return lane_size_ != kEncodedUnknownSize; } in HasLaneSize() function in vixl::aarch64::CPURegister
144 VIXL_ASSERT(HasLaneSize());
149 if (HasSize() && HasLaneSize()) {
183 // r.IsPRegister() && HasLaneSize() -> PRegisterWithLaneSize(r)
260 bool IsVector() const { return HasLaneSize() && (size_ != lane_size_); }
261 bool IsScalar() const { return HasLaneSize() && (size_ == lane_size_); }
663 VIXL_ASSERT(other.HasLaneSize());
680 return IsValidPRegister() && !HasLaneSize() && IsUnqualified();
732 return IsValidPRegister() && HasLaneSize() && IsUnqualified();
735 // Overload lane size accessors so we can assert `HasLaneSize()`
[all...]
H A Doperands-aarch64.h651 VIXL_ASSERT(base_.HasLaneSize()); in GetVectorBase()
662 VIXL_ASSERT(regoffset_.HasLaneSize()); in GetVectorOffset()
H A Dassembler-sve-aarch64.cc3283 VIXL_ASSERT(!pg.HasLaneSize()); in movprfx()
6095 if (pg.HasLaneSize()) VIXL_ASSERT(AreSameFormat(pg, pn)); in cntp()
6516 VIXL_ASSERT((!pd.HasLaneSize() && !pn.HasLaneSize()) || in mov()
H A Dassembler-aarch64.h7188 VIXL_ASSERT(!pg.HasLaneSize()); in PgLow8()
7196 VIXL_ASSERT(!pg.HasLaneSize()); in Pg()
7697 VIXL_ASSERT(rd.HasLaneSize());
H A Dmacro-assembler-aarch64.h5745 VIXL_ASSERT(!pd.HasLaneSize() || pd.IsLaneSizeB()); in Rdffr()
6530 VIXL_ASSERT(!pn.HasLaneSize() || pn.IsLaneSizeB()); in Wrffr()
H A Dassembler-aarch64.cc2509 VIXL_ASSERT(vt.HasSize() && vt.HasLaneSize()); in LoadStoreStructVerify()
/third_party/vixl/test/aarch64/
H A Dtest-utils-aarch64.h411 VIXL_ASSERT(reg.HasLaneSize());
438 VIXL_ASSERT(reg.HasLaneSize());
460 if (!result.HasLaneSize()) {
H A Dtest-utils-aarch64.cc391 VIXL_ASSERT(reg.HasLaneSize()); in EqualSVELane()

Completed in 53 milliseconds