| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-fp-aarch64.cc | 633 __ Fmul(s0, s17, s18); in TEST()
634 __ Fmul(s1, s18, s19); in TEST()
635 __ Fmul(s2, s14, s14); in TEST()
636 __ Fmul(s3, s15, s20); in TEST()
637 __ Fmul(s4, s16, s20); in TEST()
638 __ Fmul(s5, s15, s19); in TEST()
639 __ Fmul(s6, s19, s16); in TEST()
641 __ Fmul(d7, d30, d31); in TEST()
642 __ Fmul(d8, d29, d31); in TEST()
643 __ Fmul(d in TEST()
[all...] |
| H A D | test-disasm-neon-aarch64.cc | 1854 COMPARE_MACRO(Fmul(v22.V8H(), v23.V8H(), v24.V8H()), in TEST()
1856 COMPARE_MACRO(Fmul(v25.V4H(), v26.V4H(), v27.V4H()), in TEST()
1954 COMPARE_MACRO(Fmul(v6.M, v7.M, v8.M), "fmul v6." S ", v7." S ", v8." S); in TEST()
2496 COMPARE_MACRO(Fmul(v0.V4H(), v1.V4H(), v2.H(), 0), in TEST()
2498 COMPARE_MACRO(Fmul(v2.V8H(), v3.V8H(), v15.H(), 7), in TEST()
2500 COMPARE_MACRO(Fmul(v0.V2S(), v1.V2S(), v2.S(), 0), in TEST()
2502 COMPARE_MACRO(Fmul(v2.V4S(), v3.V4S(), v15.S(), 3), in TEST()
2504 COMPARE_MACRO(Fmul(v2.V4S(), v3.V4S(), v31.S(), 3), in TEST()
2506 COMPARE_MACRO(Fmul(v0.V2D(), v1.V2D(), v2.D(), 0), in TEST()
2508 COMPARE_MACRO(Fmul(v in TEST()
[all...] |
| H A D | test-assembler-sve-aarch64.cc | 12233 ArithFn fn = &MacroAssembler::Fmul;
14824 __ Fmul(z2.VnH(), z1.VnH(), z0.VnH(), 0);
14825 __ Fmul(z3.VnH(), z1.VnH(), z0.VnH(), 1);
14826 __ Fmul(z4.VnH(), z1.VnH(), z0.VnH(), 4);
14827 __ Fmul(z5.VnH(), z1.VnH(), z0.VnH(), 7);
14829 __ Fmul(z6.VnS(), z1.VnS(), z0.VnS(), 0);
14830 __ Fmul(z7.VnS(), z1.VnS(), z0.VnS(), 1);
14831 __ Fmul(z8.VnS(), z1.VnS(), z0.VnS(), 2);
14832 __ Fmul(z9.VnS(), z1.VnS(), z0.VnS(), 3);
14834 __ Fmul(z1
[all...] |
| H A D | test-utils-aarch64.cc | 855 __ Fmul(z31.WithLaneSize(esize), in SetFpData()
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| H A D | test-assembler-neon-aarch64.cc | 3772 __ Fmul(v6.V4H(), v1.V4H(), v0.V4H()); in TEST()
3773 __ Fmul(v7.V8H(), v3.V8H(), v2.V8H()); in TEST()
3774 __ Fmul(v8.V4H(), v4.V4H(), v3.V4H()); in TEST()
3775 __ Fmul(v9.V4H(), v0.V4H(), v1.V4H()); in TEST()
3776 __ Fmul(v10.V4H(), v5.V4H(), v0.V4H()); in TEST()
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| H A D | test-disasm-sve-aarch64.cc | 1014 COMPARE_MACRO(Fmul(z1.VnS(), in TEST()
1111 COMPARE_MACRO(Fmul(z21.VnH(), p3.Merging(), z11.VnH(), 2.0), in TEST()
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| /third_party/vixl/examples/aarch64/ |
| H A D | neon-matrix-multiply.cc | 38 // __ Fmul(v<v_out>.V4S(), v4.V4S(), v<s_column>.S(), 0);
54 __ Fmul(v_out, v4.V4S(), v_in, 0); // e.g. (v0.V4S(), v4.V4S(), v8.S(), 0). in GenerateMultiplyColumn()
|
| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 368 __ Fmul(PickV(size), PickV(size), PickV(size)); in GenerateFPSequence()
|
| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1123 FP32_BINOP(f32_mul, Fmul)
1136 FP64_BINOP(f64_mul, Fmul)
1850 Fmul(dst.fp().V2D(), lhs.fp().V2D(), rhs.fp().V2D()); in emit_f64x2_mul()
1991 Fmul(dst.fp().V4S(), lhs.fp().V4S(), rhs.fp().V4S()); in emit_f32x4_mul()
|
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1612 __ Fmul(i.OutputFloat32Register(), i.InputFloat32Register(0), in AssembleArchInstruction()
1656 __ Fmul(i.OutputDoubleRegister(), i.InputDoubleRegister(0), in AssembleArchInstruction()
2167 SIMD_BINOP_LANE_SIZE_CASE(kArm64FMul, Fmul); in AssembleArchInstruction()
2307 __ Fmul(i.OutputSimd128Register().Format(v_f), in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 217 V(fmul, Fmul) \
1070 inline void Fmul(const VRegister& fd, const VRegister& fn,
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| H A D | macro-assembler-arm64-inl.h | 729 void TurboAssembler::Fmul(const VRegister& fd, const VRegister& fn, in Fmul() function in v8::internal::TurboAssembler
|
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceConverter.cpp | 301 return convertArithInstruction(Instr, Ice::InstArithmetic::Fmul); in convertInstruction()
|
| H A D | IceTargetLoweringARM32.cpp | 2723 case InstArithmetic::Fmul: in lowerInt64Arithmetic()
2919 case InstArithmetic::Fmul:
3004 case InstArithmetic::Fmul: {
3325 case InstArithmetic::Fmul:
6646 case InstArithmetic::Fmul:
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| H A D | WasmTranslator.cpp | 432 Control()->appendInst(InstArithmetic::create(Func, InstArithmetic::Fmul, in Binop()
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| H A D | IceTargetLoweringX8632.cpp | 1867 case InstArithmetic::Fmul: in lowerArithmetic()
2013 case InstArithmetic::Fmul: { in lowerArithmetic()
2329 case InstArithmetic::Fmul: in lowerArithmetic()
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| H A D | PNaClTranslator.cpp | 1780 Op = Ice::InstArithmetic::Fmul; in convertBinopOpcode()
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| H A D | IceTargetLoweringMIPS32.cpp | 2688 case InstArithmetic::Fmul: in lowerInt64Arithmetic()
2970 case InstArithmetic::Fmul: in lowerArithmetic()
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| H A D | IceTargetLoweringX8664.cpp | 1813 case InstArithmetic::Fmul: { in lowerArithmetic()
2145 case InstArithmetic::Fmul: in lowerArithmetic()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 1698 void Fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fmul() function in vixl::aarch64::MacroAssembler
3106 V(fmul, Fmul) \
4697 void Fmul(const ZRegister& zd, in Fmul() function in vixl::aarch64::MacroAssembler
4705 void Fmul(const ZRegister& zd,
4710 void Fmul(const ZRegister& zd, in Fmul() function in vixl::aarch64::MacroAssembler
4718 void Fmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Fmul() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-sve-aarch64.cc | 734 void MacroAssembler::Fmul(const ZRegister& zd, in Fmul() function in vixl::aarch64::MacroAssembler
|
| /third_party/skia/third_party/externals/swiftshader/src/Reactor/ |
| H A D | SubzeroReactor.cpp | 1206 case Ice::InstArithmetic::Fmul:
1274 return createArithmetic(Ice::InstArithmetic::Fmul, lhs, rhs);
|