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Searched refs:DCB_DSCSR_SBRSELEN_Msk (Results 1 - 6 of 6) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm23.h1116 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ macro
H A Dcore_cm35p.h1927 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ macro
H A Dcore_cm33.h1927 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ macro
H A Dcore_starmc1.h2021 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ macro
H A Dcore_cm85.h3443 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ macro
H A Dcore_cm55.h3419 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ macro

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