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Searched refs:D6 (Results 1 - 24 of 24) sorted by relevance

/third_party/typescript/tests/baselines/reference/
H A DsubtypesOfTypeParameterWithRecursiveConstraints.js87 class D6<T extends Foo<U>, U extends Foo<T>, V extends Foo<V>> extends Base<U> {
139 class D6<T extends Foo<U>, U extends Foo<T>, V extends Foo<V>> extends Base2<U> {
262 var D6 = /** @class */ (function (_super) {
263 __extends(D6, _super);
264 function D6() {
267 return D6;
333 var D6 = /** @class */ (function (_super) {
334 __extends(D6, _super);
335 function D6() {
338 return D6;
[all...]
H A DsubtypesOfTypeParameterWithConstraints4.js61 class D6<T extends Foo, U extends Foo, V> extends B1<T> {
163 var D6 = /** @class */ (function (_super) {
164 __extends(D6, _super);
165 function D6() {
168 return D6;
H A DundefinedIsSubtypeOfEverything.js52 class D6 extends Base {
216 var D6 = /** @class */ (function (_super) {
217 __extends(D6, _super);
218 function D6() {
221 return D6;
/third_party/decimal.js/test/modules/
H A Dclone.js23 var D6 = Decimal.clone({ precision: 6 }); variable
38 var x6 = new D6(5);
60 var y6 = new D6(3);
90 t(D6.precision === 6);
/third_party/FreeBSD/lib/msun/ld128/
H A Ds_expl.c179 D6 = 1.38888888888888888888887138722762072e-3L, variable
254 q = x * x2 * D3 + x2 * x2 * (D4 + x * (D5 + x * (D6 + in expm1l()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp34 AArch64::D6, AArch64::D7};
H A DAArch64PBQPRegAlloc.cpp115 case AArch64::D6: in isOdd()
H A DAArch64FastISel.cpp3016 AArch64::D5, AArch64::D6, AArch64::D7 }, in fastLowerArguments()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h77 case D7: case D6: case D5: case D4: in isARMArea3Register()
H A DARMCallingConv.cpp163 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h117 case AArch64::D6: return AArch64::B6; in getBRegFromDReg()
157 case AArch64::B6: return AArch64::D6; in getDRegFromBReg()
/third_party/mbedtls/library/
H A Daes.c120 V(0D, F2, F2, FF), V(BD, 6B, 6B, D6), V(B1, 6F, 6F, DE), V(54, C5, C5, 91), \
137 V(F6, 52, 52, A4), V(4D, 3B, 3B, 76), V(61, D6, D6, B7), V(CE, B3, B3, 7D), \
182 V(CB, B0, B0, 7B), V(FC, 54, 54, A8), V(D6, BB, BB, 6D), V(3A, 16, 16, 2C)
268 V(24, FB, 98, 19), V(97, E9, BD, D6), V(CC, 43, 40, 89), V(77, 9E, D9, 67), \
294 V(D9, 9B, E7, BA), V(CE, 36, 6F, 4A), V(D4, 09, 9F, EA), V(D6, 7C, B0, 29), \
298 V(8D, D6, 4D, 76), V(4D, B0, EF, 43), V(54, 4D, AA, CC), V(DF, 04, 96, E4), \
301 V(5A, 1D, 67, B3), V(52, D2, DB, 92), V(33, 56, 10, E9), V(13, 47, D6, 6D), \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp63 D0, D1, D2, D3, D4, D5, D6, D7, 0 in getCallerSavedRegs()
H A DHexagonISelLowering.cpp281 .Case("r13:12", Hexagon::D6) in getRegisterByName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp169 {codeview::RegisterId::ARM64_D6, AArch64::D6}, in initLLVMToCVRegMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp84 SP::D6, SP::D22, SP::D7, SP::D23,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1168 VA.convertToReg(Mips::D6); in processCallArgs()
1337 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}}; in fastLowerArguments()
H A DMipsISelLowering.cpp2969 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; in CC_MipsO32_FP32()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp586 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, in DecodeDoubleRegsRegisterClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp150 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp335 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1317 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3237 case Mips::D6: return Mips::F13; in nextReg()
/third_party/skia/third_party/externals/microhttpd/doc/
H A Dtexinfo.tex9298 \DeclareUnicodeCharacter{00D6}{\"O}

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