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Searched refs:D15 (Results 1 - 15 of 15) sorted by relevance

/third_party/typescript/tests/baselines/reference/
H A DundefinedIsSubtypeOfEverything.js105 class D15<T, U> extends Base {
109 //class D15<T, U extends T> extends Base {
295 var D15 = /** @class */ (function (_super) {
296 __extends(D15, _super);
297 function D15() {
300 return D15;
302 //class D15<T, U extends T> extends Base {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp208 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
216 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
224 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
232 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
240 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
248 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
256 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
264 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
588 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; in DecodeDoubleRegsRegisterClass()
/third_party/FreeBSD/lib/msun/ld128/
H A Ds_expl.c197 D15 = 7.6478532249581686e-13, /* 0x1.ae892e3D16fcep-41 */ variable
257 dx * (D14 + dx * (D15 + dx * (D16 + in expm1l()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h75 case D15: case D14: case D13: case D12: in isARMArea3Register()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h126 case AArch64::D15: return AArch64::B15; in getBRegFromDReg()
166 case AArch64::B15: return AArch64::D15; in getDRegFromBReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp247 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) in getMax32BitSubRegister()
672 .addDef(Hexagon::D15) in insertEpilogueInBlock()
720 .addDef(Hexagon::D15) in insertEpilogueInBlock()
726 .addDef(Hexagon::D15) in insertEpilogueInBlock()
963 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) { in insertCFIInstructionsAt()
H A DHexagonISelLowering.cpp290 .Case("r31:30", Hexagon::D15) in getRegisterByName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp70 case AArch64::D15: in isOdd()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp675 // D14/D15 pair = 0x00000800
685 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
H A DAArch64MCTargetDesc.cpp178 {codeview::RegisterId::ARM64_D15, AArch64::D15}, in initLLVMToCVRegMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp88 SP::D14, SP::D30, SP::D15, SP::D31 };
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp152 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp337 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1319 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3191 // Each double-precision register DO-D15 overlaps with two of the single
3246 case Mips::D15: return Mips::F31; in nextReg()

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