| /third_party/typescript/tests/baselines/reference/ |
| H A D | undefinedIsSubtypeOfEverything.js | 78 class D11 extends Base {
255 var D11 = /** @class */ (function (_super) {
256 __extends(D11, _super);
257 function D11() {
260 return D11;
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| /third_party/FreeBSD/lib/msun/ld128/ |
| H A D | s_expl.c | 184 D11 = 2.50521083855084570046480450935267433e-8L, variable
190 * XXX can start the double coeffs but not the double mults at D11.
191 * With my coeffs (D11-D16 double):
256 x * (D11 + x * (D12 + x * (D13 + in expm1l()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 76 case D11: case D10: case D9: case D8: in isARMArea3Register()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 90 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
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| H A D | HexagonFrameLowering.cpp | 931 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, in insertCFIInstructionsAt()
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| H A D | HexagonISelLowering.cpp | 286 .Case("r23:22", Hexagon::D11) in getRegisterByName()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 122 case AArch64::D11: return AArch64::B11; in getBRegFromDReg()
162 case AArch64::B11: return AArch64::D11; in getDRegFromBReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 68 case AArch64::D11: in isOdd()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 587 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, in DecodeDoubleRegsRegisterClass()
597 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; in DecodeGeneralDoubleLow8RegsRegisterClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 257 case D11: in getDuplexRegisterNumbering()
561 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11)); in isDblRegForSubInst()
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| H A D | HexagonMCDuplexInfo.cpp | 693 case Hexagon::D11: in addOps()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 673 // D10/D11 pair = 0x00000200,
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
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| H A D | AArch64MCTargetDesc.cpp | 174 {codeview::RegisterId::ARM64_D11, AArch64::D11}, in initLLVMToCVRegMapping()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 86 SP::D10, SP::D26, SP::D11, SP::D27,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 151 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 336 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1318 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3242 case Mips::D11: return Mips::F23; in nextReg()
|