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Searched refs:CPUID (Results 1 - 25 of 34) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/src/Common/
H A DCPUID.cpp15 #include "CPUID.hpp"
32 bool CPUID::MMX = detectMMX();
33 bool CPUID::CMOV = detectCMOV();
34 bool CPUID::SSE = detectSSE();
35 bool CPUID::SSE2 = detectSSE2();
36 bool CPUID::SSE3 = detectSSE3();
37 bool CPUID::SSSE3 = detectSSSE3();
38 bool CPUID::SSE4_1 = detectSSE4_1();
39 int CPUID::cores = detectCoreCount();
40 int CPUID
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H A DCPUID.hpp28 class CPUID class
86 inline bool CPUID::supportsMMX() in supportsMMX()
91 inline bool CPUID::supportsCMOV() in supportsCMOV()
96 inline bool CPUID::supportsMMX2() in supportsMMX2()
101 inline bool CPUID::supportsSSE() in supportsSSE()
106 inline bool CPUID::supportsSSE2() in supportsSSE2()
111 inline bool CPUID::supportsSSE3() in supportsSSE3()
116 inline bool CPUID::supportsSSSE3() in supportsSSSE3()
121 inline bool CPUID::supportsSSE4_1() in supportsSSE4_1()
126 inline int CPUID
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/third_party/skia/third_party/externals/swiftshader/src/System/
H A DCPUID.cpp15 #include "CPUID.hpp"
50 bool CPUID::supportsMMX() in supportsMMX()
57 bool CPUID::supportsCMOV() in supportsCMOV()
64 bool CPUID::supportsSSE() in supportsSSE()
71 bool CPUID::supportsSSE2() in supportsSSE2()
78 bool CPUID::supportsSSE3() in supportsSSE3()
85 bool CPUID::supportsSSSE3() in supportsSSSE3()
92 bool CPUID::supportsSSE4_1() in supportsSSE4_1()
99 int CPUID::coreCount() in coreCount()
128 int CPUID
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H A DCPUID.hpp28 class CPUID class
/third_party/skia/third_party/externals/swiftshader/src/Reactor/
H A DCPUID.cpp15 #include "CPUID.hpp"
50 bool CPUID::supportsMMX() in supportsMMX()
57 bool CPUID::supportsCMOV() in supportsCMOV()
64 bool CPUID::supportsSSE() in supportsSSE()
71 bool CPUID::supportsSSE2() in supportsSSE2()
78 bool CPUID::supportsSSE3() in supportsSSE3()
85 bool CPUID::supportsSSSE3() in supportsSSSE3()
92 bool CPUID::supportsSSE4_1() in supportsSSE4_1()
H A DCPUID.hpp28 class CPUID class
H A DSubzeroReactor.cpp287 class CPUID class
337 constexpr bool CPUID::ARM = CPUID::detectARM();
338 const bool CPUID::SSE4_1 = CPUID::detectSSE4_1();
340 constexpr bool emulateMismatchedBitCast = CPUID::ARM;
522 if(CPUID::ARM) in relocateSymbol()
895 Flags.setTargetInstructionSet(CPUID::SSE4_1 ? Ice::X86InstructionSet_SSE4_1 : Ice::X86InstructionSet_SSE2);
2367 if(emulateIntrinsics || CPUID::ARM)
2479 if(emulateIntrinsics || CPUID
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H A DLLVMReactor.cpp17 #include "CPUID.hpp"
2187 if(CPUID::supportsSSE4_1()) in UShort4()
2560 if(CPUID::supportsSSE4_1()) in Int4()
2584 if(CPUID::supportsSSE4_1()) in Int4()
2608 if(CPUID::supportsSSE4_1()) in Int4()
2626 if(CPUID::supportsSSE4_1()) in Int4()
2712 if(CPUID::supportsSSE4_1()) in Max()
2728 if(CPUID::supportsSSE4_1()) in Min()
2895 if(CPUID::supportsSSE4_1()) in Max()
2911 if(CPUID in Min()
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/third_party/mesa3d/src/mesa/x86/
H A Dcommon_x86_asm.S26 * Check extended CPU capabilities. Now justs returns the raw CPUID
52 /* Test for the CPUID command. If the ID Flag bit in EFLAGS
53 * (bit 21) is writable, the CPUID command is present */
80 CPUID
103 CPUID
116 CPUID
130 CPUID
144 CPUID
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h109 unsigned CPUID) const { in isZeroIdiom()
114 /// subtarget associated with CPUID .
120 /// If MI is a dependency breaking instruction for subtarget CPUID, then Mask
134 unsigned CPUID) const { in isDependencyBreaking()
135 return isZeroIdiom(MI, Mask, CPUID); in isDependencyBreaking()
145 unsigned CPUID) const { in isOptimizableRegisterMove()
H A DMCSubtargetInfo.h215 unsigned CPUID) const { in resolveVariantSchedClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
H A DMCSchedule.cpp75 unsigned CPUID = getProcessorID(); in computeInstrLatency() local
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in computeInstrLatency()
121 unsigned CPUID = getProcessorID(); in getReciprocalThroughput() local
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in getReciprocalThroughput()
/third_party/skia/third_party/externals/swiftshader/src/Renderer/
H A DRenderer.cpp26 #include "Common/CPUID.hpp"
749 CPUID::setFlushToZero(true); in threadFunction()
750 CPUID::setDenormalsAreZero(true); in threadFunction()
2940 case -1: threadCount = CPUID::coreCount(); break;
2941 case 0: threadCount = CPUID::processAffinity(); break;
2945 CPUID::setEnableSSE4_1(configuration.enableSSE4_1);
2946 CPUID::setEnableSSSE3(configuration.enableSSSE3);
2947 CPUID::setEnableSSE3(configuration.enableSSE3);
2948 CPUID::setEnableSSE2(configuration.enableSSE2);
2949 CPUID
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H A DSurface.cpp23 #include "Common/CPUID.hpp"
3059 if(CPUID::supportsSSE()) in memfill4()
3818 if(CPUID::supportsSSE2() && (width % 4) == 0) in resolve()
4112 if(CPUID::supportsSSE2() && (width % 4) == 0) in resolve()
4405 if(CPUID::supportsSSE2() && (width % 2) == 0) in resolve()
4698 if(CPUID::supportsSSE() && (width % 4) == 0) in resolve()
4995 if(CPUID::supportsSSE() && (width % 2) == 0) in resolve()
5294 if(CPUID::supportsSSE()) in resolve()
5591 if(CPUID::supportsSSE2() && (width % 8) == 0) in resolve()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/BinaryFormat/
H A DMinidump.h150 support::ulittle32_t CPUID; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/
H A DInstrBuilder.cpp524 unsigned CPUID = SM.getProcessorID();
526 SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID);
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_sc000.h355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
368 /** \brief SCB CPUID Register Definitions */
369 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
370 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
372 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
373 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
375 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
376 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
378 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
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H A Dcore_cm1.h344 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
355 /** \brief SCB CPUID Register Definitions */
356 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
359 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
362 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
365 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
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H A Dcore_cm0.h344 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
355 /** \brief SCB CPUID Register Definitions */
356 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
359 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
362 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
365 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
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H A Dcore_cm0plus.h358 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
373 /** \brief SCB CPUID Register Definitions */
374 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
377 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
380 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
383 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
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H A Dcore_cm4.h455 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
480 /** \brief SCB CPUID Register Definitions */
481 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
482 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
484 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
485 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
487 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
488 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
490 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
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H A Dcore_sc300.h382 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
407 /** \brief SCB CPUID Register Definitions */
408 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
409 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
411 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
412 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
414 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
415 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
417 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
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H A Dcore_cm3.h382 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
407 /** \brief SCB CPUID Register Definitions */
408 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
409 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
411 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
412 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
414 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
415 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
417 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
[all...]
H A Dcore_cm23.h384 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ member
399 /** \brief SCB CPUID Register Definitions */
400 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
403 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
406 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
409 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ObjectYAML/
H A DMinidumpYAML.cpp165 mapRequiredHex(IO, "CPUID", Info.CPUID); in mapping()

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