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/kernel/linux/linux-5.10/drivers/clk/pistachio/
H A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104,
[all...]
/kernel/linux/linux-6.6/drivers/clk/pistachio/
H A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104,
[all...]
/kernel/linux/linux-5.10/drivers/memory/tegra/
H A Dtegra20.c181 TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
182 TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
183 TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
184 TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
185 TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
186 TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
187 TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
188 TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
189 TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
190 TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104,
[all...]
/kernel/linux/linux-6.6/drivers/memory/tegra/
H A Dtegra20.c262 TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
263 TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
264 TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
265 TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
266 TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
267 TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
268 TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
269 TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
270 TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
271 TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104,
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/marvell/mwifiex/
H A Dcfp.c88 0x1a, 0x34, 0x4e, 0x68, 0x9c, 0xd0, 0xea, 0x104 },
92 0x1c, 0x39, 0x56, 0x73, 0xad, 0xe7, 0x104, 0x120 }
102 { 0x82, 0x104, 0x186, 0x208, 0x30C, 0x410, 0x492,
110 { 0x41, 0x82, 0xC3, 0x104, 0x186, 0x208, 0x249,
135 { 0x104, 0x208, 0x30C, 0x410, 0x618, 0x820, 0x924,
143 { 0x82, 0x104, 0x186, 0x208, 0x30C, 0x410, 0x492,
155 { 0x1A, 0x34, 0x4A, 0x68, 0x9C, 0xD0, 0xEA, 0x104,
159 { 0x1D, 0x3A, 0x57, 0x74, 0xAE, 0xE6, 0x104, 0x121,
/kernel/linux/linux-6.6/drivers/net/wireless/marvell/mwifiex/
H A Dcfp.c76 0x1a, 0x34, 0x4e, 0x68, 0x9c, 0xd0, 0xea, 0x104 },
80 0x1c, 0x39, 0x56, 0x73, 0xad, 0xe7, 0x104, 0x120 }
90 { 0x82, 0x104, 0x186, 0x208, 0x30C, 0x410, 0x492,
98 { 0x41, 0x82, 0xC3, 0x104, 0x186, 0x208, 0x249,
123 { 0x104, 0x208, 0x30C, 0x410, 0x618, 0x820, 0x924,
131 { 0x82, 0x104, 0x186, 0x208, 0x30C, 0x410, 0x492,
143 { 0x1A, 0x34, 0x4A, 0x68, 0x9C, 0xD0, 0xEA, 0x104,
147 { 0x1D, 0x3A, 0x57, 0x74, 0xAE, 0xE6, 0x104, 0x121,
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx8mp.c460 hws[IMX8MP_SYS_PLL2_REF_SEL] = imx_clk_hw_mux("sys_pll2_ref_sel", anatop_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mp_clocks_probe()
471 hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll); in imx8mp_clocks_probe()
482 hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx8mp_clocks_probe()
514 hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27); in imx8mp_clocks_probe()
515 hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25); in imx8mp_clocks_probe()
516 hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23); in imx8mp_clocks_probe()
517 hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21); in imx8mp_clocks_probe()
518 hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19); in imx8mp_clocks_probe()
519 hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17); in imx8mp_clocks_probe()
520 hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 1 in imx8mp_clocks_probe()
[all...]
H A Dclk-imx8mm.c385 hws[IMX8MM_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27); in imx8mm_clocks_probe()
386 hws[IMX8MM_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25); in imx8mm_clocks_probe()
387 hws[IMX8MM_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23); in imx8mm_clocks_probe()
388 hws[IMX8MM_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21); in imx8mm_clocks_probe()
389 hws[IMX8MM_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19); in imx8mm_clocks_probe()
390 hws[IMX8MM_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17); in imx8mm_clocks_probe()
391 hws[IMX8MM_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15); in imx8mm_clocks_probe()
392 hws[IMX8MM_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13); in imx8mm_clocks_probe()
393 hws[IMX8MM_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); in imx8mm_clocks_probe()
H A Dclk-imx8mn.c380 hws[IMX8MN_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27); in imx8mn_clocks_probe()
381 hws[IMX8MN_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25); in imx8mn_clocks_probe()
382 hws[IMX8MN_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23); in imx8mn_clocks_probe()
383 hws[IMX8MN_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21); in imx8mn_clocks_probe()
384 hws[IMX8MN_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19); in imx8mn_clocks_probe()
385 hws[IMX8MN_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17); in imx8mn_clocks_probe()
386 hws[IMX8MN_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15); in imx8mn_clocks_probe()
387 hws[IMX8MN_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13); in imx8mn_clocks_probe()
388 hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); in imx8mn_clocks_probe()
/kernel/linux/linux-5.10/drivers/clk/axs10x/
H A Di2s_pll_clock.c37 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
38 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
42 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
44 { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
/kernel/linux/linux-6.6/drivers/clk/axs10x/
H A Di2s_pll_clock.c34 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
35 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
39 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
41 { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
/kernel/linux/linux-5.10/arch/mips/pci/
H A Dpci-vr41xx.h78 #define COMMANDREG 0x104
79 #define STATUSREG 0x104
/kernel/linux/linux-5.10/drivers/media/pci/bt8xx/
H A Dbt878.h37 #define BT878_AINT_MASK 0x104
73 #define BT878_INT_MASK 0x104
/kernel/linux/linux-6.6/drivers/media/pci/bt8xx/
H A Dbt878.h37 #define BT878_AINT_MASK 0x104
73 #define BT878_INT_MASK 0x104
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
H A Dregs-sys-s3c64xx.h17 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
H A Dregs-sys-s3c64xx.h17 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
/kernel/linux/linux-5.10/include/linux/
H A Datmel_pdc.h16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
H A Dmicrel_phy.h45 #define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW 0x104
/kernel/linux/linux-6.6/include/linux/
H A Datmel_pdc.h16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
/kernel/linux/linux-5.10/arch/arm/mach-tango/
H A Dsmc.h5 #define tango_start_aux_core(val) tango_smc(val, 0x104)
/kernel/linux/linux-5.10/arch/arm/mach-orion5x/
H A Dbridge-regs.h16 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
/kernel/linux/linux-6.6/arch/arm/mach-orion5x/
H A Dbridge-regs.h11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_regs.h28 #define BLK_P0_PTR_HIGH 0x104
77 #define GCU_CONFIGURATION_ID1 0x104
231 #define CU_INPUT2_OFFSET 0x104
391 #define BS_FRAME_TO 0x104
/kernel/linux/linux-6.6/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_regs.h28 #define BLK_P0_PTR_HIGH 0x104
77 #define GCU_CONFIGURATION_ID1 0x104
231 #define CU_INPUT2_OFFSET 0x104
391 #define BS_FRAME_TO 0x104
/kernel/linux/linux-5.10/drivers/media/usb/gspca/
H A Dstk1135.h18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */

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