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Searched refs:vuip (Results 1 - 25 of 48) sorted by relevance

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/kernel/linux/linux-5.10/arch/alpha/kernel/
H A Dcore_apecs.c48 #define vuip volatile unsigned int * macro
138 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
139 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
145 haxr2 = *(vuip)APECS_IOC_HAXR2; in conf_read()
147 *(vuip)APECS_IOC_HAXR2 = haxr2 | 1; in conf_read()
159 asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr) in conf_read()
180 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
191 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
200 *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1; in conf_read()
218 stat0 = *(vuip)APECS_IOC_DCS in conf_write()
[all...]
H A Dcore_mcpcia.c102 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
103 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; in conf_read()
105 *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
116 value = *((vuip)addr); in conf_read()
147 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
148 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); in conf_write()
149 *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
158 *((vuip)addr) = value; in conf_write()
161 *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ in conf_write()
250 *(vuip)MCPCIA_SG_TBI in mcpcia_pci_tbi()
[all...]
H A Dsys_alcor.c41 *(vuip)GRU_INT_MASK = mask; in alcor_update_irq_hw()
63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()
64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()
73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()
74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()
91 pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS; in alcor_device_interrupt()
116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()
117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()
118 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ in alcor_init_irq()
119 *(vuip)GRU_INT_CLEA in alcor_init_irq()
[all...]
H A Dsys_rawhide.c49 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; in rawhide_update_irq_hw()
51 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)); in rawhide_update_irq_hw()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; in rawhide_init_irq()
178 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; in rawhide_init_irq()
H A Dcore_polaris.c101 *value = *(vuip)addr; in polaris_read_config()
131 *(vuip)addr = value; in polaris_write_config()
133 *(vuip)addr; in polaris_write_config()
H A Dcore_irongate.c120 *value = *(vuip)addr; in irongate_read_config()
149 *(vuip)addr = value; in irongate_write_config()
151 *(vuip)addr; in irongate_write_config()
H A Dcore_marvel.c562 *value = *(vuip)addr; in marvel_read_config()
592 *(vuip)addr = value; in marvel_write_config()
594 *(vuip)addr; in marvel_write_config()
1096 vuip addr; in marvel_agp_info()
1102 addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0); in marvel_agp_info()
/kernel/linux/linux-6.6/arch/alpha/kernel/
H A Dcore_apecs.c48 #define vuip volatile unsigned int * macro
138 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
139 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
145 haxr2 = *(vuip)APECS_IOC_HAXR2; in conf_read()
147 *(vuip)APECS_IOC_HAXR2 = haxr2 | 1; in conf_read()
159 asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr) in conf_read()
180 stat0 = *(vuip)APECS_IOC_DCSR; in conf_read()
191 *(vuip)APECS_IOC_DCSR = stat0; in conf_read()
200 *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1; in conf_read()
218 stat0 = *(vuip)APECS_IOC_DCS in conf_write()
[all...]
H A Dcore_mcpcia.c102 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
103 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; in conf_read()
105 *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()
116 value = *((vuip)addr); in conf_read()
147 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
148 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); in conf_write()
149 *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()
158 *((vuip)addr) = value; in conf_write()
161 *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ in conf_write()
250 *(vuip)MCPCIA_SG_TBI in mcpcia_pci_tbi()
[all...]
H A Dsys_alcor.c41 *(vuip)GRU_INT_MASK = mask; in alcor_update_irq_hw()
63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()
64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()
73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()
74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()
91 pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS; in alcor_device_interrupt()
116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()
117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()
118 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ in alcor_init_irq()
119 *(vuip)GRU_INT_CLEA in alcor_init_irq()
[all...]
H A Dsys_rawhide.c49 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; in rawhide_update_irq_hw()
51 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)); in rawhide_update_irq_hw()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; in rawhide_init_irq()
178 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; in rawhide_init_irq()
H A Dcore_polaris.c101 *value = *(vuip)addr; in polaris_read_config()
131 *(vuip)addr = value; in polaris_write_config()
133 *(vuip)addr; in polaris_write_config()
H A Dcore_irongate.c120 *value = *(vuip)addr; in irongate_read_config()
149 *(vuip)addr = value; in irongate_write_config()
151 *(vuip)addr; in irongate_write_config()
/kernel/linux/linux-5.10/arch/alpha/include/asm/
H A Djensen.h100 #define vuip volatile unsigned int * macro
116 return 0xff & *(vuip)((addr << 9) + EISA_VL82C106); in jensen_local_inb()
121 *(vuip)((addr << 9) + EISA_VL82C106) = b; in jensen_local_outb()
137 *(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101; in jensen_bus_outb()
183 return *(vuip) ((addr << 7) + EISA_IO + 0x60); in jensen_inl()
189 *(vuip) ((addr << 7) + EISA_IO + 0x20) = b * 0x00010001; in jensen_outw()
196 *(vuip) ((addr << 7) + EISA_IO + 0x60) = b; in jensen_outl()
233 return *(vuip) ((addr << 7) + EISA_MEM + 0x60); in jensen_readl()
244 r0 = *(vuip) (addr); in jensen_readq()
245 r1 = *(vuip) (add in jensen_readq()
329 #undef vuip global() macro
[all...]
H A Dcore_t2.h362 #define vuip volatile unsigned int * macro
375 *(vuip) ((addr << 5) + T2_IO + 0x00) = w; in t2_outb()
390 *(vuip) ((addr << 5) + T2_IO + 0x08) = w; in t2_outw()
396 return *(vuip) ((addr << 5) + T2_IO + 0x18); in t2_inl()
401 *(vuip) ((addr << 5) + T2_IO + 0x18) = b; in t2_outl()
471 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); in t2_readw()
486 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); in t2_readl()
498 r0 = *(vuip)(work); in t2_readq()
499 r1 = *(vuip)(work + (4 << 5)); in t2_readq()
511 *(vuip) ((add in t2_writeb()
597 #undef vuip global() macro
[all...]
H A Dcore_apecs.h375 #define vuip volatile unsigned int __force * macro
420 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite8()
456 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite16()
464 return *(vuip)addr; in apecs_ioread32()
472 *(vuip)addr = b; in apecs_iowrite32()
499 #undef vuip macro
H A Dcore_cia.h342 #define vuip volatile unsigned int __force * macro
374 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite8()
404 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite16()
412 return *(vuip)addr; in cia_ioread32()
420 *(vuip)addr = b; in cia_iowrite32()
466 #undef vuip macro
H A Dcore_lca.h220 #define vuip volatile unsigned int __force * macro
266 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite8()
302 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite16()
310 return *(vuip)addr; in lca_ioread32()
318 *(vuip)addr = b; in lca_iowrite32()
343 #undef vuip macro
H A Dcore_mcpcia.h250 #define vuip volatile unsigned int __force * macro
291 *(vuip) ((addr << 5) + hose + 0x00) = w; in mcpcia_iowrite8()
315 *(vuip) ((addr << 5) + hose + 0x08) = w; in mcpcia_iowrite16()
325 return *(vuip)addr; in mcpcia_ioread32()
335 *(vuip)addr = b; in mcpcia_iowrite32()
364 #undef vuip macro
/kernel/linux/linux-6.6/arch/alpha/include/asm/
H A Djensen.h100 #define vuip volatile unsigned int * macro
117 return 0xff & *(vuip)((addr << 9) + EISA_VL82C106); in jensen_local_inb()
122 *(vuip)((addr << 9) + EISA_VL82C106) = b; in jensen_local_outb()
138 *(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101; in jensen_bus_outb()
184 return *(vuip) ((addr << 7) + EISA_IO + 0x60); in jensen_inl()
196 *(vuip) ((addr << 7) + EISA_IO + 0x20) = b * 0x00010001; in jensen_outw()
203 *(vuip) ((addr << 7) + EISA_IO + 0x60) = b; in jensen_outl()
247 return *(vuip) ((addr << 7) + EISA_MEM + 0x60); in jensen_readl()
258 r0 = *(vuip) (addr); in jensen_readq()
259 r1 = *(vuip) (add in jensen_readq()
344 #undef vuip global() macro
[all...]
H A Dcore_t2.h362 #define vuip volatile unsigned int * macro
376 *(vuip) ((addr << 5) + T2_IO + 0x00) = w; in t2_outb()
391 *(vuip) ((addr << 5) + T2_IO + 0x08) = w; in t2_outw()
397 return *(vuip) ((addr << 5) + T2_IO + 0x18); in t2_inl()
402 *(vuip) ((addr << 5) + T2_IO + 0x18) = b; in t2_outl()
483 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); in t2_readw()
498 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); in t2_readl()
510 r0 = *(vuip)(work); in t2_readq()
511 r1 = *(vuip)(work + (4 << 5)); in t2_readq()
523 *(vuip) ((add in t2_writeb()
610 #undef vuip global() macro
[all...]
H A Dcore_mcpcia.h250 #define vuip volatile unsigned int __force * macro
292 *(vuip) ((addr << 5) + hose + 0x00) = w; in mcpcia_iowrite8()
316 *(vuip) ((addr << 5) + hose + 0x08) = w; in mcpcia_iowrite16()
326 return *(vuip)addr; in mcpcia_ioread32()
336 *(vuip)addr = b; in mcpcia_iowrite32()
385 #undef vuip macro
H A Dcore_cia.h342 #define vuip volatile unsigned int __force * macro
374 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite8()
404 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite16()
412 return *(vuip)addr; in cia_ioread32()
420 *(vuip)addr = b; in cia_iowrite32()
482 #undef vuip macro
H A Dcore_lca.h220 #define vuip volatile unsigned int __force * macro
266 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite8()
302 *(vuip) ((addr << 5) + base_and_type) = w; in lca_iowrite16()
310 return *(vuip)addr; in lca_ioread32()
318 *(vuip)addr = b; in lca_iowrite32()
359 #undef vuip macro
H A Dcore_apecs.h375 #define vuip volatile unsigned int __force * macro
420 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite8()
456 *(vuip) ((addr << 5) + base_and_type) = w; in apecs_iowrite16()
464 return *(vuip)addr; in apecs_ioread32()
472 *(vuip)addr = b; in apecs_iowrite32()
515 #undef vuip macro

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